From: chandanu@codeaurora.org
To: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>,
Taniya Das <tdas@codeaurora.org>,
Andy Gross <andy.gross@linaro.org>,
David Brown <david.brown@linaro.org>,
Rajendra Nayak <rnayak@codeaurora.org>,
linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-msm-owner@vger.kernel.org
Subject: Re: [PATCH v1 2/2] clk: qcom : dispcc: Add support for display port clocks
Date: Sun, 11 Nov 2018 19:41:56 -0800 [thread overview]
Message-ID: <b3882909df919f084fc580fcaa88985d@codeaurora.org> (raw)
In-Reply-To: <154152409835.88331.14046185859724133804@swboyd.mtv.corp.google.com>
On 2018-11-06 09:08, Stephen Boyd wrote:
> Quoting Taniya Das (2018-10-31 22:02:22)
>> + Chandan from Display Port team,
>>
>> On 10/30/2018 10:03 PM, Stephen Boyd wrote:
>> > Also, those
>> > numbers look like gigabits per second (Gbit/s) for the DP spec which
>> > isn't exactly the same as a clk frequency. What frequency does the PLL
>> > run at for these various DP link speeds?
>> >
>> Could you please help with the above query from Stephen?
Hello Stephen,
For DP link speed of 5.4Gbit/s, the PLL will be running at 10.8 Ghz. For
all
the other DP link speeds, the PLL will be running at 8.1 Ghz.
>
> Can I safely assume that it matches the link rate shown on Wikipedia
> for
> display port[1]? I.e.
>
> RBR (Reduced Bit Rate): 1.62 Gbit/s bandwidth per lane (162 MHz link
> symbol rate)
> HBR (High Bit Rate): 2.70 Gbit/s bandwidth per lane (270 MHz link
> symbol rate)
> HBR2 (High Bit Rate 2): 5.40 Gbit/s bandwidth per lane (540 MHz link
> symbol rate), introduced in DP 1.2
> HBR3 (High Bit Rate 3): 8.10 Gbit/s bandwidth per lane (810 MHz link
> symbol rate), introduced in DP 1.3
>
> So then they're MHz but the table is written in kHz when it should be
> written in Hz. Either way, the table can be removed and then we just
> need to fix the DP PHY PLL code to accept Hz instead of kHz.
>
> [1] https://en.wikipedia.org/wiki/DisplayPort#Main_link
next prev parent reply other threads:[~2018-11-12 3:41 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-09 13:57 [PATCH v1 0/2] Add support for display port clocks and clock ops Taniya Das
2018-10-09 13:57 ` [PATCH v1 1/2] clk: qcom: rcg2: Add support for display port " Taniya Das
2018-10-09 20:46 ` Stephen Boyd
2018-10-19 10:31 ` Taniya Das
2018-10-09 13:57 ` [PATCH v1 2/2] clk: qcom : dispcc: Add support for display port clocks Taniya Das
2018-10-09 20:34 ` Stephen Boyd
2018-10-19 10:34 ` Taniya Das
2018-10-28 10:34 ` Taniya Das
2018-10-29 18:43 ` Stephen Boyd
2018-10-30 6:01 ` Taniya Das
2018-10-30 16:33 ` Stephen Boyd
2018-11-01 5:02 ` Taniya Das
2018-11-06 17:08 ` Stephen Boyd
2018-11-12 3:41 ` chandanu [this message]
2019-02-02 0:05 ` chandanu
2019-07-15 22:59 ` Stephen Boyd
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