* [PATCH v3 0/3] Add functions to operate USB PHY related clock.
@ 2020-06-30 16:38 周琰杰 (Zhou Yanjie)
2020-06-30 16:38 ` [PATCH v3 1/3] clk: JZ4780: Add functions for enable and disable USB PHY 周琰杰 (Zhou Yanjie)
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2020-06-30 16:38 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, sboyd, paul, mturquette, dongsheng.qiu, aric.pzqi,
rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin
v2->v3:
1.Remove the wrong "WARN()".
2.Remove extra blank line.
3.Fix wrong parameters in recalc_rate/set_rate functions.
周琰杰 (Zhou Yanjie) (3):
clk: JZ4780: Add functions for enable and disable USB PHY.
clk: JZ4780: Reformat the code to align it.
clk: X1000: Add support for calculat REFCLK of USB PHY.
drivers/clk/ingenic/jz4780-cgu.c | 153 ++++++++++++++++++++-------------------
drivers/clk/ingenic/x1000-cgu.c | 84 ++++++++++++++++++++-
2 files changed, 162 insertions(+), 75 deletions(-)
--
2.11.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v3 1/3] clk: JZ4780: Add functions for enable and disable USB PHY.
2020-06-30 16:38 [PATCH v3 0/3] Add functions to operate USB PHY related clock 周琰杰 (Zhou Yanjie)
@ 2020-06-30 16:38 ` 周琰杰 (Zhou Yanjie)
2020-06-30 16:38 ` [PATCH v3 2/3] clk: JZ4780: Reformat the code to align it 周琰杰 (Zhou Yanjie)
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2020-06-30 16:38 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, sboyd, paul, mturquette, dongsheng.qiu, aric.pzqi,
rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin
Add new functions to "jz4780_otg_phy_ops" to enable or disable the
USB PHY in the JZ4780 SoC.
Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
Notes:
v1->v2:
1.Use "WARN()" instead "BUG()".
2.Move the reformat part ot the new patch.
3.Remove unnecessary get_parent/set_parent functions.
v2->v3:
1.Remove the wrong "WARN()".
2.Remove extra blank line.
drivers/clk/ingenic/jz4780-cgu.c | 65 +++++++++++++++++++++-------------------
1 file changed, 35 insertions(+), 30 deletions(-)
diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c
index 6c5b8029cc8a..cf3f7f87e7a6 100644
--- a/drivers/clk/ingenic/jz4780-cgu.c
+++ b/drivers/clk/ingenic/jz4780-cgu.c
@@ -4,6 +4,7 @@
*
* Copyright (c) 2013-2015 Imagination Technologies
* Author: Paul Burton <paul.burton@mips.com>
+ * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
*/
#include <linux/clk-provider.h>
@@ -59,6 +60,7 @@
#define USBPCR_VBUSVLDEXT BIT(24)
#define USBPCR_VBUSVLDEXTSEL BIT(23)
#define USBPCR_POR BIT(22)
+#define USBPCR_SIDDQ BIT(21)
#define USBPCR_OTG_DISABLE BIT(20)
#define USBPCR_COMPDISTUNE_MASK (0x7 << 17)
#define USBPCR_OTGTUNE_MASK (0x7 << 14)
@@ -100,32 +102,6 @@
static struct ingenic_cgu *cgu;
-static u8 jz4780_otg_phy_get_parent(struct clk_hw *hw)
-{
- /* we only use CLKCORE, revisit if that ever changes */
- return 0;
-}
-
-static int jz4780_otg_phy_set_parent(struct clk_hw *hw, u8 idx)
-{
- unsigned long flags;
- u32 usbpcr1;
-
- if (idx > 0)
- return -EINVAL;
-
- spin_lock_irqsave(&cgu->lock, flags);
-
- usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
- usbpcr1 &= ~USBPCR1_REFCLKSEL_MASK;
- /* we only use CLKCORE */
- usbpcr1 |= USBPCR1_REFCLKSEL_CORE;
- writel(usbpcr1, cgu->base + CGU_REG_USBPCR1);
-
- spin_unlock_irqrestore(&cgu->lock, flags);
- return 0;
-}
-
static unsigned long jz4780_otg_phy_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
@@ -149,7 +125,6 @@ static unsigned long jz4780_otg_phy_recalc_rate(struct clk_hw *hw,
return 19200000;
}
- BUG();
return parent_rate;
}
@@ -206,13 +181,43 @@ static int jz4780_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate,
return 0;
}
-static const struct clk_ops jz4780_otg_phy_ops = {
- .get_parent = jz4780_otg_phy_get_parent,
- .set_parent = jz4780_otg_phy_set_parent,
+static int jz4780_otg_phy_enable(struct clk_hw *hw)
+{
+ void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
+ void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
+
+ writel(readl(reg_opcr) | OPCR_SPENDN0, reg_opcr);
+ writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ, reg_usbpcr);
+ return 0;
+}
+
+static void jz4780_otg_phy_disable(struct clk_hw *hw)
+{
+ void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
+ void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
+ writel(readl(reg_opcr) & ~OPCR_SPENDN0, reg_opcr);
+ writel(readl(reg_usbpcr) | USBPCR_OTG_DISABLE | USBPCR_SIDDQ, reg_usbpcr);
+}
+
+static int jz4780_otg_phy_is_enabled(struct clk_hw *hw)
+{
+ void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
+ void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
+
+ return (readl(reg_opcr) & OPCR_SPENDN0) &&
+ !(readl(reg_usbpcr) & USBPCR_SIDDQ) &&
+ !(readl(reg_usbpcr) & USBPCR_OTG_DISABLE);
+}
+
+static const struct clk_ops jz4780_otg_phy_ops = {
.recalc_rate = jz4780_otg_phy_recalc_rate,
.round_rate = jz4780_otg_phy_round_rate,
.set_rate = jz4780_otg_phy_set_rate,
+
+ .enable = jz4780_otg_phy_enable,
+ .disable = jz4780_otg_phy_disable,
+ .is_enabled = jz4780_otg_phy_is_enabled,
};
static int jz4780_core1_enable(struct clk_hw *hw)
--
2.11.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v3 2/3] clk: JZ4780: Reformat the code to align it.
2020-06-30 16:38 [PATCH v3 0/3] Add functions to operate USB PHY related clock 周琰杰 (Zhou Yanjie)
2020-06-30 16:38 ` [PATCH v3 1/3] clk: JZ4780: Add functions for enable and disable USB PHY 周琰杰 (Zhou Yanjie)
@ 2020-06-30 16:38 ` 周琰杰 (Zhou Yanjie)
2020-06-30 16:38 ` [PATCH v3 3/3] clk: X1000: Add support for calculat REFCLK of USB PHY 周琰杰 (Zhou Yanjie)
2020-07-25 4:01 ` [PATCH v3 0/3] Add functions to operate USB PHY related clock Zhou Yanjie
3 siblings, 0 replies; 7+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2020-06-30 16:38 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, sboyd, paul, mturquette, dongsheng.qiu, aric.pzqi,
rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin
Reformat the code (add one level of indentation before the values),
to align the code in the macro definition section.
Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
Notes:
v2:
New patch.
v2->v3:
No change.
drivers/clk/ingenic/jz4780-cgu.c | 90 ++++++++++++++++++++--------------------
1 file changed, 45 insertions(+), 45 deletions(-)
diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c
index cf3f7f87e7a6..abd8d6d78590 100644
--- a/drivers/clk/ingenic/jz4780-cgu.c
+++ b/drivers/clk/ingenic/jz4780-cgu.c
@@ -20,50 +20,50 @@
/* CGU register offsets */
#define CGU_REG_CLOCKCONTROL 0x00
-#define CGU_REG_LCR 0x04
-#define CGU_REG_APLL 0x10
-#define CGU_REG_MPLL 0x14
-#define CGU_REG_EPLL 0x18
-#define CGU_REG_VPLL 0x1c
-#define CGU_REG_CLKGR0 0x20
-#define CGU_REG_OPCR 0x24
-#define CGU_REG_CLKGR1 0x28
-#define CGU_REG_DDRCDR 0x2c
-#define CGU_REG_VPUCDR 0x30
-#define CGU_REG_USBPCR 0x3c
-#define CGU_REG_USBRDT 0x40
-#define CGU_REG_USBVBFIL 0x44
-#define CGU_REG_USBPCR1 0x48
-#define CGU_REG_LP0CDR 0x54
-#define CGU_REG_I2SCDR 0x60
-#define CGU_REG_LP1CDR 0x64
-#define CGU_REG_MSC0CDR 0x68
-#define CGU_REG_UHCCDR 0x6c
-#define CGU_REG_SSICDR 0x74
-#define CGU_REG_CIMCDR 0x7c
-#define CGU_REG_PCMCDR 0x84
-#define CGU_REG_GPUCDR 0x88
-#define CGU_REG_HDMICDR 0x8c
-#define CGU_REG_MSC1CDR 0xa4
-#define CGU_REG_MSC2CDR 0xa8
-#define CGU_REG_BCHCDR 0xac
-#define CGU_REG_CLOCKSTATUS 0xd4
+#define CGU_REG_LCR 0x04
+#define CGU_REG_APLL 0x10
+#define CGU_REG_MPLL 0x14
+#define CGU_REG_EPLL 0x18
+#define CGU_REG_VPLL 0x1c
+#define CGU_REG_CLKGR0 0x20
+#define CGU_REG_OPCR 0x24
+#define CGU_REG_CLKGR1 0x28
+#define CGU_REG_DDRCDR 0x2c
+#define CGU_REG_VPUCDR 0x30
+#define CGU_REG_USBPCR 0x3c
+#define CGU_REG_USBRDT 0x40
+#define CGU_REG_USBVBFIL 0x44
+#define CGU_REG_USBPCR1 0x48
+#define CGU_REG_LP0CDR 0x54
+#define CGU_REG_I2SCDR 0x60
+#define CGU_REG_LP1CDR 0x64
+#define CGU_REG_MSC0CDR 0x68
+#define CGU_REG_UHCCDR 0x6c
+#define CGU_REG_SSICDR 0x74
+#define CGU_REG_CIMCDR 0x7c
+#define CGU_REG_PCMCDR 0x84
+#define CGU_REG_GPUCDR 0x88
+#define CGU_REG_HDMICDR 0x8c
+#define CGU_REG_MSC1CDR 0xa4
+#define CGU_REG_MSC2CDR 0xa8
+#define CGU_REG_BCHCDR 0xac
+#define CGU_REG_CLOCKSTATUS 0xd4
/* bits within the OPCR register */
-#define OPCR_SPENDN0 BIT(7)
-#define OPCR_SPENDN1 BIT(6)
+#define OPCR_SPENDN0 BIT(7)
+#define OPCR_SPENDN1 BIT(6)
/* bits within the USBPCR register */
-#define USBPCR_USB_MODE BIT(31)
+#define USBPCR_USB_MODE BIT(31)
#define USBPCR_IDPULLUP_MASK (0x3 << 28)
-#define USBPCR_COMMONONN BIT(25)
-#define USBPCR_VBUSVLDEXT BIT(24)
+#define USBPCR_COMMONONN BIT(25)
+#define USBPCR_VBUSVLDEXT BIT(24)
#define USBPCR_VBUSVLDEXTSEL BIT(23)
-#define USBPCR_POR BIT(22)
-#define USBPCR_SIDDQ BIT(21)
-#define USBPCR_OTG_DISABLE BIT(20)
+#define USBPCR_POR BIT(22)
+#define USBPCR_SIDDQ BIT(21)
+#define USBPCR_OTG_DISABLE BIT(20)
#define USBPCR_COMPDISTUNE_MASK (0x7 << 17)
-#define USBPCR_OTGTUNE_MASK (0x7 << 14)
+#define USBPCR_OTGTUNE_MASK (0x7 << 14)
#define USBPCR_SQRXTUNE_MASK (0x7 << 11)
#define USBPCR_TXFSLSTUNE_MASK (0xf << 7)
#define USBPCR_TXPREEMPHTUNE BIT(6)
@@ -80,13 +80,13 @@
#define USBPCR1_REFCLKDIV_48 (0x2 << USBPCR1_REFCLKDIV_SHIFT)
#define USBPCR1_REFCLKDIV_24 (0x1 << USBPCR1_REFCLKDIV_SHIFT)
#define USBPCR1_REFCLKDIV_12 (0x0 << USBPCR1_REFCLKDIV_SHIFT)
-#define USBPCR1_USB_SEL BIT(28)
-#define USBPCR1_WORD_IF0 BIT(19)
-#define USBPCR1_WORD_IF1 BIT(18)
+#define USBPCR1_USB_SEL BIT(28)
+#define USBPCR1_WORD_IF0 BIT(19)
+#define USBPCR1_WORD_IF1 BIT(18)
/* bits within the USBRDT register */
-#define USBRDT_VBFIL_LD_EN BIT(25)
-#define USBRDT_USBRDT_MASK 0x7fffff
+#define USBRDT_VBFIL_LD_EN BIT(25)
+#define USBRDT_USBRDT_MASK 0x7fffff
/* bits within the USBVBFIL register */
#define USBVBFIL_IDDIGFIL_SHIFT 16
@@ -94,11 +94,11 @@
#define USBVBFIL_USBVBFIL_MASK (0xffff)
/* bits within the LCR register */
-#define LCR_PD_SCPU BIT(31)
-#define LCR_SCPUS BIT(27)
+#define LCR_PD_SCPU BIT(31)
+#define LCR_SCPUS BIT(27)
/* bits within the CLKGR1 register */
-#define CLKGR1_CORE1 BIT(15)
+#define CLKGR1_CORE1 BIT(15)
static struct ingenic_cgu *cgu;
--
2.11.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v3 3/3] clk: X1000: Add support for calculat REFCLK of USB PHY.
2020-06-30 16:38 [PATCH v3 0/3] Add functions to operate USB PHY related clock 周琰杰 (Zhou Yanjie)
2020-06-30 16:38 ` [PATCH v3 1/3] clk: JZ4780: Add functions for enable and disable USB PHY 周琰杰 (Zhou Yanjie)
2020-06-30 16:38 ` [PATCH v3 2/3] clk: JZ4780: Reformat the code to align it 周琰杰 (Zhou Yanjie)
@ 2020-06-30 16:38 ` 周琰杰 (Zhou Yanjie)
2020-07-25 4:01 ` [PATCH v3 0/3] Add functions to operate USB PHY related clock Zhou Yanjie
3 siblings, 0 replies; 7+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2020-06-30 16:38 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, sboyd, paul, mturquette, dongsheng.qiu, aric.pzqi,
rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin
Add functions for calculat the rate of REFCLK, which is needed by
USB PHY in Ingenic X1000 SoC.
Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
Notes:
v1->v2:
1.Use "WARN()" instead "BUG()".
2.Remove unnecessary get_parent/set_parent functions.
v2->v3:
1.Remove the wrong "WARN()";
2.Fix wrong parameters in recalc_rate/set_rate functions.
drivers/clk/ingenic/x1000-cgu.c | 84 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 83 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c
index 453f3323cb99..38143bcd4cbd 100644
--- a/drivers/clk/ingenic/x1000-cgu.c
+++ b/drivers/clk/ingenic/x1000-cgu.c
@@ -48,8 +48,87 @@
#define USBPCR_SIDDQ BIT(21)
#define USBPCR_OTG_DISABLE BIT(20)
+/* bits within the USBPCR1 register */
+#define USBPCR1_REFCLKSEL_SHIFT 26
+#define USBPCR1_REFCLKSEL_MASK (0x3 << USBPCR1_REFCLKSEL_SHIFT)
+#define USBPCR1_REFCLKSEL_CORE (0x2 << USBPCR1_REFCLKSEL_SHIFT)
+#define USBPCR1_REFCLKDIV_SHIFT 24
+#define USBPCR1_REFCLKDIV_MASK (0x3 << USBPCR1_REFCLKDIV_SHIFT)
+#define USBPCR1_REFCLKDIV_48 (0x2 << USBPCR1_REFCLKDIV_SHIFT)
+#define USBPCR1_REFCLKDIV_24 (0x1 << USBPCR1_REFCLKDIV_SHIFT)
+#define USBPCR1_REFCLKDIV_12 (0x0 << USBPCR1_REFCLKDIV_SHIFT)
+
static struct ingenic_cgu *cgu;
+static unsigned long x1000_otg_phy_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ u32 usbpcr1;
+ unsigned refclk_div;
+
+ usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
+ refclk_div = usbpcr1 & USBPCR1_REFCLKDIV_MASK;
+
+ switch (refclk_div) {
+ case USBPCR1_REFCLKDIV_12:
+ return 12000000;
+
+ case USBPCR1_REFCLKDIV_24:
+ return 24000000;
+
+ case USBPCR1_REFCLKDIV_48:
+ return 48000000;
+ }
+
+ return parent_rate;
+}
+
+static long x1000_otg_phy_round_rate(struct clk_hw *hw, unsigned long req_rate,
+ unsigned long *parent_rate)
+{
+ if (req_rate < 18000000)
+ return 12000000;
+
+ if (req_rate < 36000000)
+ return 24000000;
+
+ return 48000000;
+}
+
+static int x1000_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate,
+ unsigned long parent_rate)
+{
+ unsigned long flags;
+ u32 usbpcr1, div_bits;
+
+ switch (req_rate) {
+ case 12000000:
+ div_bits = USBPCR1_REFCLKDIV_12;
+ break;
+
+ case 24000000:
+ div_bits = USBPCR1_REFCLKDIV_24;
+ break;
+
+ case 48000000:
+ div_bits = USBPCR1_REFCLKDIV_48;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&cgu->lock, flags);
+
+ usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
+ usbpcr1 &= ~USBPCR1_REFCLKDIV_MASK;
+ usbpcr1 |= div_bits;
+ writel(usbpcr1, cgu->base + CGU_REG_USBPCR1);
+
+ spin_unlock_irqrestore(&cgu->lock, flags);
+ return 0;
+}
+
static int x1000_usb_phy_enable(struct clk_hw *hw)
{
void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
@@ -80,6 +159,10 @@ static int x1000_usb_phy_is_enabled(struct clk_hw *hw)
}
static const struct clk_ops x1000_otg_phy_ops = {
+ .recalc_rate = x1000_otg_phy_recalc_rate,
+ .round_rate = x1000_otg_phy_round_rate,
+ .set_rate = x1000_otg_phy_set_rate,
+
.enable = x1000_usb_phy_enable,
.disable = x1000_usb_phy_disable,
.is_enabled = x1000_usb_phy_is_enabled,
@@ -144,7 +227,6 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
},
},
-
/* Custom (SoC-specific) OTG PHY */
[X1000_CLK_OTGPHY] = {
--
2.11.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v3 0/3] Add functions to operate USB PHY related clock.
2020-06-30 16:38 [PATCH v3 0/3] Add functions to operate USB PHY related clock 周琰杰 (Zhou Yanjie)
` (2 preceding siblings ...)
2020-06-30 16:38 ` [PATCH v3 3/3] clk: X1000: Add support for calculat REFCLK of USB PHY 周琰杰 (Zhou Yanjie)
@ 2020-07-25 4:01 ` Zhou Yanjie
2020-07-28 1:19 ` Stephen Boyd
3 siblings, 1 reply; 7+ messages in thread
From: Zhou Yanjie @ 2020-07-25 4:01 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, sboyd, paul, mturquette, dongsheng.qiu, aric.pzqi,
rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin
Gentle ping.
在 2020/7/1 上午12:38, 周琰杰 (Zhou Yanjie) 写道:
> v2->v3:
> 1.Remove the wrong "WARN()".
> 2.Remove extra blank line.
> 3.Fix wrong parameters in recalc_rate/set_rate functions.
>
> 周琰杰 (Zhou Yanjie) (3):
> clk: JZ4780: Add functions for enable and disable USB PHY.
> clk: JZ4780: Reformat the code to align it.
> clk: X1000: Add support for calculat REFCLK of USB PHY.
>
> drivers/clk/ingenic/jz4780-cgu.c | 153 ++++++++++++++++++++-------------------
> drivers/clk/ingenic/x1000-cgu.c | 84 ++++++++++++++++++++-
> 2 files changed, 162 insertions(+), 75 deletions(-)
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 0/3] Add functions to operate USB PHY related clock.
2020-07-25 4:01 ` [PATCH v3 0/3] Add functions to operate USB PHY related clock Zhou Yanjie
@ 2020-07-28 1:19 ` Stephen Boyd
2020-07-28 1:46 ` Paul Cercueil
0 siblings, 1 reply; 7+ messages in thread
From: Stephen Boyd @ 2020-07-28 1:19 UTC (permalink / raw)
To: Zhou Yanjie, linux-clk
Cc: linux-kernel, paul, mturquette, dongsheng.qiu, aric.pzqi,
rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin
Quoting Zhou Yanjie (2020-07-24 21:01:38)
> Gentle ping.
>
I was hoping Paul would review but I guess not. I applied the patches to
clk-next.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 0/3] Add functions to operate USB PHY related clock.
2020-07-28 1:19 ` Stephen Boyd
@ 2020-07-28 1:46 ` Paul Cercueil
0 siblings, 0 replies; 7+ messages in thread
From: Paul Cercueil @ 2020-07-28 1:46 UTC (permalink / raw)
To: Stephen Boyd
Cc: Zhou Yanjie, linux-clk, linux-kernel, mturquette, dongsheng.qiu,
aric.pzqi, rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin
Le lun. 27 juil. 2020 à 18:19, Stephen Boyd <sboyd@kernel.org> a
écrit :
> Quoting Zhou Yanjie (2020-07-24 21:01:38)
>> Gentle ping.
>>
>
> I was hoping Paul would review but I guess not. I applied the patches
> to
> clk-next.
I did receive the "gentle ping" and was going to review it soonish :(
I said for v1 that I don't like how it comes out with magic Hz values...
-Paul
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-07-28 1:46 UTC | newest]
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2020-06-30 16:38 [PATCH v3 0/3] Add functions to operate USB PHY related clock 周琰杰 (Zhou Yanjie)
2020-06-30 16:38 ` [PATCH v3 1/3] clk: JZ4780: Add functions for enable and disable USB PHY 周琰杰 (Zhou Yanjie)
2020-06-30 16:38 ` [PATCH v3 2/3] clk: JZ4780: Reformat the code to align it 周琰杰 (Zhou Yanjie)
2020-06-30 16:38 ` [PATCH v3 3/3] clk: X1000: Add support for calculat REFCLK of USB PHY 周琰杰 (Zhou Yanjie)
2020-07-25 4:01 ` [PATCH v3 0/3] Add functions to operate USB PHY related clock Zhou Yanjie
2020-07-28 1:19 ` Stephen Boyd
2020-07-28 1:46 ` Paul Cercueil
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