From: Stephen Warren <swarren@wwwdotorg.org>
To: Dmitry Osipenko <digetx@gmail.com>,
Sowjanya Komatineni <skomatineni@nvidia.com>
Cc: thierry.reding@gmail.com, jonathanh@nvidia.com,
tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com,
linus.walleij@linaro.org, stefan@agner.ch, mark.rutland@arm.com,
pdeschrijver@nvidia.com, pgaikwad@nvidia.com, sboyd@kernel.org,
linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org,
jckuo@nvidia.com, josephl@nvidia.com, talho@nvidia.com,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
mperttunen@nvidia.com, spatra@nvidia.com, robh+dt@kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH V3 02/17] pinctrl: tegra: add suspend and resume support
Date: Tue, 18 Jun 2019 09:41:03 -0600 [thread overview]
Message-ID: <fd415362-7479-6f98-c8db-1b7758fd3f1d@wwwdotorg.org> (raw)
In-Reply-To: <a23ffbae-dd85-c023-7aae-3b81e0b17ebc@gmail.com>
On 6/18/19 3:30 AM, Dmitry Osipenko wrote:
> 18.06.2019 12:22, Dmitry Osipenko пишет:
>> 18.06.2019 10:46, Sowjanya Komatineni пишет:
>>> This patch adds suspend and resume support for Tegra pinctrl driver
>>> and registers them to syscore so the pinmux settings are restored
>>> before the devices resume.
>>>
>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>> ---
>>> drivers/pinctrl/tegra/pinctrl-tegra.c | 62 ++++++++++++++++++++++++++++++++
>>> drivers/pinctrl/tegra/pinctrl-tegra.h | 5 +++
>>> drivers/pinctrl/tegra/pinctrl-tegra114.c | 1 +
>>> drivers/pinctrl/tegra/pinctrl-tegra124.c | 1 +
>>> drivers/pinctrl/tegra/pinctrl-tegra20.c | 1 +
>>> drivers/pinctrl/tegra/pinctrl-tegra210.c | 13 +++++++
>>> drivers/pinctrl/tegra/pinctrl-tegra30.c | 1 +
>>> 7 files changed, 84 insertions(+)
>>>
>>> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
>>> index 34596b246578..ceced30d8bd1 100644
>>> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c
>>> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
>>> @@ -20,11 +20,16 @@
>>> #include <linux/pinctrl/pinmux.h>
>>> #include <linux/pinctrl/pinconf.h>
>>> #include <linux/slab.h>
>>> +#include <linux/syscore_ops.h>
>>>
>>> #include "../core.h"
>>> #include "../pinctrl-utils.h"
>>> #include "pinctrl-tegra.h"
>>>
>>> +#define EMMC2_PAD_CFGPADCTRL_0 0x1c8
>>> +#define EMMC4_PAD_CFGPADCTRL_0 0x1e0
>>> +#define EMMC_DPD_PARKING (0x1fff << 14)
>>> +
>>> static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
>>> {
>>> return readl(pmx->regs[bank] + reg);
>>> @@ -619,6 +624,48 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
>>> pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
>>> }
>>> }
>>> +
>>> + if (pmx->soc->has_park_padcfg) {
>>> + val = pmx_readl(pmx, 0, EMMC2_PAD_CFGPADCTRL_0);
>>> + val &= ~EMMC_DPD_PARKING;
>>> + pmx_writel(pmx, val, 0, EMMC2_PAD_CFGPADCTRL_0);
>>> +
>>> + val = pmx_readl(pmx, 0, EMMC4_PAD_CFGPADCTRL_0);
>>> + val &= ~EMMC_DPD_PARKING;
>>> + pmx_writel(pmx, val, 0, EMMC4_PAD_CFGPADCTRL_0);
>>> + }
>>> +}
>>
>> Is there any reason why parked_bit can't be changed to parked_bitmask like I was
>> asking in a comment to v2?
>>
>> I suppose that it's more preferable to keep pinctrl-tegra.c platform-agnostic for
>> consistency when possible, hence adding platform specifics here should be discouraged.
>> And then the parked_bitmask will also result in a proper hardware description in the code.
>>
>
> I'm now also vaguely recalling that Stephen Warren had some kind of a "code generator"
> for the pinctrl drivers. So I guess all those tables were auto-generated initially.
>
> Stephen, maybe you could adjust the generator to take into account the bitmask (of
> course if that's a part of the generated code) and then re-gen it all for Sowjanya?
https://github.com/NVIDIA/tegra-pinmux-scripts holds the scripts that
generate tegra-pinctrlNNN.c. See soc-to-kernel-pinctrl-driver.py.
IIRC, tegra-pinctrl.c (the core file) isn't auto-generated. Sowjanya is
welcome to send a patch to that repo if the code needs to be updated.
next prev parent reply other threads:[~2019-06-18 15:48 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-18 7:46 [PATCH V3 00/17] SC7 entry and exit support for Tegra210 Sowjanya Komatineni
2019-06-18 7:46 ` [PATCH V3 01/17] irqchip: tegra: do not disable COP IRQ during suspend Sowjanya Komatineni
2019-06-18 9:19 ` Marc Zyngier
2019-06-18 10:58 ` Thierry Reding
2019-06-18 7:46 ` [PATCH V3 02/17] pinctrl: tegra: add suspend and resume support Sowjanya Komatineni
2019-06-18 9:22 ` Dmitry Osipenko
2019-06-18 9:30 ` Dmitry Osipenko
2019-06-18 15:41 ` Stephen Warren [this message]
2019-06-18 16:50 ` Sowjanya Komatineni
2019-06-18 17:34 ` Sowjanya Komatineni
2019-06-18 20:00 ` Dmitry Osipenko
2019-06-18 20:04 ` Sowjanya Komatineni
2019-06-19 8:31 ` Thierry Reding
2019-06-19 8:40 ` Dmitry Osipenko
2019-06-19 8:33 ` Thierry Reding
2019-06-19 8:57 ` Thierry Reding
2019-06-18 11:31 ` Thierry Reding
2019-06-18 7:46 ` [PATCH V3 03/17] gpio: tegra: use resume_noirq for tegra gpio resume Sowjanya Komatineni
2019-06-18 11:39 ` Thierry Reding
2019-06-18 7:46 ` [PATCH V3 04/17] clk: tegra: save and restore divider rate Sowjanya Komatineni
2019-06-18 11:40 ` Thierry Reding
2019-06-18 7:46 ` [PATCH V3 05/17] clk: tegra: pllout: save and restore pllout context Sowjanya Komatineni
2019-06-18 11:41 ` Thierry Reding
2019-06-18 7:46 ` [PATCH V3 06/17] clk: tegra: pll: save and restore pll context Sowjanya Komatineni
2019-06-18 11:45 ` Thierry Reding
2019-06-25 20:46 ` Stephen Boyd
2019-06-25 21:22 ` Sowjanya Komatineni
2019-06-18 7:46 ` [PATCH V3 07/17] clk: tegra: save and restore CPU and System clocks context Sowjanya Komatineni
2019-06-18 11:48 ` Thierry Reding
2019-06-18 7:46 ` [PATCH V3 08/17] clk: tegra: add support for peripheral clock suspend and resume Sowjanya Komatineni
2019-06-18 11:50 ` Thierry Reding
2019-06-18 7:46 ` [PATCH V3 09/17] clk: tegra: support for saving and restoring OSC clock context Sowjanya Komatineni
2019-06-18 11:51 ` Thierry Reding
2019-06-18 7:46 ` [PATCH V3 10/17] clk: tegra: add suspend resume support for DFLL Sowjanya Komatineni
2019-06-18 11:59 ` Thierry Reding
2019-06-18 7:46 ` [PATCH V3 11/17] clk: tegra210: support for Tegra210 clocks suspend and resume Sowjanya Komatineni
2019-06-18 12:16 ` Thierry Reding
2019-06-18 17:58 ` Sowjanya Komatineni
2019-06-19 8:15 ` Thierry Reding
2019-06-21 20:44 ` Sowjanya Komatineni
2019-06-18 7:46 ` [PATCH V3 12/17] soc/tegra: pmc: allow support for more tegra wake Sowjanya Komatineni
2019-06-18 9:26 ` Marc Zyngier
2019-06-18 7:46 ` [PATCH V3 13/17] soc/tegra: pmc: add pmc wake support for tegra210 Sowjanya Komatineni
2019-06-18 7:46 ` [PATCH V3 14/17] arm64: tegra: enable wake from deep sleep on RTC alarm Sowjanya Komatineni
2019-06-18 7:46 ` [PATCH V3 15/17] soc/tegra: pmc: configure core power request polarity Sowjanya Komatineni
2019-06-18 7:46 ` [PATCH V3 16/17] soc/tegra: pmc: configure deep sleep control settings Sowjanya Komatineni
2019-06-18 7:46 ` [PATCH V3 17/17] arm64: dts: tegra210-p2180: Jetson TX1 SC7 timings Sowjanya Komatineni
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=fd415362-7479-6f98-c8db-1b7758fd3f1d@wwwdotorg.org \
--to=swarren@wwwdotorg.org \
--cc=devicetree@vger.kernel.org \
--cc=digetx@gmail.com \
--cc=jason@lakedaemon.net \
--cc=jckuo@nvidia.com \
--cc=jonathanh@nvidia.com \
--cc=josephl@nvidia.com \
--cc=linus.walleij@linaro.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=marc.zyngier@arm.com \
--cc=mark.rutland@arm.com \
--cc=mperttunen@nvidia.com \
--cc=pdeschrijver@nvidia.com \
--cc=pgaikwad@nvidia.com \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
--cc=skomatineni@nvidia.com \
--cc=spatra@nvidia.com \
--cc=stefan@agner.ch \
--cc=talho@nvidia.com \
--cc=tglx@linutronix.de \
--cc=thierry.reding@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).