Re: [PATCH v6 08/42] x86/sev-es: initialize sev_status/features within #VC handler

[Michael Roth <michael.roth@amd.com>]

On Thu, Oct 21, 2021 at 04:39:31PM +0200, Borislav Petkov wrote:
> On Wed, Oct 20, 2021 at 09:05:42PM -0500, Michael Roth wrote:
> > According to the APM at least, (Rev 3.37, 15.34.10, "SEV_STATUS MSR"), the
> > SEV MSR is the appropriate source for guests to use. This is what is used
> > in the EFI code as well. So that seems to be the right way to make the
> > initial determination.
> 
> Yap.
> 
> > There's a dependency there on the SEV CPUID bit however, since setting the
> > bit to 0 would generally result in a guest skipping the SEV MSR read and
> > assuming 0. So for SNP it would be more reliable to make use of the CPUID
> > table at that point, since it's less-susceptible to manipulation, or do the
> > #VC-based SEV MSR read (or both).
> 
> So the CPUID page is supplied by the firmware, right?

Yes.

> 
> Then, you parse it and see that the CPUID bit is 1, then you start using
> the SEV_STATUS MSR and all good.
> 
> If there *is* a CPUID page but that bit is 0, then you can safely assume
> that something is playing tricks on ya so you simply refuse booting.

I think that's a good way to deal with this.

I was going to suggest we could assume the presence of SEV status MSR by
virtue of EFI/bootloader/etc having provided a cc_blob, and just read it
right away to confirm this is SNP. But with your approach we could basically
just set up the table early, based on the presence of the cc_blob, and do all
the checks in sme_enable() in the same order as with SEV/SEV-ES, then just
have additional sanity checks against the CPUID/MSR response values to
ensure the SNP bits are present for the cases where a cpuid table / cc_blob
are provided.

I'll work on implementing things in this way and see how it goes.

> 
> > Fully-unencrypted should result in a crash due to the reasons below.
> 
> Crash is a good thing in confidential computing. :)
> 
> > But there may exist some carefully crafted outside influences that could
> > goad the guest into, perhaps, not marking certain pages as private. The
> > best that can be done to prevent that is to audit/harden all the code in the
> > boot stack so that it is less susceptible to that kind of outside
> > manipulation (via mechanisms like SEV-ES, SNP page validation, SNP CPUID
> > table, SNP restricted injection, etc.)
> 
> So to me I wonder why would one use anything *else* but an SNP guest. We
> all know that those previous technologies were just the stepping stones
> towards SNP.

Yah, I think ultimately that's where things are headed.

> 
> > Then of course that boot stack needs to be part of the attestation process
> > to provide any meaningful assurances about the resulting guest state.
> >
> > Outside of the boot stack the guest owner might take some extra precautions.
> > Perhaps custom some kernel driver to verify encryption/validated status of
> > guest pages, some checks against the CPUID table to verify it contains sane
> > values, but not really worth speculating on that aspect as it will be
> > ultimately dependent on how the cloud vendor decides to handle things after
> > boot.
> 
> Well, I've always advocated having a best-practices writeup somewhere
> goes a long way to explain this technology to people and how to get
> their feet wet. And there you can give hints how such verification could
> look like in detail...

Our security team is working on some initial reference designs / tooling
for attestation. It'll eventually make it's way to here:

  https://github.com/AMDESE/sev-guest

but it's still mostly an internal effort so nothing there ATM. But hopefully
that will fill in some of these gaps. But I agree some an accompanying best
practices document to highlight some of these considerations is also
something that should be considered, I'll need to check to see if there's
anything like that in the works already.

> 
> > That would indeed be useful. Perhaps as a nice big comment in sme_enable()
> > and/or the proposed sev_init() so that those invariants can be maintained,
> > or updated in sync with future changes. I'll look into that for the next
> > spin and check with Brijesh on the details.
> 
> There is Documentation/x86/amd-memory-encryption.rst, for example.

Makes sense, will work with Brijesh on this.

Thanks!

-Mike

> 
> -- 
> Regards/Gruss,
>     Boris.
> 
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