From: Brijesh Singh <brijesh.singh@amd.com>
To: <x86@kernel.org>, <linux-kernel@vger.kernel.org>,
<kvm@vger.kernel.org>, <linux-efi@vger.kernel.org>,
<platform-driver-x86@vger.kernel.org>,
<linux-coco@lists.linux.dev>, <linux-mm@kvack.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Joerg Roedel <jroedel@suse.de>,
Tom Lendacky <thomas.lendacky@amd.com>,
"H. Peter Anvin" <hpa@zytor.com>,
Ard Biesheuvel <ardb@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Sean Christopherson <seanjc@google.com>,
"Vitaly Kuznetsov" <vkuznets@redhat.com>,
Jim Mattson <jmattson@google.com>,
"Andy Lutomirski" <luto@kernel.org>,
Dave Hansen <dave.hansen@linux.intel.com>,
Sergio Lopez <slp@redhat.com>, Peter Gonda <pgonda@google.com>,
"Peter Zijlstra" <peterz@infradead.org>,
Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>,
David Rientjes <rientjes@google.com>,
Dov Murik <dovmurik@linux.ibm.com>,
Tobin Feldman-Fitzthum <tobin@ibm.com>,
Borislav Petkov <bp@alien8.de>,
Michael Roth <michael.roth@amd.com>,
Vlastimil Babka <vbabka@suse.cz>,
"Kirill A . Shutemov" <kirill@shutemov.name>,
Andi Kleen <ak@linux.intel.com>,
"Dr . David Alan Gilbert" <dgilbert@redhat.com>,
<tony.luck@intel.com>, <marcorr@google.com>,
<sathyanarayanan.kuppuswamy@linux.intel.com>,
Brijesh Singh <brijesh.singh@amd.com>
Subject: [PATCH v7 16/45] x86/sev: Register GHCB memory when SEV-SNP is active
Date: Wed, 10 Nov 2021 16:07:02 -0600 [thread overview]
Message-ID: <20211110220731.2396491-17-brijesh.singh@amd.com> (raw)
In-Reply-To: <20211110220731.2396491-1-brijesh.singh@amd.com>
The SEV-SNP guest is required to perform GHCB GPA registration. This is
because the hypervisor may prefer that a guest use a consistent and/or
specific GPA for the GHCB associated with a vCPU. For more information,
see the GHCB specification section GHCB GPA Registration.
During the boot, init_ghcb() allocates a per-cpu GHCB page. On very first
VC exception, the exception handler switch to using the per-cpu GHCB page
allocated during the init_ghcb(). The GHCB page must be registered in
the current vcpu context.
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
---
arch/x86/include/asm/sev.h | 2 +
arch/x86/kernel/cpu/common.c | 5 ++
arch/x86/kernel/head64.c | 3 +
arch/x86/kernel/sev.c | 116 ++++++++++++++++++++---------------
4 files changed, 77 insertions(+), 49 deletions(-)
diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h
index e37451849165..0df508374a35 100644
--- a/arch/x86/include/asm/sev.h
+++ b/arch/x86/include/asm/sev.h
@@ -122,6 +122,7 @@ static inline int pvalidate(unsigned long vaddr, bool rmp_psize, bool validate)
return rc;
}
+void sev_snp_register_ghcb(void);
#else
static inline void sev_es_ist_enter(struct pt_regs *regs) { }
static inline void sev_es_ist_exit(void) { }
@@ -130,6 +131,7 @@ static inline void sev_es_nmi_complete(void) { }
static inline int sev_es_efi_map_ghcbs(pgd_t *pgd) { return 0; }
static inline int pvalidate(unsigned long vaddr, bool rmp_psize, bool validate) { return 0; }
static inline int rmpadjust(unsigned long vaddr, bool rmp_psize, unsigned long attrs) { return 0; }
+static inline void sev_snp_register_ghcb(void) { }
#endif
#endif
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 0083464de5e3..16b5667bbfdb 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -59,6 +59,7 @@
#include <asm/cpu_device_id.h>
#include <asm/uv/uv.h>
#include <asm/sigframe.h>
+#include <asm/sev.h>
#include "cpu.h"
@@ -1977,6 +1978,10 @@ void cpu_init_exception_handling(void)
load_TR_desc();
+ /* Register the GHCB before taking any VC exception */
+ if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT))
+ sev_snp_register_ghcb();
+
/* Finally load the IDT */
load_current_idt();
}
diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
index 54bf0603002f..968105cec364 100644
--- a/arch/x86/kernel/head64.c
+++ b/arch/x86/kernel/head64.c
@@ -588,6 +588,9 @@ void early_setup_idt(void)
bringup_idt_descr.address = (unsigned long)bringup_idt_table;
native_load_idt(&bringup_idt_descr);
+
+ if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT))
+ sev_snp_register_ghcb();
}
/*
diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c
index 80a41e413cb8..30634e7e5c7b 100644
--- a/arch/x86/kernel/sev.c
+++ b/arch/x86/kernel/sev.c
@@ -158,55 +158,6 @@ void noinstr __sev_es_ist_exit(void)
this_cpu_write(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC], *(unsigned long *)ist);
}
-/*
- * Nothing shall interrupt this code path while holding the per-CPU
- * GHCB. The backup GHCB is only for NMIs interrupting this path.
- *
- * Callers must disable local interrupts around it.
- */
-static noinstr struct ghcb *__sev_get_ghcb(struct ghcb_state *state)
-{
- struct sev_es_runtime_data *data;
- struct ghcb *ghcb;
-
- WARN_ON(!irqs_disabled());
-
- data = this_cpu_read(runtime_data);
- ghcb = &data->ghcb_page;
-
- if (unlikely(data->ghcb_active)) {
- /* GHCB is already in use - save its contents */
-
- if (unlikely(data->backup_ghcb_active)) {
- /*
- * Backup-GHCB is also already in use. There is no way
- * to continue here so just kill the machine. To make
- * panic() work, mark GHCBs inactive so that messages
- * can be printed out.
- */
- data->ghcb_active = false;
- data->backup_ghcb_active = false;
-
- instrumentation_begin();
- panic("Unable to handle #VC exception! GHCB and Backup GHCB are already in use");
- instrumentation_end();
- }
-
- /* Mark backup_ghcb active before writing to it */
- data->backup_ghcb_active = true;
-
- state->ghcb = &data->backup_ghcb;
-
- /* Backup GHCB content */
- *state->ghcb = *ghcb;
- } else {
- state->ghcb = NULL;
- data->ghcb_active = true;
- }
-
- return ghcb;
-}
-
static inline u64 sev_es_rd_ghcb_msr(void)
{
return __rdmsr(MSR_AMD64_SEV_ES_GHCB);
@@ -459,6 +410,55 @@ static enum es_result vc_slow_virt_to_phys(struct ghcb *ghcb, struct es_em_ctxt
/* Include code shared with pre-decompression boot stage */
#include "sev-shared.c"
+/*
+ * Nothing shall interrupt this code path while holding the per-CPU
+ * GHCB. The backup GHCB is only for NMIs interrupting this path.
+ *
+ * Callers must disable local interrupts around it.
+ */
+static noinstr struct ghcb *__sev_get_ghcb(struct ghcb_state *state)
+{
+ struct sev_es_runtime_data *data;
+ struct ghcb *ghcb;
+
+ WARN_ON(!irqs_disabled());
+
+ data = this_cpu_read(runtime_data);
+ ghcb = &data->ghcb_page;
+
+ if (unlikely(data->ghcb_active)) {
+ /* GHCB is already in use - save its contents */
+
+ if (unlikely(data->backup_ghcb_active)) {
+ /*
+ * Backup-GHCB is also already in use. There is no way
+ * to continue here so just kill the machine. To make
+ * panic() work, mark GHCBs inactive so that messages
+ * can be printed out.
+ */
+ data->ghcb_active = false;
+ data->backup_ghcb_active = false;
+
+ instrumentation_begin();
+ panic("Unable to handle #VC exception! GHCB and Backup GHCB are already in use");
+ instrumentation_end();
+ }
+
+ /* Mark backup_ghcb active before writing to it */
+ data->backup_ghcb_active = true;
+
+ state->ghcb = &data->backup_ghcb;
+
+ /* Backup GHCB content */
+ *state->ghcb = *ghcb;
+ } else {
+ state->ghcb = NULL;
+ data->ghcb_active = true;
+ }
+
+ return ghcb;
+}
+
static noinstr void __sev_put_ghcb(struct ghcb_state *state)
{
struct sev_es_runtime_data *data;
@@ -650,6 +650,10 @@ static bool __init setup_ghcb(void)
/* Alright - Make the boot-ghcb public */
boot_ghcb = &boot_ghcb_page;
+ /* SEV-SNP guest requires that GHCB GPA must be registered. */
+ if (cc_platform_has(CC_ATTR_SEV_SNP))
+ snp_register_ghcb_early(__pa(&boot_ghcb_page));
+
return true;
}
@@ -741,6 +745,20 @@ static void __init init_ghcb(int cpu)
data->backup_ghcb_active = false;
}
+void sev_snp_register_ghcb(void)
+{
+ struct sev_es_runtime_data *data;
+ struct ghcb *ghcb;
+
+ if (!cc_platform_has(CC_ATTR_SEV_SNP))
+ return;
+
+ data = this_cpu_read(runtime_data);
+ ghcb = &data->ghcb_page;
+
+ snp_register_ghcb_early(__pa(ghcb));
+}
+
void __init sev_es_init_vc_handling(void)
{
int cpu;
--
2.25.1
next prev parent reply other threads:[~2021-11-10 22:08 UTC|newest]
Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-10 22:06 [PATCH v7 00/45] Add AMD Secure Nested Paging (SEV-SNP) Guest Support Brijesh Singh
2021-11-10 22:06 ` [PATCH v7 01/45] x86/compressed/64: detect/setup SEV/SME features earlier in boot Brijesh Singh
2021-11-12 16:52 ` Borislav Petkov
2021-11-12 20:30 ` Michael Roth
2021-11-23 21:55 ` Venu Busireddy
2021-11-10 22:06 ` [PATCH v7 02/45] x86/sev: " Brijesh Singh
2021-11-15 19:12 ` Borislav Petkov
2021-11-15 20:17 ` Michael Roth
2021-11-17 13:11 ` Borislav Petkov
2021-12-06 23:47 ` Venu Busireddy
2021-11-10 22:06 ` [PATCH v7 03/45] x86/mm: Extend cc_attr to include AMD SEV-SNP Brijesh Singh
2021-11-10 22:06 ` [PATCH v7 04/45] x86/sev: Shorten GHCB terminate macro names Brijesh Singh
2021-11-10 22:06 ` [PATCH v7 05/45] x86/sev: Get rid of excessive use of defines Brijesh Singh
2021-11-10 22:06 ` [PATCH v7 06/45] x86/head64: Carve out the guest encryption postprocessing into a helper Brijesh Singh
2021-11-10 22:06 ` [PATCH v7 07/45] x86/sev: Remove do_early_exception() forward declarations Brijesh Singh
2021-11-10 22:06 ` [PATCH v7 08/45] x86/sev: Define the Linux specific guest termination reasons Brijesh Singh
2021-11-10 22:06 ` [PATCH v7 09/45] x86/sev: Save the negotiated GHCB version Brijesh Singh
2021-12-07 12:51 ` Tianyu Lan
2021-12-07 13:17 ` Borislav Petkov
2021-12-07 16:58 ` Brijesh Singh
2021-11-10 22:06 ` [PATCH v7 10/45] x86/sev: Add support for hypervisor feature VMGEXIT Brijesh Singh
2021-12-02 17:52 ` Borislav Petkov
2021-12-06 15:15 ` Brijesh Singh
2021-11-10 22:06 ` [PATCH v7 11/45] x86/sev: Check SEV-SNP features support Brijesh Singh
2021-11-10 22:06 ` [PATCH v7 12/45] x86/sev: Add a helper for the PVALIDATE instruction Brijesh Singh
2021-11-10 22:06 ` [PATCH v7 13/45] x86/sev: Check the vmpl level Brijesh Singh
2021-12-06 18:25 ` Borislav Petkov
2021-11-10 22:07 ` [PATCH v7 14/45] x86/compressed: Add helper for validating pages in the decompression stage Brijesh Singh
2021-12-07 11:48 ` Borislav Petkov
2021-12-07 19:21 ` Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 15/45] x86/compressed: Register GHCB memory when SEV-SNP is active Brijesh Singh
2021-11-15 14:05 ` Jörg Rödel
2021-11-10 22:07 ` Brijesh Singh [this message]
2021-12-08 17:41 ` [PATCH v7 16/45] x86/sev: " Borislav Petkov
2021-11-10 22:07 ` [PATCH v7 17/45] x86/sev: Add helper for validating pages in early enc attribute changes Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 18/45] x86/kernel: Make the bss.decrypted section shared in RMP table Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 19/45] x86/kernel: Validate rom memory before accessing when SEV-SNP is active Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 20/45] x86/mm: Add support to validate memory when changing C-bit Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 21/45] KVM: SVM: Define sev_features and vmpl field in the VMSA Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 22/45] KVM: SVM: Create a separate mapping for the SEV-ES save area Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 23/45] KVM: SVM: Create a separate mapping for the GHCB " Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 24/45] KVM: SVM: Update the SEV-ES save area mapping Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 25/45] x86/sev: Use SEV-SNP AP creation to start secondary CPUs Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 26/45] x86/head: re-enable stack protection for 32/64-bit builds Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 27/45] x86/sev: move MSR-based VMGEXITs for CPUID to helper Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 28/45] KVM: x86: move lookup of indexed CPUID leafs " Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 29/45] x86/compressed/acpi: move EFI system table lookup " Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 30/45] x86/compressed/acpi: move EFI config " Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 31/45] x86/compressed/acpi: move EFI vendor " Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 32/45] x86/boot: Add Confidential Computing type to setup_data Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 33/45] KVM: SEV: Add documentation for SEV-SNP CPUID Enforcement Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 34/45] x86/compressed/64: add support for SEV-SNP CPUID table in #VC handlers Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 35/45] x86/boot: add a pointer to Confidential Computing blob in bootparams Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 36/45] x86/compressed: add SEV-SNP feature detection/setup Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 37/45] x86/compressed: use firmware-validated CPUID for SEV-SNP guests Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 38/45] x86/compressed/64: add identity mapping for Confidential Computing blob Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 39/45] x86/sev: add SEV-SNP feature detection/setup Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 40/45] x86/sev: use firmware-validated CPUID for SEV-SNP guests Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 41/45] x86/sev: Provide support for SNP guest request NAEs Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 42/45] x86/sev: Register SNP guest request platform device Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 43/45] virt: Add SEV-SNP guest driver Brijesh Singh
2021-11-10 22:27 ` Randy Dunlap
2021-11-11 19:27 ` Brijesh Singh
2021-11-11 22:57 ` Randy Dunlap
2021-11-17 23:34 ` Peter Gonda
2021-11-18 17:08 ` Peter Gonda
2021-11-18 17:32 ` Brijesh Singh
2021-11-19 16:16 ` Peter Gonda
2021-11-20 0:28 ` Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 44/45] virt: sevguest: Add support to derive key Brijesh Singh
2021-11-18 16:43 ` Peter Gonda
2021-11-18 17:43 ` Brijesh Singh
2021-11-10 22:07 ` [PATCH v7 45/45] virt: sevguest: Add support to get extended report Brijesh Singh
2021-11-15 15:56 ` [PATCH v7 00/45] Add AMD Secure Nested Paging (SEV-SNP) Guest Support Venu Busireddy
2021-11-15 16:02 ` Brijesh Singh
2021-11-15 16:37 ` Venu Busireddy
2021-11-15 16:45 ` Brijesh Singh
2021-11-15 16:55 ` Venu Busireddy
2021-11-16 15:45 ` Venu Busireddy
2021-11-16 16:03 ` Brijesh Singh
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