* [PATCH 0/3] x86/sev: Minor updates for SEV guest support
@ 2021-06-22 14:48 Joerg Roedel
2021-06-22 14:48 ` [PATCH 1/3] x86/sev: Add Comments to existing GHCB MSR protocol defines Joerg Roedel
` (2 more replies)
0 siblings, 3 replies; 11+ messages in thread
From: Joerg Roedel @ 2021-06-22 14:48 UTC (permalink / raw)
To: x86
Cc: Joerg Roedel, Joerg Roedel, hpa, Andy Lutomirski, Dave Hansen,
Peter Zijlstra, Jiri Slaby, Dan Williams, Tom Lendacky,
Juergen Gross, Kees Cook, David Rientjes, Cfir Cohen,
Erdem Aktas, Masami Hiramatsu, Mike Stunes, Sean Christopherson,
Martin Radev, Arvind Sankar, linux-coco, linux-kernel, kvm,
virtualization
From: Joerg Roedel <jroedel@suse.de>
Hi,
here are three small patches to update SEV-ES guest support in Linux.
It would be great to have at least patch 3 merged for v5.14 to avoid
future merge conflicts. It contains defines needed by KVM and X86
patches under development.
Thanks,
Joerg
Brijesh Singh (1):
x86/sev: Add defines for GHCB version 2 MSR protocol requests
Joerg Roedel (2):
x86/sev: Add Comments to existing GHCB MSR protocol defines
x86/sev: Use "SEV: " prefix for messages from sev.c
arch/x86/include/asm/sev-common.h | 17 +++++++++++++++++
arch/x86/kernel/sev.c | 2 +-
2 files changed, 18 insertions(+), 1 deletion(-)
base-commit: be1a5408868af341f61f93c191b5e346ee88c82a
--
2.31.1
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH 1/3] x86/sev: Add Comments to existing GHCB MSR protocol defines 2021-06-22 14:48 [PATCH 0/3] x86/sev: Minor updates for SEV guest support Joerg Roedel @ 2021-06-22 14:48 ` Joerg Roedel 2021-06-22 14:48 ` [PATCH 2/3] x86/sev: Add defines for GHCB version 2 MSR protocol requests Joerg Roedel 2021-06-22 14:48 ` [PATCH 3/3] x86/sev: Use "SEV: " prefix for messages from sev.c Joerg Roedel 2 siblings, 0 replies; 11+ messages in thread From: Joerg Roedel @ 2021-06-22 14:48 UTC (permalink / raw) To: x86 Cc: Joerg Roedel, Joerg Roedel, hpa, Andy Lutomirski, Dave Hansen, Peter Zijlstra, Jiri Slaby, Dan Williams, Tom Lendacky, Juergen Gross, Kees Cook, David Rientjes, Cfir Cohen, Erdem Aktas, Masami Hiramatsu, Mike Stunes, Sean Christopherson, Martin Radev, Arvind Sankar, linux-coco, linux-kernel, kvm, virtualization From: Joerg Roedel <jroedel@suse.de> Add comments to the defines for SEV Info and CPUID MSR protocol defines to document to which protocol part they belong. Signed-off-by: Joerg Roedel <jroedel@suse.de> --- arch/x86/include/asm/sev-common.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index 629c3df243f0..1cc9e7dd8107 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -11,6 +11,7 @@ #define GHCB_MSR_INFO_POS 0 #define GHCB_MSR_INFO_MASK (BIT_ULL(12) - 1) +/* SEV Information Request/Response */ #define GHCB_MSR_SEV_INFO_RESP 0x001 #define GHCB_MSR_SEV_INFO_REQ 0x002 #define GHCB_MSR_VER_MAX_POS 48 @@ -28,6 +29,7 @@ #define GHCB_MSR_PROTO_MAX(v) (((v) >> GHCB_MSR_VER_MAX_POS) & GHCB_MSR_VER_MAX_MASK) #define GHCB_MSR_PROTO_MIN(v) (((v) >> GHCB_MSR_VER_MIN_POS) & GHCB_MSR_VER_MIN_MASK) +/* CPUID Request/Response */ #define GHCB_MSR_CPUID_REQ 0x004 #define GHCB_MSR_CPUID_RESP 0x005 #define GHCB_MSR_CPUID_FUNC_POS 32 -- 2.31.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/3] x86/sev: Add defines for GHCB version 2 MSR protocol requests 2021-06-22 14:48 [PATCH 0/3] x86/sev: Minor updates for SEV guest support Joerg Roedel 2021-06-22 14:48 ` [PATCH 1/3] x86/sev: Add Comments to existing GHCB MSR protocol defines Joerg Roedel @ 2021-06-22 14:48 ` Joerg Roedel 2021-06-22 16:19 ` Tom Lendacky 2021-06-23 6:40 ` Joerg Roedel 2021-06-22 14:48 ` [PATCH 3/3] x86/sev: Use "SEV: " prefix for messages from sev.c Joerg Roedel 2 siblings, 2 replies; 11+ messages in thread From: Joerg Roedel @ 2021-06-22 14:48 UTC (permalink / raw) To: x86 Cc: Joerg Roedel, Joerg Roedel, Brijesh Singh, Tom Lendacky, hpa, Andy Lutomirski, Dave Hansen, Peter Zijlstra, Jiri Slaby, Dan Williams, Juergen Gross, Kees Cook, David Rientjes, Cfir Cohen, Erdem Aktas, Masami Hiramatsu, Mike Stunes, Sean Christopherson, Martin Radev, Arvind Sankar, linux-coco, linux-kernel, kvm, virtualization From: Brijesh Singh <brijesh.singh@amd.com> Add the necessary defines for supporting the GHCB version 2 protocol. This includes defines for: - MSR-based AP hlt request/response - Hypervisor Feature request/response This is the bare minimum of requests that need to be supported by a GHCB version 2 implementation. There are more requests in the specification, but those depend on Secure Nested Paging support being available. These defines are shared between SEV host and guest support, so they are submitted as an individual patch without users yet to avoid merge conflicts in the future. Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Co-developed-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Joerg Roedel <jroedel@suse.de> --- arch/x86/include/asm/sev-common.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index 1cc9e7dd8107..4e6c4c7cb294 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -47,6 +47,21 @@ (((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << GHCB_MSR_CPUID_REG_POS) | \ (((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS)) +/* AP Reset Hold */ +#define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 +#define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 +#define GHCB_MSR_AP_RESET_HOLD_RESULT_POS 12 +#define GHCB_MSR_AP_RESET_HOLD_RESULT_MASK GENMASK_ULL(51, 0) + +/* GHCB Hypervisor Feature Request/Response */ +#define GHCB_MSR_HV_FT_REQ 0x080 +#define GHCB_MSR_HV_FT_RESP 0x081 +#define GHCB_MSR_HV_FT_POS 12 +#define GHCB_MSR_HV_FT_MASK GENMASK_ULL(51, 0) + +#define GHCB_MSR_HV_FT_RESP_VAL(v) \ + (((unsigned long)((v) & GHCB_MSR_HV_FT_MASK) >> GHCB_MSR_HV_FT_POS)) + #define GHCB_MSR_TERM_REQ 0x100 #define GHCB_MSR_TERM_REASON_SET_POS 12 #define GHCB_MSR_TERM_REASON_SET_MASK 0xf -- 2.31.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 2/3] x86/sev: Add defines for GHCB version 2 MSR protocol requests 2021-06-22 14:48 ` [PATCH 2/3] x86/sev: Add defines for GHCB version 2 MSR protocol requests Joerg Roedel @ 2021-06-22 16:19 ` Tom Lendacky 2021-06-22 16:34 ` Brijesh Singh 2021-06-23 6:40 ` Joerg Roedel 1 sibling, 1 reply; 11+ messages in thread From: Tom Lendacky @ 2021-06-22 16:19 UTC (permalink / raw) To: Joerg Roedel, x86 Cc: Joerg Roedel, Brijesh Singh, hpa, Andy Lutomirski, Dave Hansen, Peter Zijlstra, Jiri Slaby, Dan Williams, Juergen Gross, Kees Cook, David Rientjes, Cfir Cohen, Erdem Aktas, Masami Hiramatsu, Mike Stunes, Sean Christopherson, Martin Radev, Arvind Sankar, linux-coco, linux-kernel, kvm, virtualization On 6/22/21 9:48 AM, Joerg Roedel wrote: > From: Brijesh Singh <brijesh.singh@amd.com> > > Add the necessary defines for supporting the GHCB version 2 protocol. > This includes defines for: > > - MSR-based AP hlt request/response > - Hypervisor Feature request/response > > This is the bare minimum of requests that need to be supported by a GHCB > version 2 implementation. There are more requests in the specification, > but those depend on Secure Nested Paging support being available. > > These defines are shared between SEV host and guest support, so they are > submitted as an individual patch without users yet to avoid merge > conflicts in the future. > > Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> > Co-developed-by: Tom Lendacky <thomas.lendacky@amd.com> > Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> > Signed-off-by: Joerg Roedel <jroedel@suse.de> > --- > arch/x86/include/asm/sev-common.h | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h > index 1cc9e7dd8107..4e6c4c7cb294 100644 > --- a/arch/x86/include/asm/sev-common.h > +++ b/arch/x86/include/asm/sev-common.h > @@ -47,6 +47,21 @@ > (((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << GHCB_MSR_CPUID_REG_POS) | \ > (((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS)) > > +/* AP Reset Hold */ > +#define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 > +#define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 > +#define GHCB_MSR_AP_RESET_HOLD_RESULT_POS 12 > +#define GHCB_MSR_AP_RESET_HOLD_RESULT_MASK GENMASK_ULL(51, 0) > + > +/* GHCB Hypervisor Feature Request/Response */ > +#define GHCB_MSR_HV_FT_REQ 0x080 > +#define GHCB_MSR_HV_FT_RESP 0x081 > +#define GHCB_MSR_HV_FT_POS 12 > +#define GHCB_MSR_HV_FT_MASK GENMASK_ULL(51, 0) > + > +#define GHCB_MSR_HV_FT_RESP_VAL(v) \ > + (((unsigned long)((v) & GHCB_MSR_HV_FT_MASK) >> GHCB_MSR_HV_FT_POS)) This should shift down first and then mask or else the mask should be from 12 to 63. Thanks, Tom > + > #define GHCB_MSR_TERM_REQ 0x100 > #define GHCB_MSR_TERM_REASON_SET_POS 12 > #define GHCB_MSR_TERM_REASON_SET_MASK 0xf > ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/3] x86/sev: Add defines for GHCB version 2 MSR protocol requests 2021-06-22 16:19 ` Tom Lendacky @ 2021-06-22 16:34 ` Brijesh Singh 0 siblings, 0 replies; 11+ messages in thread From: Brijesh Singh @ 2021-06-22 16:34 UTC (permalink / raw) To: Tom Lendacky, Joerg Roedel, x86 Cc: brijesh.singh, Joerg Roedel, hpa, Andy Lutomirski, Dave Hansen, Peter Zijlstra, Jiri Slaby, Dan Williams, Juergen Gross, Kees Cook, David Rientjes, Cfir Cohen, Erdem Aktas, Masami Hiramatsu, Mike Stunes, Sean Christopherson, Martin Radev, Arvind Sankar, linux-coco, linux-kernel, kvm, virtualization On 6/22/2021 11:19 AM, Tom Lendacky wrote: > On 6/22/21 9:48 AM, Joerg Roedel wrote: >> From: Brijesh Singh <brijesh.singh@amd.com> >> >> Add the necessary defines for supporting the GHCB version 2 protocol. >> This includes defines for: >> >> - MSR-based AP hlt request/response >> - Hypervisor Feature request/response >> >> This is the bare minimum of requests that need to be supported by a GHCB >> version 2 implementation. There are more requests in the specification, >> but those depend on Secure Nested Paging support being available. >> >> These defines are shared between SEV host and guest support, so they are >> submitted as an individual patch without users yet to avoid merge >> conflicts in the future. >> >> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> >> Co-developed-by: Tom Lendacky <thomas.lendacky@amd.com> >> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> >> Signed-off-by: Joerg Roedel <jroedel@suse.de> >> --- >> arch/x86/include/asm/sev-common.h | 15 +++++++++++++++ >> 1 file changed, 15 insertions(+) >> >> diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h >> index 1cc9e7dd8107..4e6c4c7cb294 100644 >> --- a/arch/x86/include/asm/sev-common.h >> +++ b/arch/x86/include/asm/sev-common.h >> @@ -47,6 +47,21 @@ >> (((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << GHCB_MSR_CPUID_REG_POS) | \ >> (((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS)) >> >> +/* AP Reset Hold */ >> +#define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 >> +#define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 >> +#define GHCB_MSR_AP_RESET_HOLD_RESULT_POS 12 >> +#define GHCB_MSR_AP_RESET_HOLD_RESULT_MASK GENMASK_ULL(51, 0) >> + >> +/* GHCB Hypervisor Feature Request/Response */ >> +#define GHCB_MSR_HV_FT_REQ 0x080 >> +#define GHCB_MSR_HV_FT_RESP 0x081 >> +#define GHCB_MSR_HV_FT_POS 12 >> +#define GHCB_MSR_HV_FT_MASK GENMASK_ULL(51, 0) >> + >> +#define GHCB_MSR_HV_FT_RESP_VAL(v) \ >> + (((unsigned long)((v) & GHCB_MSR_HV_FT_MASK) >> GHCB_MSR_HV_FT_POS)) > > This should shift down first and then mask or else the mask should be from > 12 to 63. > Ah, that's good catch. Joerg, Please let me know if you want me to send the updated patch or you will take care in your next revision. thanks ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 2/3] x86/sev: Add defines for GHCB version 2 MSR protocol requests 2021-06-22 14:48 ` [PATCH 2/3] x86/sev: Add defines for GHCB version 2 MSR protocol requests Joerg Roedel 2021-06-22 16:19 ` Tom Lendacky @ 2021-06-23 6:40 ` Joerg Roedel 2021-06-23 9:32 ` Borislav Petkov 1 sibling, 1 reply; 11+ messages in thread From: Joerg Roedel @ 2021-06-23 6:40 UTC (permalink / raw) To: x86 Cc: Joerg Roedel, Brijesh Singh, Tom Lendacky, hpa, Andy Lutomirski, Dave Hansen, Peter Zijlstra, Jiri Slaby, Dan Williams, Juergen Gross, Kees Cook, David Rientjes, Cfir Cohen, Erdem Aktas, Masami Hiramatsu, Mike Stunes, Sean Christopherson, Martin Radev, Arvind Sankar, linux-coco, linux-kernel, kvm, virtualization From: Brijesh Singh <brijesh.singh@amd.com> Add the necessary defines for supporting the GHCB version 2 protocol. This includes defines for: - MSR-based AP hlt request/response - Hypervisor Feature request/response This is the bare minimum of requests that need to be supported by a GHCB version 2 implementation. There are more requests in the specification, but those depend on Secure Nested Paging support being available. These defines are shared between SEV host and guest support, so they are submitted as an individual patch without users yet to avoid merge conflicts in the future. Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Co-developed-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Joerg Roedel <jroedel@suse.de> --- arch/x86/include/asm/sev-common.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index 1cc9e7dd8107..9aa2f29b4c97 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -47,6 +47,21 @@ (((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << GHCB_MSR_CPUID_REG_POS) | \ (((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS)) +/* AP Reset Hold */ +#define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 +#define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 +#define GHCB_MSR_AP_RESET_HOLD_RESULT_POS 12 +#define GHCB_MSR_AP_RESET_HOLD_RESULT_MASK GENMASK_ULL(51, 0) + +/* GHCB Hypervisor Feature Request/Response */ +#define GHCB_MSR_HV_FT_REQ 0x080 +#define GHCB_MSR_HV_FT_RESP 0x081 +#define GHCB_MSR_HV_FT_POS 12 +#define GHCB_MSR_HV_FT_MASK GENMASK_ULL(51, 0) + +#define GHCB_MSR_HV_FT_RESP_VAL(v) \ + ((unsigned long)((v) >> GHCB_MSR_HV_FT_POS) & GHCB_MSR_HV_FT_MASK) + #define GHCB_MSR_TERM_REQ 0x100 #define GHCB_MSR_TERM_REASON_SET_POS 12 #define GHCB_MSR_TERM_REASON_SET_MASK 0xf -- 2.31.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 2/3] x86/sev: Add defines for GHCB version 2 MSR protocol requests 2021-06-23 6:40 ` Joerg Roedel @ 2021-06-23 9:32 ` Borislav Petkov 2021-06-23 9:49 ` Joerg Roedel ` (2 more replies) 0 siblings, 3 replies; 11+ messages in thread From: Borislav Petkov @ 2021-06-23 9:32 UTC (permalink / raw) To: Joerg Roedel Cc: x86, Joerg Roedel, Brijesh Singh, Tom Lendacky, hpa, Andy Lutomirski, Dave Hansen, Peter Zijlstra, Jiri Slaby, Dan Williams, Juergen Gross, Kees Cook, David Rientjes, Cfir Cohen, Erdem Aktas, Masami Hiramatsu, Mike Stunes, Sean Christopherson, Martin Radev, Arvind Sankar, linux-coco, linux-kernel, kvm, virtualization On Wed, Jun 23, 2021 at 08:40:00AM +0200, Joerg Roedel wrote: > From: Brijesh Singh <brijesh.singh@amd.com> > > Add the necessary defines for supporting the GHCB version 2 protocol. > This includes defines for: > > - MSR-based AP hlt request/response > - Hypervisor Feature request/response > > This is the bare minimum of requests that need to be supported by a GHCB > version 2 implementation. There are more requests in the specification, > but those depend on Secure Nested Paging support being available. > > These defines are shared between SEV host and guest support, so they are > submitted as an individual patch without users yet to avoid merge > conflicts in the future. > > Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> > Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> > Co-developed-by: Tom Lendacky <thomas.lendacky@amd.com> > Signed-off-by: Joerg Roedel <jroedel@suse.de> > --- > arch/x86/include/asm/sev-common.h | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h > index 1cc9e7dd8107..9aa2f29b4c97 100644 > --- a/arch/x86/include/asm/sev-common.h > +++ b/arch/x86/include/asm/sev-common.h > @@ -47,6 +47,21 @@ > (((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << GHCB_MSR_CPUID_REG_POS) | \ > (((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS)) > > +/* AP Reset Hold */ > +#define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 > +#define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 > +#define GHCB_MSR_AP_RESET_HOLD_RESULT_POS 12 > +#define GHCB_MSR_AP_RESET_HOLD_RESULT_MASK GENMASK_ULL(51, 0) > + > +/* GHCB Hypervisor Feature Request/Response */ > +#define GHCB_MSR_HV_FT_REQ 0x080 > +#define GHCB_MSR_HV_FT_RESP 0x081 > +#define GHCB_MSR_HV_FT_POS 12 > +#define GHCB_MSR_HV_FT_MASK GENMASK_ULL(51, 0) > + > +#define GHCB_MSR_HV_FT_RESP_VAL(v) \ > + ((unsigned long)((v) >> GHCB_MSR_HV_FT_POS) & GHCB_MSR_HV_FT_MASK) > + Ok, so I took a critical look at this and it doesn't make sense to have a differently named define each time you need the [63:12] slice of GHCBData. So you can simply use GHCB_DATA(msr_value) instead, see below. Complaints? --- From: Brijesh Singh <brijesh.singh@amd.com> Date: Wed, 23 Jun 2021 08:40:00 +0200 Subject: [PATCH] x86/sev: Add defines for GHCB version 2 MSR protocol requests Add the necessary defines for supporting the GHCB version 2 protocol. This includes defines for: - MSR-based AP hlt request/response - Hypervisor Feature request/response This is the bare minimum of requests that need to be supported by a GHCB version 2 implementation. There are more requests in the specification, but those depend on Secure Nested Paging support being available. These defines are shared between SEV host and guest support. [ bp: Fold in https://lkml.kernel.org/r/20210622144825.27588-2-joro@8bytes.org too. Simplify the brewing macro maze into readability. ] Co-developed-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/YNLXQIZ5e1wjkshG@8bytes.org --- arch/x86/include/asm/sev-common.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index 629c3df243f0..2cef6c5a52c2 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -9,8 +9,13 @@ #define __ASM_X86_SEV_COMMON_H #define GHCB_MSR_INFO_POS 0 -#define GHCB_MSR_INFO_MASK (BIT_ULL(12) - 1) +#define GHCB_DATA_LOW 12 +#define GHCB_MSR_INFO_MASK (BIT_ULL(GHCB_DATA_LOW) - 1) +#define GHCB_DATA(v) \ + (((unsigned long)(v) & ~GHCB_MSR_INFO_MASK) >> GHCB_DATA_LOW) + +/* SEV Information Request/Response */ #define GHCB_MSR_SEV_INFO_RESP 0x001 #define GHCB_MSR_SEV_INFO_REQ 0x002 #define GHCB_MSR_VER_MAX_POS 48 @@ -28,6 +33,7 @@ #define GHCB_MSR_PROTO_MAX(v) (((v) >> GHCB_MSR_VER_MAX_POS) & GHCB_MSR_VER_MAX_MASK) #define GHCB_MSR_PROTO_MIN(v) (((v) >> GHCB_MSR_VER_MIN_POS) & GHCB_MSR_VER_MIN_MASK) +/* CPUID Request/Response */ #define GHCB_MSR_CPUID_REQ 0x004 #define GHCB_MSR_CPUID_RESP 0x005 #define GHCB_MSR_CPUID_FUNC_POS 32 @@ -45,6 +51,14 @@ (((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << GHCB_MSR_CPUID_REG_POS) | \ (((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS)) +/* AP Reset Hold */ +#define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 +#define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 + +/* GHCB Hypervisor Feature Request/Response */ +#define GHCB_MSR_HV_FT_REQ 0x080 +#define GHCB_MSR_HV_FT_RESP 0x081 + #define GHCB_MSR_TERM_REQ 0x100 #define GHCB_MSR_TERM_REASON_SET_POS 12 #define GHCB_MSR_TERM_REASON_SET_MASK 0xf -- 2.29.2 -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 2/3] x86/sev: Add defines for GHCB version 2 MSR protocol requests 2021-06-23 9:32 ` Borislav Petkov @ 2021-06-23 9:49 ` Joerg Roedel 2021-06-23 12:33 ` Brijesh Singh 2021-06-23 13:12 ` Tom Lendacky 2 siblings, 0 replies; 11+ messages in thread From: Joerg Roedel @ 2021-06-23 9:49 UTC (permalink / raw) To: Borislav Petkov Cc: Joerg Roedel, x86, Brijesh Singh, Tom Lendacky, hpa, Andy Lutomirski, Dave Hansen, Peter Zijlstra, Jiri Slaby, Dan Williams, Juergen Gross, Kees Cook, David Rientjes, Cfir Cohen, Erdem Aktas, Masami Hiramatsu, Mike Stunes, Sean Christopherson, Martin Radev, Arvind Sankar, linux-coco, linux-kernel, kvm, virtualization On Wed, Jun 23, 2021 at 11:32:50AM +0200, Borislav Petkov wrote: > Ok, so I took a critical look at this and it doesn't make sense to have > a differently named define each time you need the [63:12] slice of > GHCBData. So you can simply use GHCB_DATA(msr_value) instead, see below. > > Complaints? Looks good to me. ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/3] x86/sev: Add defines for GHCB version 2 MSR protocol requests 2021-06-23 9:32 ` Borislav Petkov 2021-06-23 9:49 ` Joerg Roedel @ 2021-06-23 12:33 ` Brijesh Singh 2021-06-23 13:12 ` Tom Lendacky 2 siblings, 0 replies; 11+ messages in thread From: Brijesh Singh @ 2021-06-23 12:33 UTC (permalink / raw) To: Borislav Petkov, Joerg Roedel Cc: brijesh.singh, x86, Joerg Roedel, Tom Lendacky, hpa, Andy Lutomirski, Dave Hansen, Peter Zijlstra, Jiri Slaby, Dan Williams, Juergen Gross, Kees Cook, David Rientjes, Cfir Cohen, Erdem Aktas, Masami Hiramatsu, Mike Stunes, Sean Christopherson, Martin Radev, Arvind Sankar, linux-coco, linux-kernel, kvm, virtualization On 6/23/21 4:32 AM, Borislav Petkov wrote: > On Wed, Jun 23, 2021 at 08:40:00AM +0200, Joerg Roedel wrote: >> From: Brijesh Singh <brijesh.singh@amd.com> >> >> Add the necessary defines for supporting the GHCB version 2 protocol. >> This includes defines for: >> >> - MSR-based AP hlt request/response >> - Hypervisor Feature request/response >> >> This is the bare minimum of requests that need to be supported by a GHCB >> version 2 implementation. There are more requests in the specification, >> but those depend on Secure Nested Paging support being available. >> >> These defines are shared between SEV host and guest support, so they are >> submitted as an individual patch without users yet to avoid merge >> conflicts in the future. >> >> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> >> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> >> Co-developed-by: Tom Lendacky <thomas.lendacky@amd.com> >> Signed-off-by: Joerg Roedel <jroedel@suse.de> >> --- >> arch/x86/include/asm/sev-common.h | 15 +++++++++++++++ >> 1 file changed, 15 insertions(+) >> >> diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h >> index 1cc9e7dd8107..9aa2f29b4c97 100644 >> --- a/arch/x86/include/asm/sev-common.h >> +++ b/arch/x86/include/asm/sev-common.h >> @@ -47,6 +47,21 @@ >> (((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << GHCB_MSR_CPUID_REG_POS) | \ >> (((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS)) >> >> +/* AP Reset Hold */ >> +#define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 >> +#define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 >> +#define GHCB_MSR_AP_RESET_HOLD_RESULT_POS 12 >> +#define GHCB_MSR_AP_RESET_HOLD_RESULT_MASK GENMASK_ULL(51, 0) >> + >> +/* GHCB Hypervisor Feature Request/Response */ >> +#define GHCB_MSR_HV_FT_REQ 0x080 >> +#define GHCB_MSR_HV_FT_RESP 0x081 >> +#define GHCB_MSR_HV_FT_POS 12 >> +#define GHCB_MSR_HV_FT_MASK GENMASK_ULL(51, 0) >> + >> +#define GHCB_MSR_HV_FT_RESP_VAL(v) \ >> + ((unsigned long)((v) >> GHCB_MSR_HV_FT_POS) & GHCB_MSR_HV_FT_MASK) >> + > Ok, so I took a critical look at this and it doesn't make sense to have > a differently named define each time you need the [63:12] slice of > GHCBData. So you can simply use GHCB_DATA(msr_value) instead, see below. > > Complaints? Looks good to me. ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/3] x86/sev: Add defines for GHCB version 2 MSR protocol requests 2021-06-23 9:32 ` Borislav Petkov 2021-06-23 9:49 ` Joerg Roedel 2021-06-23 12:33 ` Brijesh Singh @ 2021-06-23 13:12 ` Tom Lendacky 2 siblings, 0 replies; 11+ messages in thread From: Tom Lendacky @ 2021-06-23 13:12 UTC (permalink / raw) To: Borislav Petkov, Joerg Roedel Cc: x86, Joerg Roedel, Brijesh Singh, hpa, Andy Lutomirski, Dave Hansen, Peter Zijlstra, Jiri Slaby, Dan Williams, Juergen Gross, Kees Cook, David Rientjes, Cfir Cohen, Erdem Aktas, Masami Hiramatsu, Mike Stunes, Sean Christopherson, Martin Radev, Arvind Sankar, linux-coco, linux-kernel, kvm, virtualization On 6/23/21 4:32 AM, Borislav Petkov wrote: > On Wed, Jun 23, 2021 at 08:40:00AM +0200, Joerg Roedel wrote: >> From: Brijesh Singh <brijesh.singh@amd.com> >> > > Ok, so I took a critical look at this and it doesn't make sense to have > a differently named define each time you need the [63:12] slice of > GHCBData. So you can simply use GHCB_DATA(msr_value) instead, see below. > > Complaints? None from me. Thanks, Tom ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 3/3] x86/sev: Use "SEV: " prefix for messages from sev.c 2021-06-22 14:48 [PATCH 0/3] x86/sev: Minor updates for SEV guest support Joerg Roedel 2021-06-22 14:48 ` [PATCH 1/3] x86/sev: Add Comments to existing GHCB MSR protocol defines Joerg Roedel 2021-06-22 14:48 ` [PATCH 2/3] x86/sev: Add defines for GHCB version 2 MSR protocol requests Joerg Roedel @ 2021-06-22 14:48 ` Joerg Roedel 2 siblings, 0 replies; 11+ messages in thread From: Joerg Roedel @ 2021-06-22 14:48 UTC (permalink / raw) To: x86 Cc: Joerg Roedel, Joerg Roedel, hpa, Andy Lutomirski, Dave Hansen, Peter Zijlstra, Jiri Slaby, Dan Williams, Tom Lendacky, Juergen Gross, Kees Cook, David Rientjes, Cfir Cohen, Erdem Aktas, Masami Hiramatsu, Mike Stunes, Sean Christopherson, Martin Radev, Arvind Sankar, linux-coco, linux-kernel, kvm, virtualization From: Joerg Roedel <jroedel@suse.de> The source file has been renamed froms sev-es.c to sev.c, but the messages are still prefixed with "SEV-ES: ". Change that to "SEV: " to make it consistent. Fixes: e759959fe3b8 ("x86/sev-es: Rename sev-es.{ch} to sev.{ch}") Signed-off-by: Joerg Roedel <jroedel@suse.de> --- arch/x86/kernel/sev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 87a4b00f028e..a6895e440bc3 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -7,7 +7,7 @@ * Author: Joerg Roedel <jroedel@suse.de> */ -#define pr_fmt(fmt) "SEV-ES: " fmt +#define pr_fmt(fmt) "SEV: " fmt #include <linux/sched/debug.h> /* For show_regs() */ #include <linux/percpu-defs.h> -- 2.31.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2021-06-23 13:12 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-06-22 14:48 [PATCH 0/3] x86/sev: Minor updates for SEV guest support Joerg Roedel 2021-06-22 14:48 ` [PATCH 1/3] x86/sev: Add Comments to existing GHCB MSR protocol defines Joerg Roedel 2021-06-22 14:48 ` [PATCH 2/3] x86/sev: Add defines for GHCB version 2 MSR protocol requests Joerg Roedel 2021-06-22 16:19 ` Tom Lendacky 2021-06-22 16:34 ` Brijesh Singh 2021-06-23 6:40 ` Joerg Roedel 2021-06-23 9:32 ` Borislav Petkov 2021-06-23 9:49 ` Joerg Roedel 2021-06-23 12:33 ` Brijesh Singh 2021-06-23 13:12 ` Tom Lendacky 2021-06-22 14:48 ` [PATCH 3/3] x86/sev: Use "SEV: " prefix for messages from sev.c Joerg Roedel
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