* [PATCH V3 0/3] kprobe: Optimize the performance of patching ss
@ 2022-09-23 8:46 Liao Chang
2022-09-23 8:46 ` [PATCH 1/3] riscv/kprobe: Optimize the performance of patching single-step slot Liao Chang
` (2 more replies)
0 siblings, 3 replies; 13+ messages in thread
From: Liao Chang @ 2022-09-23 8:46 UTC (permalink / raw)
To: catalin.marinas, will, guoren, paul.walmsley, palmer, aou,
mhiramat, rostedt, mark.rutland, maz, liaochang1,
alexandru.elisei
Cc: linux-arm-kernel, linux-kernel, linux-csky, linux-riscv
Single-step slot would not be used until kprobe is enabled, that means
no race condition occurs on it under SMP, hence it is safe to pacth ss
slot without stopping machine.
v3:
1. Drop duplicated I-Cache maintenance for arm64.
2. Add Acked-by from Masami Hiramatsu.
v2:
Backport riscv patch to cksy and arm64.
Liao Chang (3):
riscv/kprobe: Optimize the performance of patching single-step slot
csky/kprobe: Optimize the performance of patching single-step slot
arm64/kprobe: Optimize the performance of patching single-step slot
arch/arm64/kernel/probes/kprobes.c | 7 ++-----
arch/csky/kernel/probes/kprobes.c | 6 +++++-
arch/riscv/kernel/probes/kprobes.c | 8 +++++---
3 files changed, 12 insertions(+), 9 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH 1/3] riscv/kprobe: Optimize the performance of patching single-step slot
2022-09-23 8:46 [PATCH V3 0/3] kprobe: Optimize the performance of patching ss Liao Chang
@ 2022-09-23 8:46 ` Liao Chang
2022-09-23 8:46 ` [PATCH 2/3] csky/kprobe: " Liao Chang
2022-09-23 8:46 ` [PATCH 3/3] arm64/kprobe: " Liao Chang
2 siblings, 0 replies; 13+ messages in thread
From: Liao Chang @ 2022-09-23 8:46 UTC (permalink / raw)
To: catalin.marinas, will, guoren, paul.walmsley, palmer, aou,
mhiramat, rostedt, mark.rutland, maz, liaochang1,
alexandru.elisei
Cc: linux-arm-kernel, linux-kernel, linux-csky, linux-riscv
Single-step slot would not be used until kprobe is enabled, that means
no race condition occurs on it under SMP, hence it is safe to pacth ss
slot without stopping machine.
Acked-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
Signed-off-by: Liao Chang <liaochang1@huawei.com>
---
arch/riscv/kernel/probes/kprobes.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/kernel/probes/kprobes.c b/arch/riscv/kernel/probes/kprobes.c
index e6e950b7cf32..bc1f39b96e41 100644
--- a/arch/riscv/kernel/probes/kprobes.c
+++ b/arch/riscv/kernel/probes/kprobes.c
@@ -24,12 +24,14 @@ post_kprobe_handler(struct kprobe *, struct kprobe_ctlblk *, struct pt_regs *);
static void __kprobes arch_prepare_ss_slot(struct kprobe *p)
{
unsigned long offset = GET_INSN_LENGTH(p->opcode);
+ kprobe_opcode_t slot[MAX_INSN_SIZE];
p->ainsn.api.restore = (unsigned long)p->addr + offset;
- patch_text(p->ainsn.api.insn, p->opcode);
- patch_text((void *)((unsigned long)(p->ainsn.api.insn) + offset),
- __BUG_INSN_32);
+ memcpy(slot, &p->opcode, offset);
+ *(kprobe_opcode_t *)((unsigned long)slot + offset) = __BUG_INSN_32;
+ patch_text_nosync(p->ainsn.api.insn, slot,
+ offset + GET_INSN_LENGTH(__BUG_INSN_32));
}
static void __kprobes arch_prepare_simulate(struct kprobe *p)
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 2/3] csky/kprobe: Optimize the performance of patching single-step slot
2022-09-23 8:46 [PATCH V3 0/3] kprobe: Optimize the performance of patching ss Liao Chang
2022-09-23 8:46 ` [PATCH 1/3] riscv/kprobe: Optimize the performance of patching single-step slot Liao Chang
@ 2022-09-23 8:46 ` Liao Chang
2022-09-23 8:46 ` [PATCH 3/3] arm64/kprobe: " Liao Chang
2 siblings, 0 replies; 13+ messages in thread
From: Liao Chang @ 2022-09-23 8:46 UTC (permalink / raw)
To: catalin.marinas, will, guoren, paul.walmsley, palmer, aou,
mhiramat, rostedt, mark.rutland, maz, liaochang1,
alexandru.elisei
Cc: linux-arm-kernel, linux-kernel, linux-csky, linux-riscv
Single-step slot would not be used until kprobe is enabled, that means
no race condition occurs on it under SMP, hence it is safe to pacth ss
slot without stopping machine.
Acked-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
Signed-off-by: Liao Chang <liaochang1@huawei.com>
---
arch/csky/kernel/probes/kprobes.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/csky/kernel/probes/kprobes.c b/arch/csky/kernel/probes/kprobes.c
index 3c6e5c725d81..4feb5ce16264 100644
--- a/arch/csky/kernel/probes/kprobes.c
+++ b/arch/csky/kernel/probes/kprobes.c
@@ -57,7 +57,11 @@ static void __kprobes arch_prepare_ss_slot(struct kprobe *p)
p->ainsn.api.restore = (unsigned long)p->addr + offset;
- patch_text(p->ainsn.api.insn, p->opcode);
+ memcpy(p->ainsn.api.insn, &p->opcode, offset);
+ dcache_wb_range((unsigned long)p->ainsn.api.insn,
+ (unsigned long)p->ainsn.api.insn + offset);
+ icache_inv_range((unsigned long)p->ainsn.api.insn,
+ (unsigned long)p->ainsn.api.insn + offset);
}
static void __kprobes arch_prepare_simulate(struct kprobe *p)
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/3] arm64/kprobe: Optimize the performance of patching single-step slot
2022-09-23 8:46 [PATCH V3 0/3] kprobe: Optimize the performance of patching ss Liao Chang
2022-09-23 8:46 ` [PATCH 1/3] riscv/kprobe: Optimize the performance of patching single-step slot Liao Chang
2022-09-23 8:46 ` [PATCH 2/3] csky/kprobe: " Liao Chang
@ 2022-09-23 8:46 ` Liao Chang
2022-09-23 12:35 ` Will Deacon
2022-09-23 12:39 ` Mark Rutland
2 siblings, 2 replies; 13+ messages in thread
From: Liao Chang @ 2022-09-23 8:46 UTC (permalink / raw)
To: catalin.marinas, will, guoren, paul.walmsley, palmer, aou,
mhiramat, rostedt, mark.rutland, maz, liaochang1,
alexandru.elisei
Cc: linux-arm-kernel, linux-kernel, linux-csky, linux-riscv
Single-step slot would not be used until kprobe is enabled, that means
no race condition occurs on it under SMP, hence it is safe to pacth ss
slot without stopping machine.
Since I and D caches are coherent within single-step slot from
aarch64_insn_patch_text_nosync(), hence no need to do it again via
flush_icache_range().
Acked-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
Signed-off-by: Liao Chang <liaochang1@huawei.com>
---
arch/arm64/kernel/probes/kprobes.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/kernel/probes/kprobes.c b/arch/arm64/kernel/probes/kprobes.c
index d1d182320245..29b98bc12833 100644
--- a/arch/arm64/kernel/probes/kprobes.c
+++ b/arch/arm64/kernel/probes/kprobes.c
@@ -44,13 +44,10 @@ post_kprobe_handler(struct kprobe *, struct kprobe_ctlblk *, struct pt_regs *);
static void __kprobes arch_prepare_ss_slot(struct kprobe *p)
{
kprobe_opcode_t *addr = p->ainsn.api.insn;
- void *addrs[] = {addr, addr + 1};
- u32 insns[] = {p->opcode, BRK64_OPCODE_KPROBES_SS};
/* prepare insn slot */
- aarch64_insn_patch_text(addrs, insns, 2);
-
- flush_icache_range((uintptr_t)addr, (uintptr_t)(addr + MAX_INSN_SIZE));
+ aarch64_insn_patch_text_nosync(addr, p->opcode);
+ aarch64_insn_patch_text_nosync(addr + 1, BRK64_OPCODE_KPROBES_SS);
/*
* Needs restoring of return address after stepping xol.
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 3/3] arm64/kprobe: Optimize the performance of patching single-step slot
2022-09-23 8:46 ` [PATCH 3/3] arm64/kprobe: " Liao Chang
@ 2022-09-23 12:35 ` Will Deacon
2022-09-23 12:39 ` Mark Rutland
1 sibling, 0 replies; 13+ messages in thread
From: Will Deacon @ 2022-09-23 12:35 UTC (permalink / raw)
To: Liao Chang
Cc: catalin.marinas, guoren, paul.walmsley, palmer, aou, mhiramat,
rostedt, mark.rutland, maz, alexandru.elisei, linux-arm-kernel,
linux-kernel, linux-csky, linux-riscv
On Fri, Sep 23, 2022 at 04:46:58PM +0800, Liao Chang wrote:
> Single-step slot would not be used until kprobe is enabled, that means
> no race condition occurs on it under SMP, hence it is safe to pacth ss
> slot without stopping machine.
>
> Since I and D caches are coherent within single-step slot from
> aarch64_insn_patch_text_nosync(), hence no need to do it again via
> flush_icache_range().
>
> Acked-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
> Signed-off-by: Liao Chang <liaochang1@huawei.com>
> ---
> arch/arm64/kernel/probes/kprobes.c | 7 ++-----
> 1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/kernel/probes/kprobes.c b/arch/arm64/kernel/probes/kprobes.c
> index d1d182320245..29b98bc12833 100644
> --- a/arch/arm64/kernel/probes/kprobes.c
> +++ b/arch/arm64/kernel/probes/kprobes.c
> @@ -44,13 +44,10 @@ post_kprobe_handler(struct kprobe *, struct kprobe_ctlblk *, struct pt_regs *);
> static void __kprobes arch_prepare_ss_slot(struct kprobe *p)
> {
> kprobe_opcode_t *addr = p->ainsn.api.insn;
> - void *addrs[] = {addr, addr + 1};
> - u32 insns[] = {p->opcode, BRK64_OPCODE_KPROBES_SS};
>
> /* prepare insn slot */
> - aarch64_insn_patch_text(addrs, insns, 2);
> -
> - flush_icache_range((uintptr_t)addr, (uintptr_t)(addr + MAX_INSN_SIZE));
> + aarch64_insn_patch_text_nosync(addr, p->opcode);
> + aarch64_insn_patch_text_nosync(addr + 1, BRK64_OPCODE_KPROBES_SS);
>
> /*
> * Needs restoring of return address after stepping xol.
> --
> 2.17.1
Acked-by: Will Deacon <will@kernel.org>
Will
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 3/3] arm64/kprobe: Optimize the performance of patching single-step slot
2022-09-23 8:46 ` [PATCH 3/3] arm64/kprobe: " Liao Chang
2022-09-23 12:35 ` Will Deacon
@ 2022-09-23 12:39 ` Mark Rutland
2022-09-24 1:52 ` liaochang (A)
1 sibling, 1 reply; 13+ messages in thread
From: Mark Rutland @ 2022-09-23 12:39 UTC (permalink / raw)
To: Liao Chang
Cc: catalin.marinas, will, guoren, paul.walmsley, palmer, aou,
mhiramat, rostedt, maz, alexandru.elisei, linux-arm-kernel,
linux-kernel, linux-csky, linux-riscv
On Fri, Sep 23, 2022 at 04:46:58PM +0800, Liao Chang wrote:
> Single-step slot would not be used until kprobe is enabled, that means
> no race condition occurs on it under SMP, hence it is safe to pacth ss
> slot without stopping machine.
I think this is correct, but this depends on a couple of subtleties,
importantly:
* That the I-cache maintenance for these instructions is complete *before* the
kprobe BRK is written (and aarch64_insn_patch_text_nosync() ensures this, but
just omits causing a Context-Synchronization-Event on all CPUS).
* That the kprobe BRK results in an exception (and consequently a
Context-Synchronoization-Event), which ensures that the CPU will fetch the
single-step slot instructions *after* this, ensuring that the new
instructions are used.
It would be good if we could call that out explicitly.
Thanks,
Mark.
> Since I and D caches are coherent within single-step slot from
> aarch64_insn_patch_text_nosync(), hence no need to do it again via
> flush_icache_range().
>
> Acked-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
> Signed-off-by: Liao Chang <liaochang1@huawei.com>
> ---
> arch/arm64/kernel/probes/kprobes.c | 7 ++-----
> 1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/kernel/probes/kprobes.c b/arch/arm64/kernel/probes/kprobes.c
> index d1d182320245..29b98bc12833 100644
> --- a/arch/arm64/kernel/probes/kprobes.c
> +++ b/arch/arm64/kernel/probes/kprobes.c
> @@ -44,13 +44,10 @@ post_kprobe_handler(struct kprobe *, struct kprobe_ctlblk *, struct pt_regs *);
> static void __kprobes arch_prepare_ss_slot(struct kprobe *p)
> {
> kprobe_opcode_t *addr = p->ainsn.api.insn;
> - void *addrs[] = {addr, addr + 1};
> - u32 insns[] = {p->opcode, BRK64_OPCODE_KPROBES_SS};
>
> /* prepare insn slot */
> - aarch64_insn_patch_text(addrs, insns, 2);
> -
> - flush_icache_range((uintptr_t)addr, (uintptr_t)(addr + MAX_INSN_SIZE));
> + aarch64_insn_patch_text_nosync(addr, p->opcode);
> + aarch64_insn_patch_text_nosync(addr + 1, BRK64_OPCODE_KPROBES_SS);
>
> /*
> * Needs restoring of return address after stepping xol.
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 3/3] arm64/kprobe: Optimize the performance of patching single-step slot
2022-09-23 12:39 ` Mark Rutland
@ 2022-09-24 1:52 ` liaochang (A)
2022-09-25 1:21 ` Masami Hiramatsu
0 siblings, 1 reply; 13+ messages in thread
From: liaochang (A) @ 2022-09-24 1:52 UTC (permalink / raw)
To: Mark Rutland
Cc: catalin.marinas, will, guoren, paul.walmsley, palmer, aou,
mhiramat, rostedt, maz, alexandru.elisei, linux-arm-kernel,
linux-kernel, linux-csky, linux-riscv
在 2022/9/23 20:39, Mark Rutland 写道:
> On Fri, Sep 23, 2022 at 04:46:58PM +0800, Liao Chang wrote:
>> Single-step slot would not be used until kprobe is enabled, that means
>> no race condition occurs on it under SMP, hence it is safe to pacth ss
>> slot without stopping machine.
>
> I think this is correct, but this depends on a couple of subtleties,
> importantly:
>
> * That the I-cache maintenance for these instructions is complete *before* the
> kprobe BRK is written (and aarch64_insn_patch_text_nosync() ensures this, but
> just omits causing a Context-Synchronization-Event on all CPUS).
So in order to guarantee the I-cache maintenance is observed on all CPUS,
it needs to be followed by a explicit Context-Synchronization-Event, perhaps
it is better to place ISB before kprobe BRK is written.
>
> * That the kprobe BRK results in an exception (and consequently a
> Context-Synchronoization-Event), which ensures that the CPU will fetch the
> single-step slot instructions *after* this, ensuring that the new
> instructions are used.
Yes, because of single-step slot is installed int the BRK execption handler,
so it is not necessary to generate Context-Synchronization-Event via ISB mentioned above...
Thanks.
>
> It would be good if we could call that out explicitly.
>
> Thanks,
> Mark.
>
>> Since I and D caches are coherent within single-step slot from
>> aarch64_insn_patch_text_nosync(), hence no need to do it again via
>> flush_icache_range().
>>
>> Acked-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
>> Signed-off-by: Liao Chang <liaochang1@huawei.com>
>> ---
>> arch/arm64/kernel/probes/kprobes.c | 7 ++-----
>> 1 file changed, 2 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/arm64/kernel/probes/kprobes.c b/arch/arm64/kernel/probes/kprobes.c
>> index d1d182320245..29b98bc12833 100644
>> --- a/arch/arm64/kernel/probes/kprobes.c
>> +++ b/arch/arm64/kernel/probes/kprobes.c
>> @@ -44,13 +44,10 @@ post_kprobe_handler(struct kprobe *, struct kprobe_ctlblk *, struct pt_regs *);
>> static void __kprobes arch_prepare_ss_slot(struct kprobe *p)
>> {
>> kprobe_opcode_t *addr = p->ainsn.api.insn;
>> - void *addrs[] = {addr, addr + 1};
>> - u32 insns[] = {p->opcode, BRK64_OPCODE_KPROBES_SS};
>>
>> /* prepare insn slot */
>> - aarch64_insn_patch_text(addrs, insns, 2);
>> -
>> - flush_icache_range((uintptr_t)addr, (uintptr_t)(addr + MAX_INSN_SIZE));
>> + aarch64_insn_patch_text_nosync(addr, p->opcode);
>> + aarch64_insn_patch_text_nosync(addr + 1, BRK64_OPCODE_KPROBES_SS);
>>
>> /*
>> * Needs restoring of return address after stepping xol.
>> --
>> 2.17.1
>>
>
> .
--
BR,
Liao, Chang
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 3/3] arm64/kprobe: Optimize the performance of patching single-step slot
2022-09-24 1:52 ` liaochang (A)
@ 2022-09-25 1:21 ` Masami Hiramatsu
2022-09-27 1:37 ` liaochang (A)
0 siblings, 1 reply; 13+ messages in thread
From: Masami Hiramatsu @ 2022-09-25 1:21 UTC (permalink / raw)
To: liaochang (A)
Cc: Mark Rutland, catalin.marinas, will, guoren, paul.walmsley,
palmer, aou, mhiramat, rostedt, maz, alexandru.elisei,
linux-arm-kernel, linux-kernel, linux-csky, linux-riscv
On Sat, 24 Sep 2022 09:52:28 +0800
"liaochang (A)" <liaochang1@huawei.com> wrote:
>
>
> 在 2022/9/23 20:39, Mark Rutland 写道:
> > On Fri, Sep 23, 2022 at 04:46:58PM +0800, Liao Chang wrote:
> >> Single-step slot would not be used until kprobe is enabled, that means
> >> no race condition occurs on it under SMP, hence it is safe to pacth ss
> >> slot without stopping machine.
> >
> > I think this is correct, but this depends on a couple of subtleties,
> > importantly:
> >
> > * That the I-cache maintenance for these instructions is complete *before* the
> > kprobe BRK is written (and aarch64_insn_patch_text_nosync() ensures this, but
> > just omits causing a Context-Synchronization-Event on all CPUS).
>
> So in order to guarantee the I-cache maintenance is observed on all CPUS,
> it needs to be followed by a explicit Context-Synchronization-Event, perhaps
> it is better to place ISB before kprobe BRK is written.
>
> >
> > * That the kprobe BRK results in an exception (and consequently a
> > Context-Synchronoization-Event), which ensures that the CPU will fetch the
> > single-step slot instructions *after* this, ensuring that the new
> > instructions are used.
>
> Yes, because of single-step slot is installed int the BRK execption handler,
> so it is not necessary to generate Context-Synchronization-Event via ISB mentioned above...
Can you update the patch including above as comments in the code?
Maybe you also have to ensure it on other patches too.
Thank you,
>
> Thanks.
>
> >
> > It would be good if we could call that out explicitly.
> >
> > Thanks,
> > Mark.
> >
> >> Since I and D caches are coherent within single-step slot from
> >> aarch64_insn_patch_text_nosync(), hence no need to do it again via
> >> flush_icache_range().
> >>
> >> Acked-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
> >> Signed-off-by: Liao Chang <liaochang1@huawei.com>
> >> ---
> >> arch/arm64/kernel/probes/kprobes.c | 7 ++-----
> >> 1 file changed, 2 insertions(+), 5 deletions(-)
> >>
> >> diff --git a/arch/arm64/kernel/probes/kprobes.c b/arch/arm64/kernel/probes/kprobes.c
> >> index d1d182320245..29b98bc12833 100644
> >> --- a/arch/arm64/kernel/probes/kprobes.c
> >> +++ b/arch/arm64/kernel/probes/kprobes.c
> >> @@ -44,13 +44,10 @@ post_kprobe_handler(struct kprobe *, struct kprobe_ctlblk *, struct pt_regs *);
> >> static void __kprobes arch_prepare_ss_slot(struct kprobe *p)
> >> {
> >> kprobe_opcode_t *addr = p->ainsn.api.insn;
> >> - void *addrs[] = {addr, addr + 1};
> >> - u32 insns[] = {p->opcode, BRK64_OPCODE_KPROBES_SS};
> >>
> >> /* prepare insn slot */
> >> - aarch64_insn_patch_text(addrs, insns, 2);
> >> -
> >> - flush_icache_range((uintptr_t)addr, (uintptr_t)(addr + MAX_INSN_SIZE));
> >> + aarch64_insn_patch_text_nosync(addr, p->opcode);
> >> + aarch64_insn_patch_text_nosync(addr + 1, BRK64_OPCODE_KPROBES_SS);
> >>
> >> /*
> >> * Needs restoring of return address after stepping xol.
> >> --
> >> 2.17.1
> >>
> >
> > .
>
> --
> BR,
> Liao, Chang
--
Masami Hiramatsu (Google) <mhiramat@kernel.org>
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 3/3] arm64/kprobe: Optimize the performance of patching single-step slot
2022-09-25 1:21 ` Masami Hiramatsu
@ 2022-09-27 1:37 ` liaochang (A)
0 siblings, 0 replies; 13+ messages in thread
From: liaochang (A) @ 2022-09-27 1:37 UTC (permalink / raw)
To: Masami Hiramatsu (Google)
Cc: Mark Rutland, catalin.marinas, will, guoren, paul.walmsley,
palmer, aou, rostedt, maz, alexandru.elisei, linux-arm-kernel,
linux-kernel, linux-csky, linux-riscv
在 2022/9/25 9:21, Masami Hiramatsu (Google) 写道:
> On Sat, 24 Sep 2022 09:52:28 +0800
> "liaochang (A)" <liaochang1@huawei.com> wrote:
>
>>
>>
>> 在 2022/9/23 20:39, Mark Rutland 写道:
>>> On Fri, Sep 23, 2022 at 04:46:58PM +0800, Liao Chang wrote:
>>>> Single-step slot would not be used until kprobe is enabled, that means
>>>> no race condition occurs on it under SMP, hence it is safe to pacth ss
>>>> slot without stopping machine.
>>>
>>> I think this is correct, but this depends on a couple of subtleties,
>>> importantly:
>>>
>>> * That the I-cache maintenance for these instructions is complete *before* the
>>> kprobe BRK is written (and aarch64_insn_patch_text_nosync() ensures this, but
>>> just omits causing a Context-Synchronization-Event on all CPUS).
>>
>> So in order to guarantee the I-cache maintenance is observed on all CPUS,
>> it needs to be followed by a explicit Context-Synchronization-Event, perhaps
>> it is better to place ISB before kprobe BRK is written.
>>
>>>
>>> * That the kprobe BRK results in an exception (and consequently a
>>> Context-Synchronoization-Event), which ensures that the CPU will fetch the
>>> single-step slot instructions *after* this, ensuring that the new
>>> instructions are used.
>>
>> Yes, because of single-step slot is installed int the BRK execption handler,
>> so it is not necessary to generate Context-Synchronization-Event via ISB mentioned above...
>
> Can you update the patch including above as comments in the code?
> Maybe you also have to ensure it on other patches too.
OK，i will add these comments in the code.
Thanks.
>
> Thank you,
>
>>
>> Thanks.
>>
>>>
>>> It would be good if we could call that out explicitly.
>>>
>>> Thanks,
>>> Mark.
>>>
>>>> Since I and D caches are coherent within single-step slot from
>>>> aarch64_insn_patch_text_nosync(), hence no need to do it again via
>>>> flush_icache_range().
>>>>
>>>> Acked-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
>>>> Signed-off-by: Liao Chang <liaochang1@huawei.com>
>>>> ---
>>>> arch/arm64/kernel/probes/kprobes.c | 7 ++-----
>>>> 1 file changed, 2 insertions(+), 5 deletions(-)
>>>>
>>>> diff --git a/arch/arm64/kernel/probes/kprobes.c b/arch/arm64/kernel/probes/kprobes.c
>>>> index d1d182320245..29b98bc12833 100644
>>>> --- a/arch/arm64/kernel/probes/kprobes.c
>>>> +++ b/arch/arm64/kernel/probes/kprobes.c
>>>> @@ -44,13 +44,10 @@ post_kprobe_handler(struct kprobe *, struct kprobe_ctlblk *, struct pt_regs *);
>>>> static void __kprobes arch_prepare_ss_slot(struct kprobe *p)
>>>> {
>>>> kprobe_opcode_t *addr = p->ainsn.api.insn;
>>>> - void *addrs[] = {addr, addr + 1};
>>>> - u32 insns[] = {p->opcode, BRK64_OPCODE_KPROBES_SS};
>>>>
>>>> /* prepare insn slot */
>>>> - aarch64_insn_patch_text(addrs, insns, 2);
>>>> -
>>>> - flush_icache_range((uintptr_t)addr, (uintptr_t)(addr + MAX_INSN_SIZE));
>>>> + aarch64_insn_patch_text_nosync(addr, p->opcode);
>>>> + aarch64_insn_patch_text_nosync(addr + 1, BRK64_OPCODE_KPROBES_SS);
>>>>
>>>> /*
>>>> * Needs restoring of return address after stepping xol.
>>>> --
>>>> 2.17.1
>>>>
>>>
>>> .
>>
>> --
>> BR,
>> Liao, Chang
>
>
--
BR,
Liao, Chang
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH V4 0/3] kprobe: Optimize the performance of patching ss
@ 2022-09-27 2:24 Liao Chang
2022-09-27 2:24 ` [PATCH 3/3] arm64/kprobe: Optimize the performance of patching single-step slot Liao Chang
0 siblings, 1 reply; 13+ messages in thread
From: Liao Chang @ 2022-09-27 2:24 UTC (permalink / raw)
To: catalin.marinas, will, guoren, paul.walmsley, palmer, aou,
mhiramat, rostedt, maz, alexandru.elisei, liaochang1
Cc: linux-arm-kernel, linux-kernel, linux-csky, linux-riscv
Single-step slot would not be used until kprobe is enabled, that means
no race condition occurs on it under SMP, hence it is safe to pacth ss
slot without stopping machine.
v4:
1. Add Acked-by from Will Deacon
2. Mark Rutland provides some subtleties on arm64 micro-architecture
that needs to follow.
v3:
1. Drop duplicated I-Cache maintenance for arm64.
2. Add Acked-by from Masami Hiramatsu.
v2:
Backport riscv patch to cksy and arm64.
Liao Chang (3):
riscv/kprobe: Optimize the performance of patching single-step slot
csky/kprobe: Optimize the performance of patching single-step slot
arm64/kprobe: Optimize the performance of patching single-step slot
arch/arm64/kernel/probes/kprobes.c | 27 +++++++++++++++++++++------
arch/csky/kernel/probes/kprobes.c | 6 +++++-
arch/riscv/kernel/probes/kprobes.c | 8 +++++---
3 files changed, 31 insertions(+), 10 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 3/3] arm64/kprobe: Optimize the performance of patching single-step slot
2022-09-27 2:24 [PATCH V4 0/3] kprobe: Optimize the performance of patching ss Liao Chang
@ 2022-09-27 2:24 ` Liao Chang
2022-09-29 16:50 ` Catalin Marinas
0 siblings, 1 reply; 13+ messages in thread
From: Liao Chang @ 2022-09-27 2:24 UTC (permalink / raw)
To: catalin.marinas, will, guoren, paul.walmsley, palmer, aou,
mhiramat, rostedt, maz, alexandru.elisei, liaochang1
Cc: linux-arm-kernel, linux-kernel, linux-csky, linux-riscv
Single-step slot would not be used until kprobe is enabled, that means
no race condition occurs on it under SMP, hence it is safe to pacth ss
slot without stopping machine.
Since I and D caches are coherent within single-step slot from
aarch64_insn_patch_text_nosync(), hence no need to do it again via
flush_icache_range().
Acked-by: Will Deacon <will@kernel.org>
Acked-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
Signed-off-by: Liao Chang <liaochang1@huawei.com>
---
arch/arm64/kernel/probes/kprobes.c | 27 +++++++++++++++++++++------
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/kernel/probes/kprobes.c b/arch/arm64/kernel/probes/kprobes.c
index d1d182320245..c9e4d0720285 100644
--- a/arch/arm64/kernel/probes/kprobes.c
+++ b/arch/arm64/kernel/probes/kprobes.c
@@ -44,13 +44,28 @@ post_kprobe_handler(struct kprobe *, struct kprobe_ctlblk *, struct pt_regs *);
static void __kprobes arch_prepare_ss_slot(struct kprobe *p)
{
kprobe_opcode_t *addr = p->ainsn.api.insn;
- void *addrs[] = {addr, addr + 1};
- u32 insns[] = {p->opcode, BRK64_OPCODE_KPROBES_SS};
- /* prepare insn slot */
- aarch64_insn_patch_text(addrs, insns, 2);
-
- flush_icache_range((uintptr_t)addr, (uintptr_t)(addr + MAX_INSN_SIZE));
+ /*
+ * Prepare insn slot, Mark Rutland points out it depends on a coupe of
+ * subtleties:
+ *
+ * - That the I-cache maintenance for these instructions is complete
+ * *before* the kprobe BRK is written (and aarch64_insn_patch_text_nosync()
+ * ensures this, but just omits causing a Context-Synchronization-Event
+ * on all CPUS).
+ *
+ * - That the kprobe BRK results in an exception (and consequently a
+ * Context-Synchronoization-Event), which ensures that the CPU will
+ * fetch thesingle-step slot instructions *after* this, ensuring that
+ * the new instructions are used
+ *
+ * It supposes to place ISB after patching to guarantee I-cache maintenance
+ * is observed on all CPUS, however, single-step slot is installed in
+ * the BRK exception handler, so it is unnecessary to generate
+ * Contex-Synchronization-Event via ISB again.
+ */
+ aarch64_insn_patch_text_nosync(addr, p->opcode);
+ aarch64_insn_patch_text_nosync(addr + 1, BRK64_OPCODE_KPROBES_SS);
/*
* Needs restoring of return address after stepping xol.
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 3/3] arm64/kprobe: Optimize the performance of patching single-step slot
2022-09-27 2:24 ` [PATCH 3/3] arm64/kprobe: Optimize the performance of patching single-step slot Liao Chang
@ 2022-09-29 16:50 ` Catalin Marinas
2022-09-30 1:02 ` liaochang (A)
0 siblings, 1 reply; 13+ messages in thread
From: Catalin Marinas @ 2022-09-29 16:50 UTC (permalink / raw)
To: Liao Chang
Cc: will, guoren, paul.walmsley, palmer, aou, mhiramat, rostedt, maz,
alexandru.elisei, linux-arm-kernel, linux-kernel, linux-csky,
linux-riscv
On Tue, Sep 27, 2022 at 10:24:35AM +0800, Liao Chang wrote:
> Single-step slot would not be used until kprobe is enabled, that means
> no race condition occurs on it under SMP, hence it is safe to pacth ss
> slot without stopping machine.
>
> Since I and D caches are coherent within single-step slot from
> aarch64_insn_patch_text_nosync(), hence no need to do it again via
> flush_icache_range().
>
> Acked-by: Will Deacon <will@kernel.org>
> Acked-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
> Signed-off-by: Liao Chang <liaochang1@huawei.com>
> ---
> arch/arm64/kernel/probes/kprobes.c | 27 +++++++++++++++++++++------
> 1 file changed, 21 insertions(+), 6 deletions(-)
What's your expectation with this series, should the arch maintainers
just pick the individual patches?
--
Catalin
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/3] arm64/kprobe: Optimize the performance of patching single-step slot
2022-09-29 16:50 ` Catalin Marinas
@ 2022-09-30 1:02 ` liaochang (A)
2022-09-30 8:15 ` Catalin Marinas
0 siblings, 1 reply; 13+ messages in thread
From: liaochang (A) @ 2022-09-30 1:02 UTC (permalink / raw)
To: Catalin Marinas
Cc: will, guoren, paul.walmsley, palmer, aou, mhiramat, rostedt, maz,
alexandru.elisei, linux-arm-kernel, linux-kernel, linux-csky,
linux-riscv
在 2022/9/30 0:50, Catalin Marinas 写道:
> On Tue, Sep 27, 2022 at 10:24:35AM +0800, Liao Chang wrote:
>> Single-step slot would not be used until kprobe is enabled, that means
>> no race condition occurs on it under SMP, hence it is safe to pacth ss
>> slot without stopping machine.
>>
>> Since I and D caches are coherent within single-step slot from
>> aarch64_insn_patch_text_nosync(), hence no need to do it again via
>> flush_icache_range().
>>
>> Acked-by: Will Deacon <will@kernel.org>
>> Acked-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
>> Signed-off-by: Liao Chang <liaochang1@huawei.com>
>> ---
>> arch/arm64/kernel/probes/kprobes.c | 27 +++++++++++++++++++++------
>> 1 file changed, 21 insertions(+), 6 deletions(-)
>
> What's your expectation with this series, should the arch maintainers
> just pick the individual patches?
Yes, or should i split this series into individual patch?
Thanks.
>
--
BR,
Liao, Chang
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/3] arm64/kprobe: Optimize the performance of patching single-step slot
2022-09-30 1:02 ` liaochang (A)
@ 2022-09-30 8:15 ` Catalin Marinas
0 siblings, 0 replies; 13+ messages in thread
From: Catalin Marinas @ 2022-09-30 8:15 UTC (permalink / raw)
To: liaochang (A)
Cc: will, guoren, paul.walmsley, palmer, aou, mhiramat, rostedt, maz,
alexandru.elisei, linux-arm-kernel, linux-kernel, linux-csky,
linux-riscv
On Fri, Sep 30, 2022 at 09:02:20AM +0800, liaochang (A) wrote:
>
>
> 在 2022/9/30 0:50, Catalin Marinas 写道:
> > On Tue, Sep 27, 2022 at 10:24:35AM +0800, Liao Chang wrote:
> >> Single-step slot would not be used until kprobe is enabled, that means
> >> no race condition occurs on it under SMP, hence it is safe to pacth ss
> >> slot without stopping machine.
> >>
> >> Since I and D caches are coherent within single-step slot from
> >> aarch64_insn_patch_text_nosync(), hence no need to do it again via
> >> flush_icache_range().
> >>
> >> Acked-by: Will Deacon <will@kernel.org>
> >> Acked-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
> >> Signed-off-by: Liao Chang <liaochang1@huawei.com>
> >> ---
> >> arch/arm64/kernel/probes/kprobes.c | 27 +++++++++++++++++++++------
> >> 1 file changed, 21 insertions(+), 6 deletions(-)
> >
> > What's your expectation with this series, should the arch maintainers
> > just pick the individual patches?
>
> Yes, or should i split this series into individual patch?
No need to, I can pick the arm64 patch. If the other maintainers don't
merge the patches, you might want to post them again individually as to
avoid confusion.
--
Catalin
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2022-09-30 8:15 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-23 8:46 [PATCH V3 0/3] kprobe: Optimize the performance of patching ss Liao Chang
2022-09-23 8:46 ` [PATCH 1/3] riscv/kprobe: Optimize the performance of patching single-step slot Liao Chang
2022-09-23 8:46 ` [PATCH 2/3] csky/kprobe: " Liao Chang
2022-09-23 8:46 ` [PATCH 3/3] arm64/kprobe: " Liao Chang
2022-09-23 12:35 ` Will Deacon
2022-09-23 12:39 ` Mark Rutland
2022-09-24 1:52 ` liaochang (A)
2022-09-25 1:21 ` Masami Hiramatsu
2022-09-27 1:37 ` liaochang (A)
2022-09-27 2:24 [PATCH V4 0/3] kprobe: Optimize the performance of patching ss Liao Chang
2022-09-27 2:24 ` [PATCH 3/3] arm64/kprobe: Optimize the performance of patching single-step slot Liao Chang
2022-09-29 16:50 ` Catalin Marinas
2022-09-30 1:02 ` liaochang (A)
2022-09-30 8:15 ` Catalin Marinas
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