From: kernel test robot <lkp@intel.com>
To: Ben Widawsky <ben.widawsky@intel.com>,
linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org
Cc: llvm@lists.linux.dev, kbuild-all@lists.01.org,
Ben Widawsky <ben.widawsky@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <Jonathan.Cameron@Huawei.com>,
Vishal Verma <vishal.l.verma@intel.com>
Subject: Re: [PATCH 19/23] cxl/pci: Store component register base in cxlds
Date: Sat, 20 Nov 2021 15:28:58 +0800 [thread overview]
Message-ID: <202111201504.m2HX1MjO-lkp@intel.com> (raw)
In-Reply-To: <20211120000250.1663391-20-ben.widawsky@intel.com>
[-- Attachment #1: Type: text/plain, Size: 5236 bytes --]
Hi Ben,
I love your patch! Perhaps something to improve:
[auto build test WARNING on 53989fad1286e652ea3655ae3367ba698da8d2ff]
url: https://github.com/0day-ci/linux/commits/Ben-Widawsky/Add-drivers-for-CXL-ports-and-mem-devices/20211120-080513
base: 53989fad1286e652ea3655ae3367ba698da8d2ff
config: riscv-buildonly-randconfig-r001-20211119 (attached as .config)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install riscv cross compiling tool for clang build
# apt-get install binutils-riscv64-linux-gnu
# https://github.com/0day-ci/linux/commit/3f74c99d751a24a4c12ba76c23b68c2832f805e1
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Ben-Widawsky/Add-drivers-for-CXL-ports-and-mem-devices/20211120-080513
git checkout 3f74c99d751a24a4c12ba76c23b68c2832f805e1
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=riscv
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
drivers/cxl/pci.c:469:7: warning: variable 'size' set but not used [-Wunused-but-set-variable]
u64 size;
^
drivers/cxl/pci.c:516:7: warning: variable 'size' set but not used [-Wunused-but-set-variable]
u64 size;
^
>> drivers/cxl/pci.c:673:13: warning: variable 'cxlmd' is uninitialized when used here [-Wuninitialized]
dev_warn(&cxlmd->dev, "No component registers (%d)\n", rc);
^~~~~
include/linux/dev_printk.h:146:49: note: expanded from macro 'dev_warn'
dev_printk_index_wrap(_dev_warn, KERN_WARNING, dev, dev_fmt(fmt), ##__VA_ARGS__)
^~~
include/linux/dev_printk.h:110:11: note: expanded from macro 'dev_printk_index_wrap'
_p_func(dev, fmt, ##__VA_ARGS__); \
^~~
drivers/cxl/pci.c:630:26: note: initialize the variable 'cxlmd' to silence this warning
struct cxl_memdev *cxlmd;
^
= NULL
3 warnings generated.
vim +/cxlmd +673 drivers/cxl/pci.c
625
626 static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
627 {
628 struct cxl_endpoint_dvsec_info *info;
629 struct cxl_register_map map;
630 struct cxl_memdev *cxlmd;
631 struct cxl_dev_state *cxlds;
632 int rc;
633
634 /*
635 * Double check the anonymous union trickery in struct cxl_regs
636 * FIXME switch to struct_group()
637 */
638 BUILD_BUG_ON(offsetof(struct cxl_regs, memdev) !=
639 offsetof(struct cxl_regs, device_regs.memdev));
640
641 rc = pcim_enable_device(pdev);
642 if (rc)
643 return rc;
644
645 cxlds = cxl_dev_state_create(&pdev->dev);
646 if (IS_ERR(cxlds))
647 return PTR_ERR(cxlds);
648
649 cxlds->device_dvsec = pci_find_dvsec_capability(pdev,
650 PCI_DVSEC_VENDOR_ID_CXL,
651 CXL_DVSEC_PCIE_DEVICE);
652 if (!cxlds->device_dvsec)
653 dev_warn(&pdev->dev,
654 "Device DVSEC not present. Expect limited functionality.\n");
655 else
656 cxlds->wait_media_ready = wait_for_media_ready;
657
658 rc = cxl_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map);
659 if (rc)
660 return rc;
661
662 rc = cxl_map_regs(cxlds, &map);
663 if (rc)
664 return rc;
665
666 /*
667 * If the component registers can't be found, the cxl_pci driver may
668 * still be useful for management functions so don't return an error.
669 */
670 cxlds->component_reg_phys = CXL_RESOURCE_NONE;
671 rc = cxl_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
672 if (rc)
> 673 dev_warn(&cxlmd->dev, "No component registers (%d)\n", rc);
674 else
675 cxlds->component_reg_phys = cxl_reg_block(pdev, &map);
676
677 rc = cxl_pci_setup_mailbox(cxlds);
678 if (rc)
679 return rc;
680
681 rc = cxl_enumerate_cmds(cxlds);
682 if (rc)
683 return rc;
684
685 rc = cxl_dev_state_identify(cxlds);
686 if (rc)
687 return rc;
688
689 rc = cxl_mem_create_range_info(cxlds);
690 if (rc)
691 return rc;
692
693 info = dvsec_ranges(cxlds);
694 if (IS_ERR(info))
695 dev_err(&pdev->dev,
696 "Failed to get DVSEC range information (%ld)\n",
697 PTR_ERR(info));
698 else
699 cxlds->info = info;
700
701 cxlmd = devm_cxl_add_memdev(cxlds);
702 if (IS_ERR(cxlmd))
703 return PTR_ERR(cxlmd);
704
705 if (range_len(&cxlds->pmem_range) && IS_ENABLED(CONFIG_CXL_PMEM))
706 rc = devm_cxl_add_nvdimm(&pdev->dev, cxlmd);
707
708 return rc;
709 }
710
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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next prev parent reply other threads:[~2021-11-20 7:30 UTC|newest]
Thread overview: 127+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-20 0:02 [PATCH 00/23] Add drivers for CXL ports and mem devices Ben Widawsky
2021-11-20 0:02 ` [PATCH 01/23] cxl: Rename CXL_MEM to CXL_PCI Ben Widawsky
2021-11-22 14:47 ` Jonathan Cameron
2021-11-24 4:15 ` Dan Williams
2021-11-20 0:02 ` [PATCH 02/23] cxl: Flesh out register names Ben Widawsky
2021-11-22 14:49 ` Jonathan Cameron
2021-11-24 4:24 ` Dan Williams
2021-11-20 0:02 ` [PATCH 03/23] cxl/pci: Extract device status check Ben Widawsky
2021-11-22 15:03 ` Jonathan Cameron
2021-11-24 19:30 ` Dan Williams
2021-11-20 0:02 ` [PATCH 04/23] cxl/pci: Implement Interface Ready Timeout Ben Widawsky
2021-11-22 15:02 ` Jonathan Cameron
2021-11-22 17:17 ` Ben Widawsky
2021-11-22 17:53 ` Jonathan Cameron
2021-11-24 19:56 ` Dan Williams
2021-11-25 6:17 ` Ben Widawsky
2021-11-25 7:14 ` Dan Williams
2021-11-20 0:02 ` [PATCH 05/23] cxl/pci: Don't poll doorbell for mailbox access Ben Widawsky
2021-11-22 15:11 ` Jonathan Cameron
2021-11-22 17:24 ` Ben Widawsky
2021-11-24 21:55 ` Dan Williams
2021-11-29 18:33 ` Ben Widawsky
2021-11-29 19:02 ` Dan Williams
2021-11-29 19:11 ` Ben Widawsky
2021-11-29 19:18 ` Dan Williams
2021-11-29 19:31 ` Ben Widawsky
2021-11-29 19:37 ` Dan Williams
2021-11-29 19:50 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 06/23] cxl/pci: Don't check media status for mbox access Ben Widawsky
2021-11-22 15:19 ` Jonathan Cameron
2021-11-24 21:58 ` Dan Williams
2021-11-20 0:02 ` [PATCH 07/23] cxl/pci: Add new DVSEC definitions Ben Widawsky
2021-11-22 15:22 ` Jonathan Cameron
2021-11-22 17:32 ` Ben Widawsky
2021-11-24 22:03 ` Dan Williams
2021-11-20 0:02 ` [PATCH 08/23] cxl/acpi: Map component registers for Root Ports Ben Widawsky
2021-11-22 15:51 ` Jonathan Cameron
2021-11-22 19:28 ` Ben Widawsky
2021-11-24 22:18 ` Dan Williams
2021-11-20 0:02 ` [PATCH 09/23] cxl: Introduce module_cxl_driver Ben Widawsky
2021-11-22 15:54 ` Jonathan Cameron
2021-11-24 22:22 ` Dan Williams
2021-11-20 0:02 ` [PATCH 10/23] cxl/core: Convert decoder range to resource Ben Widawsky
2021-11-22 16:08 ` Jonathan Cameron
2021-11-24 22:41 ` Dan Williams
2021-11-20 0:02 ` [PATCH 11/23] cxl/core: Document and tighten up decoder APIs Ben Widawsky
2021-11-22 16:13 ` Jonathan Cameron
2021-11-24 22:55 ` Dan Williams
2021-11-20 0:02 ` [PATCH 12/23] cxl: Introduce endpoint decoders Ben Widawsky
2021-11-22 16:20 ` Jonathan Cameron
2021-11-22 19:37 ` Ben Widawsky
2021-11-25 0:07 ` Dan Williams
2021-11-29 20:05 ` Ben Widawsky
2021-11-29 20:07 ` Dan Williams
2021-11-29 20:12 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 13/23] cxl/core: Move target population locking to caller Ben Widawsky
2021-11-22 16:33 ` Jonathan Cameron
2021-11-22 21:58 ` Ben Widawsky
2021-11-23 11:05 ` Jonathan Cameron
2021-11-25 0:34 ` Dan Williams
2021-11-20 0:02 ` [PATCH 14/23] cxl: Introduce topology host registration Ben Widawsky
2021-11-22 18:20 ` Jonathan Cameron
2021-11-22 22:30 ` Ben Widawsky
2021-11-25 1:09 ` Dan Williams
2021-11-29 21:23 ` Ben Widawsky
2021-11-29 11:42 ` Dan Carpenter
2021-11-20 0:02 ` [PATCH 15/23] cxl/core: Store global list of root ports Ben Widawsky
2021-11-22 18:22 ` Jonathan Cameron
2021-11-22 22:32 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 16/23] cxl/pci: Cache device DVSEC offset Ben Widawsky
2021-11-22 16:46 ` Jonathan Cameron
2021-11-22 22:34 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 17/23] cxl: Cache and pass DVSEC ranges Ben Widawsky
2021-11-20 4:29 ` kernel test robot
2021-11-22 17:00 ` Jonathan Cameron
2021-11-22 22:50 ` Ben Widawsky
2021-11-26 11:37 ` Jonathan Cameron
2021-11-20 0:02 ` [PATCH 18/23] cxl/pci: Implement wait for media active Ben Widawsky
2021-11-22 17:03 ` Jonathan Cameron
2021-11-22 22:57 ` Ben Widawsky
2021-11-23 11:09 ` Jonathan Cameron
2021-11-23 16:04 ` Ben Widawsky
2021-11-23 17:48 ` Bjorn Helgaas
2021-11-23 19:37 ` Ben Widawsky
2021-11-26 11:36 ` Jonathan Cameron
2021-11-20 0:02 ` [PATCH 19/23] cxl/pci: Store component register base in cxlds Ben Widawsky
2021-11-20 7:28 ` kernel test robot [this message]
2021-11-22 17:11 ` Jonathan Cameron
2021-11-22 23:01 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 20/23] cxl/port: Introduce a port driver Ben Widawsky
2021-11-20 3:14 ` kernel test robot
2021-11-20 5:38 ` kernel test robot
2021-11-22 17:41 ` Jonathan Cameron
2021-11-22 23:38 ` Ben Widawsky
2021-11-23 11:38 ` Jonathan Cameron
2021-11-23 16:14 ` Ben Widawsky
2021-11-23 18:21 ` Bjorn Helgaas
2021-11-23 22:03 ` Ben Widawsky
2021-11-23 22:36 ` Dan Williams
2021-11-23 23:38 ` Ben Widawsky
2021-11-23 23:55 ` Bjorn Helgaas
2021-11-24 0:40 ` Dan Williams
2021-11-24 6:33 ` Christoph Hellwig
2021-11-24 7:17 ` Dan Williams
2021-11-24 7:28 ` Christoph Hellwig
2021-11-24 7:33 ` Greg Kroah-Hartman
2021-11-24 7:54 ` Dan Williams
2021-11-24 8:21 ` Greg Kroah-Hartman
2021-11-24 18:24 ` Dan Williams
2021-12-02 21:24 ` Bjorn Helgaas
2021-12-03 1:38 ` Dan Williams
2021-12-03 22:03 ` Bjorn Helgaas
2021-12-04 1:24 ` Dan Williams
2021-12-07 2:56 ` Bjorn Helgaas
2021-12-07 4:48 ` Dan Williams
2021-11-24 21:31 ` Bjorn Helgaas
2021-11-20 0:02 ` [PATCH 21/23] cxl: Unify port enumeration for decoders Ben Widawsky
2021-11-22 17:48 ` Jonathan Cameron
2021-11-22 23:44 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 22/23] cxl/mem: Introduce cxl_mem driver Ben Widawsky
2021-11-20 0:40 ` Randy Dunlap
2021-11-21 3:55 ` Ben Widawsky
2021-11-22 18:17 ` Jonathan Cameron
2021-11-23 0:05 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 23/23] cxl/mem: Disable switch hierarchies for now Ben Widawsky
2021-11-22 18:19 ` Jonathan Cameron
2021-11-22 19:17 ` Ben Widawsky
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