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From: Ben Widawsky <ben.widawsky@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
	Alison Schofield <alison.schofield@intel.com>,
	Dan Williams <dan.j.williams@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>
Subject: Re: [PATCH 13/23] cxl/core: Move target population locking to caller
Date: Mon, 22 Nov 2021 13:58:01 -0800	[thread overview]
Message-ID: <20211122215801.gshai367q2fhp6uj@intel.com> (raw)
In-Reply-To: <20211122163302.00005ae9@Huawei.com>

On 21-11-22 16:33:02, Jonathan Cameron wrote:
> On Fri, 19 Nov 2021 16:02:40 -0800
> Ben Widawsky <ben.widawsky@intel.com> wrote:
> 
> > In preparation for a port driver that enumerates a descendant port +
> > decoder hierarchy, arrange for an unlocked version of cxl_decoder_add().
> > Otherwise a port-driver that adds a child decoder will deadlock on the
> > device_lock() in ->probe().
> > 
> 
> I think this description should call out that the lock was originally taken
> for a much shorter time in decoder_populate_targets() but is moved
> up one layer.

Sounds good.

> 
> One other query inline.  Seems like we the WARN_ON stuff is a bit
> over paranoid given what's visible in this patch.  If there is a
> good reason for that, then add something to the patch description to
> justify it.
>  
> > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
> > 
> > ---
> > 
> > Changes since RFCv2:
> > - Reword commit message (Dan)
> > - Move decoder API changes into this patch (Dan)
> > ---
> >  drivers/cxl/core/bus.c | 59 +++++++++++++++++++++++++++++++-----------
> >  drivers/cxl/cxl.h      |  1 +
> >  2 files changed, 45 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/cxl/core/bus.c b/drivers/cxl/core/bus.c
> > index 16b15f54fb62..cd6fe7823c69 100644
> > --- a/drivers/cxl/core/bus.c
> > +++ b/drivers/cxl/core/bus.c
> > @@ -487,28 +487,22 @@ static int decoder_populate_targets(struct cxl_decoder *cxld,
> >  {
> >  	int rc = 0, i;
> >  
> > +	device_lock_assert(&port->dev);
> > +
> >  	if (!target_map)
> >  		return 0;
> >  
> > -	device_lock(&port->dev);
> > -	if (list_empty(&port->dports)) {
> > -		rc = -EINVAL;
> > -		goto out_unlock;
> > -	}
> > +	if (list_empty(&port->dports))
> > +		return -EINVAL;
> >  
> >  	for (i = 0; i < cxld->nr_targets; i++) {
> >  		struct cxl_dport *dport = find_dport(port, target_map[i]);
> >  
> > -		if (!dport) {
> > -			rc = -ENXIO;
> > -			goto out_unlock;
> > -		}
> > +		if (!dport)
> > +			return -ENXIO;
> >  		cxld->target[i] = dport;
> >  	}
> >  
> > -out_unlock:
> > -	device_unlock(&port->dev);
> > -
> >  	return rc;
> >  }
> >  
> > @@ -571,7 +565,7 @@ struct cxl_decoder *cxl_decoder_alloc(struct cxl_port *port,
> >  EXPORT_SYMBOL_NS_GPL(cxl_decoder_alloc, CXL);
> >  
> >  /**
> > - * cxl_decoder_add - Add a decoder with targets
> > + * cxl_decoder_add_locked - Add a decoder with targets
> >   * @cxld: The cxl decoder allocated by cxl_decoder_alloc()
> >   * @target_map: A list of downstream ports that this decoder can direct memory
> >   *              traffic to. These numbers should correspond with the port number
> > @@ -581,12 +575,14 @@ EXPORT_SYMBOL_NS_GPL(cxl_decoder_alloc, CXL);
> >   * is an endpoint device. A more awkward example is a hostbridge whose root
> >   * ports get hot added (technically possible, though unlikely).
> >   *
> > - * Context: Process context. Takes and releases the cxld's device lock.
> > + * This is the locked variant of cxl_decoder_add().
> > + *
> > + * Context: Process context. Expects the cxld's device lock to be held.
> >   *
> >   * Return: Negative error code if the decoder wasn't properly configured; else
> >   *	   returns 0.
> >   */
> > -int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map)
> > +int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map)
> >  {
> >  	struct cxl_port *port;
> >  	struct device *dev;
> > @@ -619,6 +615,39 @@ int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map)
> >  
> >  	return device_add(dev);
> >  }
> > +EXPORT_SYMBOL_NS_GPL(cxl_decoder_add_locked, CXL);
> > +
> > +/**
> > + * cxl_decoder_add - Add a decoder with targets
> > + * @cxld: The cxl decoder allocated by cxl_decoder_alloc()
> > + * @target_map: A list of downstream ports that this decoder can direct memory
> > + *              traffic to. These numbers should correspond with the port number
> > + *              in the PCIe Link Capabilities structure.
> > + *
> > + * This is the unlocked variant of cxl_decoder_add_locked().
> > + * See cxl_decoder_add_locked().
> > + *
> > + * Context: Process context. Takes and releases the cxld's device lock.
> > + */
> > +int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map)
> > +{
> > +	struct cxl_port *port;
> > +	int rc;
> > +
> > +	if (WARN_ON_ONCE(!cxld))
> > +		return -EINVAL;
> 
> Why do we now need these protections but didn't before?

I don't quite understand what you're trying to point out.

Prior to this patch, cxl_decoder_add() checks:
- !cxld
- IS_ERR(cxld)
- cxld->interleave_ways != 0

After this patch, cxl_decoder_add() checks:
- !cxld
- IS_ERR(cxld)
- (and then calls cxl_decoder_add_locked())

And cxl_decoder_add_locked() checks:
- !cxld
- IS_ERR(cxld)
- cxld->interleave_ways != 0

Ultimately we want to check all 3, and since cxl_decoder_add() calls
cxl_decoder_add_locked(), we're good there. The problem is to get from a cxld to
a port, you need to make sure you have a valid cxld, and the API previously
allowed !cxld and IS_ERR(cxld). So there are duplicative checks if you call
cxl_decoder_add(), but other than that I don't see any new protections.

> 
> 
> > +
> > +	if (WARN_ON_ONCE(IS_ERR(cxld)))
> > +		return PTR_ERR(cxld);
> > +
> > +	port = to_cxl_port(cxld->dev.parent);
> > +
> > +	device_lock(&port->dev);
> > +	rc = cxl_decoder_add_locked(cxld, target_map);
> > +	device_unlock(&port->dev);
> > +
> > +	return rc;
> > +}
> >  EXPORT_SYMBOL_NS_GPL(cxl_decoder_add, CXL);
> >  
> >  static void cxld_unregister(void *dev)
> > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> > index b66ed8f241c6..2c5627fa8a34 100644
> > --- a/drivers/cxl/cxl.h
> > +++ b/drivers/cxl/cxl.h
> > @@ -290,6 +290,7 @@ struct cxl_decoder *to_cxl_decoder(struct device *dev);
> >  bool is_root_decoder(struct device *dev);
> >  struct cxl_decoder *cxl_decoder_alloc(struct cxl_port *port,
> >  				      unsigned int nr_targets);
> > +int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map);
> >  int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map);
> >  int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld);
> >  
> 

  reply	other threads:[~2021-11-22 21:58 UTC|newest]

Thread overview: 127+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-20  0:02 [PATCH 00/23] Add drivers for CXL ports and mem devices Ben Widawsky
2021-11-20  0:02 ` [PATCH 01/23] cxl: Rename CXL_MEM to CXL_PCI Ben Widawsky
2021-11-22 14:47   ` Jonathan Cameron
2021-11-24  4:15   ` Dan Williams
2021-11-20  0:02 ` [PATCH 02/23] cxl: Flesh out register names Ben Widawsky
2021-11-22 14:49   ` Jonathan Cameron
2021-11-24  4:24   ` Dan Williams
2021-11-20  0:02 ` [PATCH 03/23] cxl/pci: Extract device status check Ben Widawsky
2021-11-22 15:03   ` Jonathan Cameron
2021-11-24 19:30   ` Dan Williams
2021-11-20  0:02 ` [PATCH 04/23] cxl/pci: Implement Interface Ready Timeout Ben Widawsky
2021-11-22 15:02   ` Jonathan Cameron
2021-11-22 17:17     ` Ben Widawsky
2021-11-22 17:53       ` Jonathan Cameron
2021-11-24 19:56         ` Dan Williams
2021-11-25  6:17           ` Ben Widawsky
2021-11-25  7:14             ` Dan Williams
2021-11-20  0:02 ` [PATCH 05/23] cxl/pci: Don't poll doorbell for mailbox access Ben Widawsky
2021-11-22 15:11   ` Jonathan Cameron
2021-11-22 17:24     ` Ben Widawsky
2021-11-24 21:55   ` Dan Williams
2021-11-29 18:33     ` Ben Widawsky
2021-11-29 19:02       ` Dan Williams
2021-11-29 19:11         ` Ben Widawsky
2021-11-29 19:18           ` Dan Williams
2021-11-29 19:31             ` Ben Widawsky
2021-11-29 19:37               ` Dan Williams
2021-11-29 19:50                 ` Ben Widawsky
2021-11-20  0:02 ` [PATCH 06/23] cxl/pci: Don't check media status for mbox access Ben Widawsky
2021-11-22 15:19   ` Jonathan Cameron
2021-11-24 21:58   ` Dan Williams
2021-11-20  0:02 ` [PATCH 07/23] cxl/pci: Add new DVSEC definitions Ben Widawsky
2021-11-22 15:22   ` Jonathan Cameron
2021-11-22 17:32     ` Ben Widawsky
2021-11-24 22:03       ` Dan Williams
2021-11-20  0:02 ` [PATCH 08/23] cxl/acpi: Map component registers for Root Ports Ben Widawsky
2021-11-22 15:51   ` Jonathan Cameron
2021-11-22 19:28     ` Ben Widawsky
2021-11-24 22:18   ` Dan Williams
2021-11-20  0:02 ` [PATCH 09/23] cxl: Introduce module_cxl_driver Ben Widawsky
2021-11-22 15:54   ` Jonathan Cameron
2021-11-24 22:22   ` Dan Williams
2021-11-20  0:02 ` [PATCH 10/23] cxl/core: Convert decoder range to resource Ben Widawsky
2021-11-22 16:08   ` Jonathan Cameron
2021-11-24 22:41   ` Dan Williams
2021-11-20  0:02 ` [PATCH 11/23] cxl/core: Document and tighten up decoder APIs Ben Widawsky
2021-11-22 16:13   ` Jonathan Cameron
2021-11-24 22:55   ` Dan Williams
2021-11-20  0:02 ` [PATCH 12/23] cxl: Introduce endpoint decoders Ben Widawsky
2021-11-22 16:20   ` Jonathan Cameron
2021-11-22 19:37     ` Ben Widawsky
2021-11-25  0:07       ` Dan Williams
2021-11-29 20:05         ` Ben Widawsky
2021-11-29 20:07           ` Dan Williams
2021-11-29 20:12             ` Ben Widawsky
2021-11-20  0:02 ` [PATCH 13/23] cxl/core: Move target population locking to caller Ben Widawsky
2021-11-22 16:33   ` Jonathan Cameron
2021-11-22 21:58     ` Ben Widawsky [this message]
2021-11-23 11:05       ` Jonathan Cameron
2021-11-25  0:34   ` Dan Williams
2021-11-20  0:02 ` [PATCH 14/23] cxl: Introduce topology host registration Ben Widawsky
2021-11-22 18:20   ` Jonathan Cameron
2021-11-22 22:30     ` Ben Widawsky
2021-11-25  1:09   ` Dan Williams
2021-11-29 21:23     ` Ben Widawsky
2021-11-29 11:42   ` Dan Carpenter
2021-11-20  0:02 ` [PATCH 15/23] cxl/core: Store global list of root ports Ben Widawsky
2021-11-22 18:22   ` Jonathan Cameron
2021-11-22 22:32     ` Ben Widawsky
2021-11-20  0:02 ` [PATCH 16/23] cxl/pci: Cache device DVSEC offset Ben Widawsky
2021-11-22 16:46   ` Jonathan Cameron
2021-11-22 22:34     ` Ben Widawsky
2021-11-20  0:02 ` [PATCH 17/23] cxl: Cache and pass DVSEC ranges Ben Widawsky
2021-11-20  4:29   ` kernel test robot
2021-11-22 17:00   ` Jonathan Cameron
2021-11-22 22:50     ` Ben Widawsky
2021-11-26 11:37   ` Jonathan Cameron
2021-11-20  0:02 ` [PATCH 18/23] cxl/pci: Implement wait for media active Ben Widawsky
2021-11-22 17:03   ` Jonathan Cameron
2021-11-22 22:57     ` Ben Widawsky
2021-11-23 11:09       ` Jonathan Cameron
2021-11-23 16:04         ` Ben Widawsky
2021-11-23 17:48           ` Bjorn Helgaas
2021-11-23 19:37             ` Ben Widawsky
2021-11-26 11:36     ` Jonathan Cameron
2021-11-20  0:02 ` [PATCH 19/23] cxl/pci: Store component register base in cxlds Ben Widawsky
2021-11-20  7:28   ` kernel test robot
2021-11-22 17:11   ` Jonathan Cameron
2021-11-22 23:01     ` Ben Widawsky
2021-11-20  0:02 ` [PATCH 20/23] cxl/port: Introduce a port driver Ben Widawsky
2021-11-20  3:14   ` kernel test robot
2021-11-20  5:38   ` kernel test robot
2021-11-22 17:41   ` Jonathan Cameron
2021-11-22 23:38     ` Ben Widawsky
2021-11-23 11:38       ` Jonathan Cameron
2021-11-23 16:14         ` Ben Widawsky
2021-11-23 18:21   ` Bjorn Helgaas
2021-11-23 22:03     ` Ben Widawsky
2021-11-23 22:36       ` Dan Williams
2021-11-23 23:38         ` Ben Widawsky
2021-11-23 23:55         ` Bjorn Helgaas
2021-11-24  0:40           ` Dan Williams
2021-11-24  6:33             ` Christoph Hellwig
2021-11-24  7:17               ` Dan Williams
2021-11-24  7:28                 ` Christoph Hellwig
2021-11-24  7:33                   ` Greg Kroah-Hartman
2021-11-24  7:54                     ` Dan Williams
2021-11-24  8:21                       ` Greg Kroah-Hartman
2021-11-24 18:24                         ` Dan Williams
2021-12-02 21:24                 ` Bjorn Helgaas
2021-12-03  1:38                   ` Dan Williams
2021-12-03 22:03                     ` Bjorn Helgaas
2021-12-04  1:24                       ` Dan Williams
2021-12-07  2:56                         ` Bjorn Helgaas
2021-12-07  4:48                           ` Dan Williams
2021-11-24 21:31       ` Bjorn Helgaas
2021-11-20  0:02 ` [PATCH 21/23] cxl: Unify port enumeration for decoders Ben Widawsky
2021-11-22 17:48   ` Jonathan Cameron
2021-11-22 23:44     ` Ben Widawsky
2021-11-20  0:02 ` [PATCH 22/23] cxl/mem: Introduce cxl_mem driver Ben Widawsky
2021-11-20  0:40   ` Randy Dunlap
2021-11-21  3:55     ` Ben Widawsky
2021-11-22 18:17   ` Jonathan Cameron
2021-11-23  0:05     ` Ben Widawsky
2021-11-20  0:02 ` [PATCH 23/23] cxl/mem: Disable switch hierarchies for now Ben Widawsky
2021-11-22 18:19   ` Jonathan Cameron
2021-11-22 19:17     ` Ben Widawsky

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