From: Ben Widawsky <ben.widawsky@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
Alison Schofield <alison.schofield@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>
Subject: Re: [PATCH 20/23] cxl/port: Introduce a port driver
Date: Tue, 23 Nov 2021 08:14:43 -0800 [thread overview]
Message-ID: <20211123161443.6gsl67mskttwpoyo@intel.com> (raw)
In-Reply-To: <20211123113823.00007ce7@Huawei.com>
On 21-11-23 11:38:23, Jonathan Cameron wrote:
> On Mon, 22 Nov 2021 15:38:20 -0800
> Ben Widawsky <ben.widawsky@intel.com> wrote:
>
> ...
>
> > > > +static int enumerate_hdm_decoders(struct cxl_port *port,
> > > > + struct cxl_port_data *portdata)
> > > > +{
> > > > + void __iomem *hdm_decoder = portdata->regs.hdm_decoder;
> > > > + bool global_enable;
> > > > + u32 global_ctrl;
> > > > + int i = 0;
> > > > +
> > > > + global_ctrl = readl(hdm_decoder + CXL_HDM_DECODER_CTRL_OFFSET);
> > > > + global_enable = global_ctrl & CXL_HDM_DECODER_ENABLE;
> > > > + if (!global_enable) {
> > > > + i = dvsec_range_used(port);
> > > > + if (i) {
> > > > + dev_err(&port->dev,
> > > > + "Couldn't add port because device is using DVSEC range registers\n");
> > > > + return -EBUSY;
> > > > + }
> > > > + }
> > > > +
> > > > + for (i = 0; i < portdata->caps.count; i++) {
> > > > + int rc, target_count = portdata->caps.tc;
> > > > + struct cxl_decoder *cxld;
> > > > + int *target_map = NULL;
> > > > + u64 size;
> > > > +
> > > > + if (is_endpoint_port(port))
> > > > + target_count = 0;
> > > > +
> > > > + cxld = cxl_decoder_alloc(port, target_count);
> > > > + if (IS_ERR(cxld)) {
> > > > + dev_warn(&port->dev,
> > > > + "Failed to allocate the decoder\n");
> > > > + return PTR_ERR(cxld);
> > > > + }
> > > > +
> > > > + cxld->target_type = CXL_DECODER_EXPANDER;
> > > > + cxld->interleave_ways = 1;
> > > > + cxld->interleave_granularity = 0;
> > > > +
> > > > + size = get_decoder_size(hdm_decoder, i);
> > > > + if (size != 0) {
> > > > +#define decoderN(reg, n) hdm_decoder + CXL_HDM_DECODER0_##reg(n)
> > >
> > > Perhaps this block in the if (size != 0) would be more readable if broken out
> > > to a utility function?
> >
> > I don't get this comment, there is already get_decoder_size(). Can you please
> > elaborate?
>
> Sure. Just talking about having something like
>
> if (size != 0)
> init_decoder() // or something better named
>
> as an alternative to this deep nesting.
>
Sounds good. I can combine it with the similar initialization done in cxl_acpi.
> >
> > > As normal I'm not keen on the macro magic if we can avoid it.
> > >
> >
> > Yeah - just trying to not have to deal with wrapping long lines.
> >
> > >
> > > > + int temp[CXL_DECODER_MAX_INTERLEAVE];
> > > > + u64 base;
> > > > + u32 ctrl;
> > > > + int j;
> > > > + union {
> > > > + u64 value;
> > > > + char target_id[8];
> > > > + } target_list;
> > >
> > > I thought we tried to avoid this union usage in kernel because of the whole
> > > thing about c compilers being able to do what they like with it...
> > >
> >
> > I wasn't aware of the restriction. I can change it back if it's required. It
> > does look a lot nicer this way. Is there a reference to this issue somewhere?
>
> Hmm. Seems I was out of date on this. There is a mess in the c99 standard that
> contradicts itself on whether you can do this or not.
>
> https://davmac.wordpress.com/2010/02/26/c99-revisited/
Thanks for the link.
>
> The pull request for a patch form Andy got a Linus response...
>
> https://lore.kernel.org/all/CAJZ5v0jq45atkapwSjJ4DkHhB1bfOA-Sh1TiA3dPXwKyFTBheA@mail.gmail.com/
>
That was a fun read :-)
I'll defer to Dan on this. This was actually his code that he suggested in
review of the RFC.
>
> >
> > > > +
> > > > + target_map = temp;
> > >
> > > This is set to a variable that goes out of scope whilst target_map is still in
> > > use.
> > >
> >
> > Yikes. I'm pretty surprised the compiler didn't catch this.
> >
> > > > + ctrl = readl(decoderN(CTRL_OFFSET, i));
> > > > + base = ioread64_hi_lo(decoderN(BASE_LOW_OFFSET, i));
> > > > +
> > > > + cxld->decoder_range = (struct range){
> > > > + .start = base,
> > > > + .end = base + size - 1
> > > > + };
> > > > +
> > > > + cxld->flags = CXL_DECODER_F_ENABLE;
> > > > + cxld->interleave_ways = to_interleave_ways(ctrl);
> > > > + cxld->interleave_granularity =
> > > > + to_interleave_granularity(ctrl);
> > > > +
> > > > + if (FIELD_GET(CXL_HDM_DECODER0_CTRL_TYPE, ctrl) == 0)
> > > > + cxld->target_type = CXL_DECODER_ACCELERATOR;
> > > > +
> > > > + target_list.value = ioread64_hi_lo(decoderN(TL_LOW, i));
> > > > + for (j = 0; j < cxld->interleave_ways; j++)
> > > > + target_map[j] = target_list.target_id[j];
> > > > +#undef decoderN
> > > > + }
> > > > +
> > > > + rc = cxl_decoder_add_locked(cxld, target_map);
> > > > + if (rc)
> > > > + put_device(&cxld->dev);
> > > > + else
> > > > + rc = cxl_decoder_autoremove(&port->dev, cxld);
> > > > + if (rc)
> > > > + dev_err(&port->dev, "Failed to add decoder\n");
> > >
> > > If that fails on the autoremove registration (unlikely) this message
> > > will be rather confusing - as the add was fine...
> > >
> > > This nest of carrying on when we have an error is getting ever deeper...
> > >
> >
> > Yeah, this is not great. I will clean it up.
> >
> > Thanks.
> >
> > > > + else
> > > > + dev_dbg(&cxld->dev, "Added to port %s\n",
> > > > + dev_name(&port->dev));
> > > > + }
> > > > +
> > > > + /*
> > > > + * Turn on global enable now since DVSEC ranges aren't being used and
> > > > + * we'll eventually want the decoder enabled.
> > > > + */
> > > > + if (!global_enable) {
> > > > + dev_dbg(&port->dev, "Enabling HDM decode\n");
> > > > + writel(global_ctrl | CXL_HDM_DECODER_ENABLE, hdm_decoder + CXL_HDM_DECODER_CTRL_OFFSET);
> > > > + }
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
>
next prev parent reply other threads:[~2021-11-23 16:16 UTC|newest]
Thread overview: 127+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-20 0:02 [PATCH 00/23] Add drivers for CXL ports and mem devices Ben Widawsky
2021-11-20 0:02 ` [PATCH 01/23] cxl: Rename CXL_MEM to CXL_PCI Ben Widawsky
2021-11-22 14:47 ` Jonathan Cameron
2021-11-24 4:15 ` Dan Williams
2021-11-20 0:02 ` [PATCH 02/23] cxl: Flesh out register names Ben Widawsky
2021-11-22 14:49 ` Jonathan Cameron
2021-11-24 4:24 ` Dan Williams
2021-11-20 0:02 ` [PATCH 03/23] cxl/pci: Extract device status check Ben Widawsky
2021-11-22 15:03 ` Jonathan Cameron
2021-11-24 19:30 ` Dan Williams
2021-11-20 0:02 ` [PATCH 04/23] cxl/pci: Implement Interface Ready Timeout Ben Widawsky
2021-11-22 15:02 ` Jonathan Cameron
2021-11-22 17:17 ` Ben Widawsky
2021-11-22 17:53 ` Jonathan Cameron
2021-11-24 19:56 ` Dan Williams
2021-11-25 6:17 ` Ben Widawsky
2021-11-25 7:14 ` Dan Williams
2021-11-20 0:02 ` [PATCH 05/23] cxl/pci: Don't poll doorbell for mailbox access Ben Widawsky
2021-11-22 15:11 ` Jonathan Cameron
2021-11-22 17:24 ` Ben Widawsky
2021-11-24 21:55 ` Dan Williams
2021-11-29 18:33 ` Ben Widawsky
2021-11-29 19:02 ` Dan Williams
2021-11-29 19:11 ` Ben Widawsky
2021-11-29 19:18 ` Dan Williams
2021-11-29 19:31 ` Ben Widawsky
2021-11-29 19:37 ` Dan Williams
2021-11-29 19:50 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 06/23] cxl/pci: Don't check media status for mbox access Ben Widawsky
2021-11-22 15:19 ` Jonathan Cameron
2021-11-24 21:58 ` Dan Williams
2021-11-20 0:02 ` [PATCH 07/23] cxl/pci: Add new DVSEC definitions Ben Widawsky
2021-11-22 15:22 ` Jonathan Cameron
2021-11-22 17:32 ` Ben Widawsky
2021-11-24 22:03 ` Dan Williams
2021-11-20 0:02 ` [PATCH 08/23] cxl/acpi: Map component registers for Root Ports Ben Widawsky
2021-11-22 15:51 ` Jonathan Cameron
2021-11-22 19:28 ` Ben Widawsky
2021-11-24 22:18 ` Dan Williams
2021-11-20 0:02 ` [PATCH 09/23] cxl: Introduce module_cxl_driver Ben Widawsky
2021-11-22 15:54 ` Jonathan Cameron
2021-11-24 22:22 ` Dan Williams
2021-11-20 0:02 ` [PATCH 10/23] cxl/core: Convert decoder range to resource Ben Widawsky
2021-11-22 16:08 ` Jonathan Cameron
2021-11-24 22:41 ` Dan Williams
2021-11-20 0:02 ` [PATCH 11/23] cxl/core: Document and tighten up decoder APIs Ben Widawsky
2021-11-22 16:13 ` Jonathan Cameron
2021-11-24 22:55 ` Dan Williams
2021-11-20 0:02 ` [PATCH 12/23] cxl: Introduce endpoint decoders Ben Widawsky
2021-11-22 16:20 ` Jonathan Cameron
2021-11-22 19:37 ` Ben Widawsky
2021-11-25 0:07 ` Dan Williams
2021-11-29 20:05 ` Ben Widawsky
2021-11-29 20:07 ` Dan Williams
2021-11-29 20:12 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 13/23] cxl/core: Move target population locking to caller Ben Widawsky
2021-11-22 16:33 ` Jonathan Cameron
2021-11-22 21:58 ` Ben Widawsky
2021-11-23 11:05 ` Jonathan Cameron
2021-11-25 0:34 ` Dan Williams
2021-11-20 0:02 ` [PATCH 14/23] cxl: Introduce topology host registration Ben Widawsky
2021-11-22 18:20 ` Jonathan Cameron
2021-11-22 22:30 ` Ben Widawsky
2021-11-25 1:09 ` Dan Williams
2021-11-29 21:23 ` Ben Widawsky
2021-11-29 11:42 ` Dan Carpenter
2021-11-20 0:02 ` [PATCH 15/23] cxl/core: Store global list of root ports Ben Widawsky
2021-11-22 18:22 ` Jonathan Cameron
2021-11-22 22:32 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 16/23] cxl/pci: Cache device DVSEC offset Ben Widawsky
2021-11-22 16:46 ` Jonathan Cameron
2021-11-22 22:34 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 17/23] cxl: Cache and pass DVSEC ranges Ben Widawsky
2021-11-20 4:29 ` kernel test robot
2021-11-22 17:00 ` Jonathan Cameron
2021-11-22 22:50 ` Ben Widawsky
2021-11-26 11:37 ` Jonathan Cameron
2021-11-20 0:02 ` [PATCH 18/23] cxl/pci: Implement wait for media active Ben Widawsky
2021-11-22 17:03 ` Jonathan Cameron
2021-11-22 22:57 ` Ben Widawsky
2021-11-23 11:09 ` Jonathan Cameron
2021-11-23 16:04 ` Ben Widawsky
2021-11-23 17:48 ` Bjorn Helgaas
2021-11-23 19:37 ` Ben Widawsky
2021-11-26 11:36 ` Jonathan Cameron
2021-11-20 0:02 ` [PATCH 19/23] cxl/pci: Store component register base in cxlds Ben Widawsky
2021-11-20 7:28 ` kernel test robot
2021-11-22 17:11 ` Jonathan Cameron
2021-11-22 23:01 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 20/23] cxl/port: Introduce a port driver Ben Widawsky
2021-11-20 3:14 ` kernel test robot
2021-11-20 5:38 ` kernel test robot
2021-11-22 17:41 ` Jonathan Cameron
2021-11-22 23:38 ` Ben Widawsky
2021-11-23 11:38 ` Jonathan Cameron
2021-11-23 16:14 ` Ben Widawsky [this message]
2021-11-23 18:21 ` Bjorn Helgaas
2021-11-23 22:03 ` Ben Widawsky
2021-11-23 22:36 ` Dan Williams
2021-11-23 23:38 ` Ben Widawsky
2021-11-23 23:55 ` Bjorn Helgaas
2021-11-24 0:40 ` Dan Williams
2021-11-24 6:33 ` Christoph Hellwig
2021-11-24 7:17 ` Dan Williams
2021-11-24 7:28 ` Christoph Hellwig
2021-11-24 7:33 ` Greg Kroah-Hartman
2021-11-24 7:54 ` Dan Williams
2021-11-24 8:21 ` Greg Kroah-Hartman
2021-11-24 18:24 ` Dan Williams
2021-12-02 21:24 ` Bjorn Helgaas
2021-12-03 1:38 ` Dan Williams
2021-12-03 22:03 ` Bjorn Helgaas
2021-12-04 1:24 ` Dan Williams
2021-12-07 2:56 ` Bjorn Helgaas
2021-12-07 4:48 ` Dan Williams
2021-11-24 21:31 ` Bjorn Helgaas
2021-11-20 0:02 ` [PATCH 21/23] cxl: Unify port enumeration for decoders Ben Widawsky
2021-11-22 17:48 ` Jonathan Cameron
2021-11-22 23:44 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 22/23] cxl/mem: Introduce cxl_mem driver Ben Widawsky
2021-11-20 0:40 ` Randy Dunlap
2021-11-21 3:55 ` Ben Widawsky
2021-11-22 18:17 ` Jonathan Cameron
2021-11-23 0:05 ` Ben Widawsky
2021-11-20 0:02 ` [PATCH 23/23] cxl/mem: Disable switch hierarchies for now Ben Widawsky
2021-11-22 18:19 ` Jonathan Cameron
2021-11-22 19:17 ` Ben Widawsky
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