Re: [PATCH v2 20/21] cxl: Export sysfs attributes for memory device QTG ID

From: Dave Jiang <dave.jiang@intel.com>
To: Dan Williams <dan.j.williams@intel.com>,
	linux-cxl@vger.kernel.org, linux-acpi@vger.kernel.org
Cc: ira.weiny@intel.com, vishal.l.verma@intel.com,
	alison.schofield@intel.com, rafael@kernel.org, lukas@wunner.de
Subject: Re: [PATCH v2 20/21] cxl: Export sysfs attributes for memory device QTG ID
Date: Wed, 29 Mar 2023 15:02:32 -0700	[thread overview]
Message-ID: <6e282177-8084-78f8-3650-f9423d27f859@intel.com> (raw)
In-Reply-To: <6424b3e14b1ac_c722294d5@dwillia2-mobl3.amr.corp.intel.com.notmuch>

On 3/29/23 2:55 PM, Dan Williams wrote:
> Dave Jiang wrote:
>> Export qtg_id sysfs attributes for the CXL memory device. The QTG ID
>> should show up as /sys/bus/cxl/devices/memX/qtg_id. The QTG ID is
>> retrieved via _DSM after supplying the caluclated bandwidth and latency
>> for the entire CXL path from device to the CPU. This ID is used to match
>> up to the root decoder QTG ID to determine which CFMWS the memory range
>> of a hotplugged CXL mem device should be assigned under.
>>
>> While there may be multiple DSMAS exported by the device CDAT, the driver
>> will only expose the first QTG ID in sysfs for now. In the future when
>> multiple QTG IDs are necessary, they can be exposed. [1]
>>
>> [1]: https://lore.kernel.org/linux-cxl/167571650007.587790.10040913293130712882.stgit@djiang5-mobl3.local/T/#md2a47b1ead3e1ba08f50eab29a4af1aed1d215ab
>>
>> Suggested-by: Dan Williams <dan.j.williams@intel.com>
>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>> ---
>>   Documentation/ABI/testing/sysfs-bus-cxl |   11 +++++++++++
>>   drivers/cxl/core/memdev.c               |   15 +++++++++++++++
>>   2 files changed, 26 insertions(+)
>>
>> diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl
>> index 471ac9a37078..a018f0a21aca 100644
>> --- a/Documentation/ABI/testing/sysfs-bus-cxl
>> +++ b/Documentation/ABI/testing/sysfs-bus-cxl
>> @@ -58,6 +58,17 @@ Description:
>>   		affinity for this device.
>>   
>>   
>> +What:		/sys/bus/cxl/devices/memX/qtg_id
> 
> Oh, I was still thinking there would be a qtg_id per partition type,
> just not a multiple qtg_ids per partition type until it is clear that
> those are something hardware vendors are actually going to ship, but I
> expect a DSMAS per partition type will be common.

Oh ok. I guess I really need to save previous changes. Time to revert. I 
hope I still have the old cxl cli changes as well. :(

> 
> So I was expecting:
> 
> /sys/bus/cxl/devices/memX/{ram,pmem}/qtg_id
> 
> ...and when the DCD patches land that expands to:
> 
> /sys/bus/cxl/devices/memX/{ram,pmem,dcd[0-7]}/qtg_id
> 
> If someone builds a device with multiple performance classes per
> partition then it would become:
> 
> /sys/bus/cxl/devices/memX/{ram,pmem,dcd[0-7]}/qtg_id
> /sys/bus/cxl/devices/memX/{ram,pmem,dcd[0-7]}/qtg_id[1..n]
> /sys/bus/cxl/devices/memX/{ram,pmem,dcd[0-7]}/qtg_range/
> /sys/bus/cxl/devices/memX/{ram,pmem,dcd[0-7]}/qtg_range[1..n]/
> 
> ...where I am using CXL 3.0 Figure 9-24 "DCD DPA Space Example" as the
> delineation of the possible partition types.