From: Dave Jiang <dave.jiang@intel.com>
To: linux-cxl@vger.kernel.org, linux-acpi@vger.kernel.org
Cc: dan.j.williams@intel.com, ira.weiny@intel.com,
vishal.l.verma@intel.com, alison.schofield@intel.com,
rafael@kernel.org, lukas@wunner.de
Subject: Re: [PATCH v2 05/21] cxl: Add callback to parse the DSMAS subtables from CDAT
Date: Thu, 30 Mar 2023 08:43:05 -0700 [thread overview]
Message-ID: <ae2e391e-996b-a6c1-1a2b-1210cc7d1b14@intel.com> (raw)
In-Reply-To: <167995347254.2857312.246180486952683569.stgit@djiang5-mobl3>
On 3/27/23 2:44 PM, Dave Jiang wrote:
> Provide a callback function to the CDAT parser in order to parse the Device
> Scoped Memory Affinity Structure (DSMAS). Each DSMAS structure contains the
> DPA range and its associated attributes in each entry. See the CDAT
> specification for details.
>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>
> ---
> v2:
> - Add DSMAS table size check. (Lukas)
> - Use local DSMAS header for LE handling.
> - Remove dsmas lock. (Jonathan)
> - Fix handle size (Jonathan)
> - Add LE to host conversion for DSMAS address and length.
> - Make dsmas_list local
> ---
> drivers/cxl/core/cdat.c | 26 ++++++++++++++++++++++++++
> drivers/cxl/cxl.h | 1 +
> drivers/cxl/cxlpci.h | 18 ++++++++++++++++++
> drivers/cxl/port.c | 24 ++++++++++++++++++++++++
> 4 files changed, 69 insertions(+)
>
> diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c
> index 210f4499bddb..d068609fb6f9 100644
> --- a/drivers/cxl/core/cdat.c
> +++ b/drivers/cxl/core/cdat.c
> @@ -98,3 +98,29 @@ int cdat_table_parse_sslbis(struct cdat_header *table,
> return cdat_table_parse_entries(CDAT_TYPE_SSLBIS, table, &proc);
> }
> EXPORT_SYMBOL_NS_GPL(cdat_table_parse_sslbis, CXL);
> +
> +int cxl_dsmas_parse_entry(struct cdat_entry_header *header, void *arg)
> +{
> + struct cdat_dsmas *dsmas = (struct cdat_dsmas *)(header);
> + struct list_head *dsmas_list = (struct list_head *)arg;
> + struct dsmas_entry *dent;
> +
> + if (dsmas->hdr.length != sizeof(*dsmas)) {
> + pr_warn("Malformed DSMAS table length: (%lu:%u)\n",
> + (unsigned long)sizeof(*dsmas), dsmas->hdr.length);
> + return -EINVAL;
> + }
> +
> + dent = kzalloc(sizeof(*dent), GFP_KERNEL);
> + if (!dent)
> + return -ENOMEM;
> +
> + dent->handle = dsmas->dsmad_handle;
> + dent->dpa_range.start = le64_to_cpu(dsmas->dpa_base_address);
> + dent->dpa_range.end = le64_to_cpu(dsmas->dpa_base_address) +
> + le64_to_cpu(dsmas->dpa_length) - 1;
> + list_add_tail(&dent->list, dsmas_list);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_dsmas_parse_entry, CXL);
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index cc3309794b45..9d0e22fe72c0 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -8,6 +8,7 @@
> #include <linux/bitfield.h>
> #include <linux/bitops.h>
> #include <linux/log2.h>
> +#include <linux/list.h>
> #include <linux/io.h>
>
> /**
> diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
> index 45e2f2bf5ef8..9a2468a93d83 100644
> --- a/drivers/cxl/cxlpci.h
> +++ b/drivers/cxl/cxlpci.h
> @@ -104,6 +104,22 @@ struct cdat_subtable_entry {
> enum cdat_type type;
> };
>
> +struct dsmas_entry {
> + struct list_head list;
> + struct range dpa_range;
> + u8 handle;
> +};
> +
> +/* Sub-table 0: Device Scoped Memory Affinity Structure (DSMAS) */
> +struct cdat_dsmas {
> + struct cdat_entry_header hdr;
> + u8 dsmad_handle;
> + u8 flags;
> + __u16 reserved;
> + __le64 dpa_base_address;
> + __le64 dpa_length;
> +} __packed;
> +
> int devm_cxl_port_enumerate_dports(struct cxl_port *port);
> struct cxl_dev_state;
> int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm,
> @@ -119,4 +135,6 @@ int cdat_table_parse_##x(struct cdat_header *table, \
> cdat_table_parse(dsmas);
> cdat_table_parse(dslbis);
> cdat_table_parse(sslbis);
> +
> +int cxl_dsmas_parse_entry(struct cdat_entry_header *header, void *arg);
> #endif /* __CXL_PCI_H__ */
> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> index 60a865680e22..c8136797d528 100644
> --- a/drivers/cxl/port.c
> +++ b/drivers/cxl/port.c
> @@ -57,6 +57,16 @@ static int discover_region(struct device *dev, void *root)
> return 0;
> }
>
> +static void dsmas_list_destroy(struct list_head *dsmas_list)
> +{
> + struct dsmas_entry *dentry, *n;
> +
> + list_for_each_entry_safe(dentry, n, dsmas_list, list) {
> + list_del(&dentry->list);
> + kfree(dentry);
> + }
> +}
> +
> static int cxl_switch_port_probe(struct cxl_port *port)
> {
> struct cxl_hdm *cxlhdm;
> @@ -131,9 +141,23 @@ static int cxl_endpoint_port_probe(struct cxl_port *port)
> static int cxl_port_probe(struct device *dev)
> {
> struct cxl_port *port = to_cxl_port(dev);
> + int rc;
>
> /* Cache the data early to ensure is_visible() works */
> read_cdat_data(port);
> + if (port->cdat.table) {
> + if (is_cxl_endpoint(port)) {
> + LIST_HEAD(dsmas_list);
> +
> + rc = cdat_table_parse_dsmas(port->cdat.table,
> + cxl_dsmas_parse_entry,
> + (void *)&dsmas_list);
> + if (rc < 0)
> + dev_warn(dev, "Failed to parse DSMAS: %d\n", rc);
> +
> + dsmas_list_destroy(&dsmas_list);
> + }
> + }
This block needs to be moved to cxl_endpoint_port_probe() after media is
ready.
>
> if (is_cxl_endpoint(port))
> return cxl_endpoint_port_probe(port);
>
>
next prev parent reply other threads:[~2023-03-30 15:46 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-27 21:44 [PATCH v2 00/21] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-03-27 21:44 ` [PATCH v2 01/21] cxl: Export QTG ids from CFMWS to sysfs Dave Jiang
2023-03-29 23:57 ` Ira Weiny
2023-03-27 21:44 ` [PATCH v2 02/21] cxl: Add checksum verification to CDAT from CXL Dave Jiang
2023-03-29 0:03 ` Alison Schofield
2023-03-29 0:21 ` Dave Jiang
2023-03-30 0:09 ` Ira Weiny
2023-03-27 21:44 ` [PATCH v2 03/21] cxl: Add support for reading CXL switch CDAT table Dave Jiang
2023-03-30 0:19 ` Ira Weiny
2023-03-27 21:44 ` [PATCH v2 04/21] cxl: Add common helpers for cdat parsing Dave Jiang
2023-03-27 21:44 ` [PATCH v2 05/21] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-03-29 0:20 ` Alison Schofield
2023-03-29 20:41 ` Dave Jiang
2023-03-30 15:43 ` Dave Jiang [this message]
2023-03-27 21:44 ` [PATCH v2 06/21] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-03-29 0:44 ` Alison Schofield
2023-03-29 20:59 ` Dave Jiang
2023-03-29 21:59 ` Alison Schofield
2023-03-27 21:44 ` [PATCH v2 07/21] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-03-27 21:44 ` [PATCH v2 08/21] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-03-27 21:44 ` [PATCH v2 09/21] cxl: Add helper function to retrieve ACPI handle of CXL root device Dave Jiang
2023-03-27 21:45 ` [PATCH v2 10/21] cxl: Add helpers to calculate pci latency for the CXL device Dave Jiang
2023-03-27 21:45 ` [PATCH v2 11/21] cxl: Add helper function that calculates QoS values for switches Dave Jiang
2023-03-27 21:45 ` [PATCH v2 12/21] cxl: Add helper function that calculate QoS values for PCI path Dave Jiang
2023-03-27 21:45 ` [PATCH v2 13/21] ACPI: NUMA: Add genport target allocation to the HMAT parsing Dave Jiang
2023-03-27 21:45 ` [PATCH v2 14/21] ACPI: NUMA: Add helper function to retrieve the performance attributes Dave Jiang
2023-03-27 21:45 ` [PATCH v2 15/21] cxl: Add helper function to retrieve generic port QoS Dave Jiang
2023-03-27 21:45 ` [PATCH v2 16/21] cxl: Add latency and bandwidth calculations for the CXL path Dave Jiang
2023-03-27 21:45 ` [PATCH v2 17/21] cxl: Wait Memory_Info_Valid before access memory related info Dave Jiang
2023-03-27 21:45 ` [PATCH v2 18/21] cxl: Move identify and partition query from pci probe to port probe Dave Jiang
2023-03-27 21:46 ` [PATCH v2 19/21] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-03-27 21:46 ` [PATCH v2 20/21] cxl: Export sysfs attributes for memory device QTG ID Dave Jiang
2023-03-29 1:27 ` Alison Schofield
2023-03-29 21:44 ` Dave Jiang
2023-03-29 21:55 ` Dan Williams
2023-03-29 22:02 ` Dave Jiang
2023-03-27 21:46 ` [PATCH v2 21/21] cxl/mem: Add debugfs output for QTG related data Dave Jiang
2023-03-29 1:13 ` Alison Schofield
2023-03-29 21:49 ` Dave Jiang
2023-03-28 17:45 ` [PATCH v2 00/21] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
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