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From: Alison Schofield <alison.schofield@intel.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: linux-cxl@vger.kernel.org, linux-acpi@vger.kernel.org,
	dan.j.williams@intel.com, ira.weiny@intel.com,
	vishal.l.verma@intel.com, rafael@kernel.org, lukas@wunner.de
Subject: Re: [PATCH v2 06/21] cxl: Add callback to parse the DSLBIS subtable from CDAT
Date: Wed, 29 Mar 2023 14:59:01 -0700	[thread overview]
Message-ID: <ZCS0pShjnJM9v4vN@aschofie-mobl2> (raw)
In-Reply-To: <4f51aade-faf2-fa63-2795-3207d82c14aa@intel.com>

On Wed, Mar 29, 2023 at 01:59:12PM -0700, Dave Jiang wrote:
> 
> 
> On 3/28/23 5:44 PM, Alison Schofield wrote:
> > On Mon, Mar 27, 2023 at 02:44:39PM -0700, Dave Jiang wrote:
> > > Provide a callback to parse the Device Scoped Latency and Bandwidth
> > > Information Structure (DSLBIS) in the CDAT structures. The DSLBIS
> > > contains the bandwidth and latency information that's tied to a DSMAS
> > > handle. The driver will retrieve the read and write latency and
> > > bandwidth associated with the DSMAS which is tied to a DPA range.
> > > 
> > > Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> > > 
> > > ---
> > > v2:
> > > - Add size check to DSLIBIS table. (Lukas)
> > > - Remove unnecessary entry type check. (Jonathan)
> > > - Move data_type check to after match. (Jonathan)
> > > - Skip unknown data type. (Jonathan)
> > > - Add overflow check for unit multiply. (Jonathan)
> > > - Use dev_warn() when entries parsing fail. (Jonathan)
> > > ---
> > >   drivers/cxl/core/cdat.c |   41 +++++++++++++++++++++++++++++++++++++++++
> > >   drivers/cxl/cxlpci.h    |   34 +++++++++++++++++++++++++++++++++-
> > >   drivers/cxl/port.c      |    9 ++++++++-
> > >   3 files changed, 82 insertions(+), 2 deletions(-)
> > > 

snip

> > > --- a/drivers/cxl/port.c
> > > +++ b/drivers/cxl/port.c
> > > @@ -152,8 +152,15 @@ static int cxl_port_probe(struct device *dev)
> > >   			rc = cdat_table_parse_dsmas(port->cdat.table,
> > >   						    cxl_dsmas_parse_entry,
> > >   						    (void *)&dsmas_list);
> > > -			if (rc < 0)
> > > +			if (rc > 0) {
> > > +				rc = cdat_table_parse_dslbis(port->cdat.table,
> > > +							     cxl_dslbis_parse_entry,
> > > +							     (void *)&dsmas_list);
> > > +				if (rc <= 0)
> > > +					dev_warn(dev, "Failed to parse DSLBIS: %d\n", rc);
> > > +			} else {
> > >   				dev_warn(dev, "Failed to parse DSMAS: %d\n", rc);
> > > +			}
> > 
> > I see you touch this func more than once. Maybe some earlier nips and
> > tucks, makes this more readable.
> 
> Not sure what you mean.

I thought this was the same func, cxl_port_probe(), that I commented
on in the previous patch, so maybe it was already getting re-aligned.

> 
> > 
> > >   			dsmas_list_destroy(&dsmas_list);
> > >   		}
> > > 
> > > 

  reply	other threads:[~2023-03-29 21:59 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-27 21:44 [PATCH v2 00/21] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-03-27 21:44 ` [PATCH v2 01/21] cxl: Export QTG ids from CFMWS to sysfs Dave Jiang
2023-03-29 23:57   ` Ira Weiny
2023-03-27 21:44 ` [PATCH v2 02/21] cxl: Add checksum verification to CDAT from CXL Dave Jiang
2023-03-29  0:03   ` Alison Schofield
2023-03-29  0:21     ` Dave Jiang
2023-03-30  0:09   ` Ira Weiny
2023-03-27 21:44 ` [PATCH v2 03/21] cxl: Add support for reading CXL switch CDAT table Dave Jiang
2023-03-30  0:19   ` Ira Weiny
2023-03-27 21:44 ` [PATCH v2 04/21] cxl: Add common helpers for cdat parsing Dave Jiang
2023-03-27 21:44 ` [PATCH v2 05/21] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-03-29  0:20   ` Alison Schofield
2023-03-29 20:41     ` Dave Jiang
2023-03-30 15:43   ` Dave Jiang
2023-03-27 21:44 ` [PATCH v2 06/21] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-03-29  0:44   ` Alison Schofield
2023-03-29 20:59     ` Dave Jiang
2023-03-29 21:59       ` Alison Schofield [this message]
2023-03-27 21:44 ` [PATCH v2 07/21] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-03-27 21:44 ` [PATCH v2 08/21] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-03-27 21:44 ` [PATCH v2 09/21] cxl: Add helper function to retrieve ACPI handle of CXL root device Dave Jiang
2023-03-27 21:45 ` [PATCH v2 10/21] cxl: Add helpers to calculate pci latency for the CXL device Dave Jiang
2023-03-27 21:45 ` [PATCH v2 11/21] cxl: Add helper function that calculates QoS values for switches Dave Jiang
2023-03-27 21:45 ` [PATCH v2 12/21] cxl: Add helper function that calculate QoS values for PCI path Dave Jiang
2023-03-27 21:45 ` [PATCH v2 13/21] ACPI: NUMA: Add genport target allocation to the HMAT parsing Dave Jiang
2023-03-27 21:45 ` [PATCH v2 14/21] ACPI: NUMA: Add helper function to retrieve the performance attributes Dave Jiang
2023-03-27 21:45 ` [PATCH v2 15/21] cxl: Add helper function to retrieve generic port QoS Dave Jiang
2023-03-27 21:45 ` [PATCH v2 16/21] cxl: Add latency and bandwidth calculations for the CXL path Dave Jiang
2023-03-27 21:45 ` [PATCH v2 17/21] cxl: Wait Memory_Info_Valid before access memory related info Dave Jiang
2023-03-27 21:45 ` [PATCH v2 18/21] cxl: Move identify and partition query from pci probe to port probe Dave Jiang
2023-03-27 21:46 ` [PATCH v2 19/21] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-03-27 21:46 ` [PATCH v2 20/21] cxl: Export sysfs attributes for memory device QTG ID Dave Jiang
2023-03-29  1:27   ` Alison Schofield
2023-03-29 21:44     ` Dave Jiang
2023-03-29 21:55   ` Dan Williams
2023-03-29 22:02     ` Dave Jiang
2023-03-27 21:46 ` [PATCH v2 21/21] cxl/mem: Add debugfs output for QTG related data Dave Jiang
2023-03-29  1:13   ` Alison Schofield
2023-03-29 21:49     ` Dave Jiang
2023-03-28 17:45 ` [PATCH v2 00/21] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang

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