* [RFC PATCH v2 0/4] CXL 3.0 Performance Monitoring Unit support
@ 2022-08-24 10:36 Jonathan Cameron
2022-08-24 10:36 ` [RFC PATCH v2 1/4] cxl: Add function to count regblocks of a given type Jonathan Cameron
` (3 more replies)
0 siblings, 4 replies; 12+ messages in thread
From: Jonathan Cameron @ 2022-08-24 10:36 UTC (permalink / raw)
To: linux-cxl, Dan Williams, Alison Schofield, Vishal Verma,
Ira Weiny, Ben Widawsky, linux-perf-users, Will Deacon,
Mark Rutland
Cc: linuxarm
v2:
- Fix up various build issues, mostly 32bit related (BIT_ULL needed
in various places for example) found by kernel test robot <lkp@intel.com>
The CXL rev 3.0 specification introduces a CXL Performance Monitoring
Unit definition. CXL components may have any number of these blocks. The
definition is highly flexible, but that does bring complexity in the
driver.
Initially posted as an RFC for a number of reasons.
1) The QEMU model against which this was developed needs tidying up and
review for correctness. I'll reply with a link to that thread once
the QEMU code has been posted for review.
2) There are quite a lot of corner cases that will need working through
with variants of the model, or I'll have to design a pathological
set of CPMUs to hit all the corner cases in one go.
3) I'm not sure it makes sense to hang this of the cxl/pci driver but
couldn't really figure out where else in the current structure we could
make it fit cleanly.
4) The interrupt initialization code is something we talked about for DOE
but in the end DOE interrupt support was dropped (for now). It requires
the cxl/pci driver to do a small amount of parsing of registers otherwise
only relevant to the CPMU driver in order to establish what interrupt
vector the CPMU is using and hence ensure the cxl/pci driver requests
sufficient vectors. Given this effects how other interrupts will be
handled in cxl/pci, we need to confirm the handle in general enough
to not need a complete rewrite when we add another interrupt use case.
5) I'm not sure how to expose to user space the sets of events that may
be summed (given by a mask in the Counter Event Capabilities registers).
For now the driver advertises the individual events. Each individual
event may form part of multiple overlapping groups for example.
It may be a case of these allowed combinations only being discoverable
by requesting a combination and checking for errors on start.
6) Driver location. In past perf maintainers have requested perf drivers
for PCI etc be under drivers/perf. That would require moving some
CXL headers to be more generally visible, but is certainly possible
if there is agreement between CXL and perf maintainers on the correct
location.
7) Documentation needs improving, but I didn't want to spend too much
time on that whilst we have so many open questions. I'll separately
raise the question about pmu->dev parenting which is mentioned in the
Docs patch introduction.
CXL rev 3.0 specification available from https://www.computeexpresslink.org
Jonathan Cameron (4):
cxl: Add function to count regblocks of a given type.
cxl/pci: Find and register CXL PMU devices
cxl: CXL Performance Monitoring Unit driver
docs: perf: Minimal introduction the the CXL PMU device and driver.
Documentation/admin-guide/perf/cxl.rst | 60 ++
Documentation/admin-guide/perf/index.rst | 1 +
drivers/cxl/Kconfig | 12 +
drivers/cxl/Makefile | 1 +
drivers/cxl/core/Makefile | 1 +
drivers/cxl/core/core.h | 3 +
drivers/cxl/core/cpmu.c | 69 ++
drivers/cxl/core/pci.c | 2 +-
drivers/cxl/core/port.c | 4 +-
drivers/cxl/core/regs.c | 64 +-
drivers/cxl/cpmu.c | 945 +++++++++++++++++++++++
drivers/cxl/cpmu.h | 54 ++
drivers/cxl/cxl.h | 16 +
drivers/cxl/cxlpci.h | 1 +
drivers/cxl/pci.c | 78 +-
15 files changed, 1304 insertions(+), 7 deletions(-)
create mode 100644 Documentation/admin-guide/perf/cxl.rst
create mode 100644 drivers/cxl/core/cpmu.c
create mode 100644 drivers/cxl/cpmu.c
create mode 100644 drivers/cxl/cpmu.h
--
2.32.0
^ permalink raw reply [flat|nested] 12+ messages in thread
* [RFC PATCH v2 1/4] cxl: Add function to count regblocks of a given type.
2022-08-24 10:36 [RFC PATCH v2 0/4] CXL 3.0 Performance Monitoring Unit support Jonathan Cameron
@ 2022-08-24 10:36 ` Jonathan Cameron
2022-09-22 20:19 ` Dave Jiang
2022-08-24 10:36 ` [RFC PATCH v2 2/4] cxl/pci: Find and register CXL PMU devices Jonathan Cameron
` (2 subsequent siblings)
3 siblings, 1 reply; 12+ messages in thread
From: Jonathan Cameron @ 2022-08-24 10:36 UTC (permalink / raw)
To: linux-cxl, Dan Williams, Alison Schofield, Vishal Verma,
Ira Weiny, Ben Widawsky, linux-perf-users, Will Deacon,
Mark Rutland
Cc: linuxarm
Until the recently release CXL 3.0 specification, there
was only ever one instance of any given register block pointed
to by the Register Block Locator DVSEC. Now, the specification allows
for multiple CXL PMU instances, each with their own register block.
To enable this add an index parameter to cxl_find_regblock()
and use that to implement cxl_count_regblock().
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
drivers/cxl/core/pci.c | 2 +-
drivers/cxl/core/port.c | 2 +-
drivers/cxl/core/regs.c | 35 ++++++++++++++++++++++++++++++++---
drivers/cxl/cxl.h | 3 ++-
drivers/cxl/pci.c | 2 +-
5 files changed, 37 insertions(+), 7 deletions(-)
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 9240df53ed87..f29cdc9df330 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -49,7 +49,7 @@ static int match_add_dports(struct pci_dev *pdev, void *data)
&lnkcap))
return 0;
- rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
+ rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map, 0);
if (rc)
dev_dbg(&port->dev, "failed to find component registers\n");
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index bffde862de0b..1629c7a4033f 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -1235,7 +1235,7 @@ static resource_size_t find_component_registers(struct device *dev)
pdev = to_pci_dev(dev);
- cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
+ cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map, 0);
return cxl_regmap_to_base(pdev, &map);
}
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index 39a129c57d40..2f651211d120 100644
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -262,6 +262,7 @@ static void cxl_decode_regblock(u32 reg_lo, u32 reg_hi,
* @pdev: The CXL PCI device to enumerate.
* @type: Register Block Indicator id
* @map: Enumeration output, clobbered on error
+ * @index: Index into which particular instance of a regblock we want.
*
* Return: 0 if register block enumerated, negative error code otherwise
*
@@ -269,9 +270,10 @@ static void cxl_decode_regblock(u32 reg_lo, u32 reg_hi,
* by @type.
*/
int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
- struct cxl_register_map *map)
+ struct cxl_register_map *map, int index)
{
u32 regloc_size, regblocks;
+ int instance = 0;
int regloc, i;
map->block_offset = U64_MAX;
@@ -294,11 +296,38 @@ int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
cxl_decode_regblock(reg_lo, reg_hi, map);
- if (map->reg_type == type)
- return 0;
+ if (map->reg_type == type) {
+ if (index == instance)
+ return 0;
+ instance++;
+ }
}
map->block_offset = U64_MAX;
return -ENODEV;
}
EXPORT_SYMBOL_NS_GPL(cxl_find_regblock, CXL);
+
+/**
+ * cxl_count_regblock() - Count instances of a given regblock type.
+ * @pdev: The CXL PCI device to enumerate.
+ * @type: Register Block Indicator id
+ *
+ * Some regblocks may be repeated. Count how many instances.
+ *
+ * Return: count of matching regblocks.
+ */
+int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type)
+{
+ struct cxl_register_map map;
+ int rc, count = 0;
+
+ while (1) {
+ rc = cxl_find_regblock(pdev, type, &map, count);
+ if (rc)
+ return count;
+ count++;
+ }
+}
+EXPORT_SYMBOL_NS_GPL(cxl_count_regblock, CXL);
+
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index f680450f0b16..5a1bcdbda654 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -216,8 +216,9 @@ int cxl_map_device_regs(struct pci_dev *pdev,
struct cxl_register_map *map);
enum cxl_regloc_type;
+int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type);
int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
- struct cxl_register_map *map);
+ struct cxl_register_map *map, int index);
void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
resource_size_t length);
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index faeb5d9d7a7a..1758380247ec 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -373,7 +373,7 @@ static int cxl_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
{
int rc;
- rc = cxl_find_regblock(pdev, type, map);
+ rc = cxl_find_regblock(pdev, type, map, 0);
if (rc)
return rc;
--
2.32.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [RFC PATCH v2 2/4] cxl/pci: Find and register CXL PMU devices
2022-08-24 10:36 [RFC PATCH v2 0/4] CXL 3.0 Performance Monitoring Unit support Jonathan Cameron
2022-08-24 10:36 ` [RFC PATCH v2 1/4] cxl: Add function to count regblocks of a given type Jonathan Cameron
@ 2022-08-24 10:36 ` Jonathan Cameron
2022-09-01 22:36 ` Dave Jiang
2022-08-24 10:36 ` [RFC PATCH v2 3/4] cxl: CXL Performance Monitoring Unit driver Jonathan Cameron
2022-08-24 10:36 ` [RFC PATCH v2 4/4] docs: perf: Minimal introduction the the CXL PMU device and driver Jonathan Cameron
3 siblings, 1 reply; 12+ messages in thread
From: Jonathan Cameron @ 2022-08-24 10:36 UTC (permalink / raw)
To: linux-cxl, Dan Williams, Alison Schofield, Vishal Verma,
Ira Weiny, Ben Widawsky, linux-perf-users, Will Deacon,
Mark Rutland
Cc: linuxarm
CXL PMU devices can be found from entries in the Register
Locator DVSEC.
In order to register the minimum number of IRQ vectors necessary
to support all CPMUs found, separate the registration into two
steps. First find the devices, and query the IRQs used and then
register the devices. Between these two steps, request the
IRQ vectors necessary and enable bus master support.
Future IRQ users for CXL type 3 devices (e.g. DOEs) will need to
follow a similar pattern the number of vectors necessary is known
before any parts of the driver stack rely on their availability.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
Open questions
1) Is this IRQ vector 'count' / request then use approach flexible
enough for other interrupt users on these devices.
2) Does hanging the CPMU off the PCI device make sense. These can
occur in Switch upstream ports as well.
3) Naming. It would be nice if the device naming indicated which
EP these were associated with, but that wouldn't be inline
with the rest of the CXL bus device naming. What is best
option here?
---
drivers/cxl/core/Makefile | 1 +
drivers/cxl/core/core.h | 3 ++
drivers/cxl/core/cpmu.c | 69 +++++++++++++++++++++++++++++++++++
drivers/cxl/core/port.c | 2 ++
drivers/cxl/core/regs.c | 29 +++++++++++++++
drivers/cxl/cpmu.h | 54 ++++++++++++++++++++++++++++
drivers/cxl/cxl.h | 15 ++++++++
drivers/cxl/cxlpci.h | 1 +
drivers/cxl/pci.c | 76 ++++++++++++++++++++++++++++++++++++++-
9 files changed, 249 insertions(+), 1 deletion(-)
diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile
index 79c7257f4107..1318e8a6830f 100644
--- a/drivers/cxl/core/Makefile
+++ b/drivers/cxl/core/Makefile
@@ -10,4 +10,5 @@ cxl_core-y += memdev.o
cxl_core-y += mbox.o
cxl_core-y += pci.o
cxl_core-y += hdm.o
+cxl_core-y += cpmu.o
cxl_core-$(CONFIG_CXL_REGION) += region.o
diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
index 1d8f87be283f..d2b12cdfd61f 100644
--- a/drivers/cxl/core/core.h
+++ b/drivers/cxl/core/core.h
@@ -14,12 +14,14 @@ extern struct device_attribute dev_attr_create_pmem_region;
extern struct device_attribute dev_attr_delete_region;
extern struct device_attribute dev_attr_region;
extern const struct device_type cxl_pmem_region_type;
+extern const struct device_type cxl_cpmu_type;
extern const struct device_type cxl_region_type;
void cxl_decoder_kill_region(struct cxl_endpoint_decoder *cxled);
#define CXL_REGION_ATTR(x) (&dev_attr_##x.attr)
#define CXL_REGION_TYPE(x) (&cxl_region_type)
#define SET_CXL_REGION_ATTR(x) (&dev_attr_##x.attr),
#define CXL_PMEM_REGION_TYPE(x) (&cxl_pmem_region_type)
+#define CXL_CPMU_TYPE(x) (&cxl_cpmu_region_type)
int cxl_region_init(void);
void cxl_region_exit(void);
#else
@@ -37,6 +39,7 @@ static inline void cxl_region_exit(void)
#define CXL_REGION_TYPE(x) NULL
#define SET_CXL_REGION_ATTR(x)
#define CXL_PMEM_REGION_TYPE(x) NULL
+#define CXL_CPMU_TYPE(x) NULL
#endif
struct cxl_send_command;
diff --git a/drivers/cxl/core/cpmu.c b/drivers/cxl/core/cpmu.c
new file mode 100644
index 000000000000..cad02f3d43c3
--- /dev/null
+++ b/drivers/cxl/core/cpmu.c
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright(c) 2022 Huawei. All rights reserved. */
+
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/idr.h>
+#include <cxlmem.h>
+#include <cpmu.h>
+#include <cxl.h>
+#include "core.h"
+
+static DEFINE_IDA(cpmu_ida);
+
+static void cxl_cpmu_release(struct device *dev)
+{
+ struct cxl_cpmu *cpmu = container_of(dev, struct cxl_cpmu, dev);
+
+ ida_free(&cpmu_ida, cpmu->id);
+ kfree(cpmu);
+}
+
+const struct device_type cxl_cpmu_type = {
+ .name = "cxl_cpmu",
+ .release = cxl_cpmu_release,
+};
+
+static void remove_dev(void *dev)
+{
+ device_del(dev);
+}
+
+int devm_cxl_cpmu_add(struct device *parent, struct cxl_cpmu_regs *regs, int index)
+{
+ struct cxl_cpmu *cpmu;
+ struct device *dev;
+ int rc;
+
+ cpmu = kzalloc(sizeof(*cpmu), GFP_KERNEL);
+ if (!cpmu)
+ return -ENOMEM;
+
+ cpmu->base = regs->cpmu;
+ dev = &cpmu->dev;
+ device_initialize(dev);
+ device_set_pm_not_required(dev);
+ dev->parent = parent;
+ dev->bus = &cxl_bus_type;
+ dev->type = &cxl_cpmu_type;
+ rc = ida_alloc(&cpmu_ida, GFP_KERNEL);
+ if (rc < 0)
+ goto err;
+ cpmu->id = rc;
+
+ rc = dev_set_name(dev, "cpmu%d", cpmu->id);
+ if (rc)
+ goto err;
+
+ rc = device_add(dev);
+ if (rc)
+ goto err;
+
+ return devm_add_action_or_reset(parent, remove_dev, dev);
+
+err:
+ put_device(&cpmu->dev);
+ return rc;
+}
+EXPORT_SYMBOL_NS_GPL(devm_cxl_cpmu_add, CXL);
+
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 1629c7a4033f..66bde8e2edb8 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -55,6 +55,8 @@ static int cxl_device_id(struct device *dev)
return CXL_DEVICE_MEMORY_EXPANDER;
if (dev->type == CXL_REGION_TYPE())
return CXL_DEVICE_REGION;
+ if (dev->type == &cxl_cpmu_type)
+ return CXL_DEVICE_CPMU;
return 0;
}
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index 2f651211d120..1ba1a77ecbf1 100644
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -6,6 +6,7 @@
#include <linux/pci.h>
#include <cxlmem.h>
#include <cxlpci.h>
+#include <cpmu.h>
/**
* DOC: cxl registers
@@ -331,3 +332,31 @@ int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type)
}
EXPORT_SYMBOL_NS_GPL(cxl_count_regblock, CXL);
+int cxl_map_cpmu_regs(struct pci_dev *pdev,
+ struct cxl_cpmu_regs *regs,
+ struct cxl_register_map *map)
+{
+ struct device *dev = &pdev->dev;
+ resource_size_t phys_addr;
+
+ phys_addr = pci_resource_start(pdev, map->barno) + map->block_offset;
+ regs->cpmu = devm_cxl_iomap_block(dev, phys_addr, CPMU_REGMAP_SIZE);
+ if (!regs->cpmu)
+ return -ENOMEM;
+
+ return 0;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_map_cpmu_regs, CXL);
+
+int cxl_cpmu_get_irq(struct cxl_cpmu_regs *regs)
+{
+ int irq = -1;
+ u64 val;
+
+ val = readq(regs->cpmu + CPMU_CAP_REG);
+ if (FIELD_GET(CPMU_CAP_INT, val))
+ irq = FIELD_GET(CPMU_CAP_MSI_N_MSK, val);
+
+ return irq;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_cpmu_get_irq, CXL);
diff --git a/drivers/cxl/cpmu.h b/drivers/cxl/cpmu.h
new file mode 100644
index 000000000000..2db885524330
--- /dev/null
+++ b/drivers/cxl/cpmu.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright(c) 2022 Huawei
+ * CXL Specification rev 3.0 Setion 8.2.7 (CPMU Register Interface)
+ */
+#ifndef CXL_CPMU_H
+#define CXL_CPMU_H
+
+#define CPMU_CAP_REG 0x0
+#define CPMU_CAP_NUM_COUNTERS_MSK GENMASK_ULL(4, 0)
+#define CPMU_CAP_COUNTER_WIDTH_MSK GENMASK_ULL(15, 8)
+#define CPMU_CAP_NUM_EVN_CAP_REG_SUP_MSK GENMASK_ULL(24, 20)
+#define CPMU_CAP_FILTERS_SUP_MSK GENMASK_ULL(39, 32)
+#define CPMU_CAP_MSI_N_MSK GENMASK_ULL(47, 44)
+#define CPMU_CAP_WRITEABLE_WHEN_FROZEN BIT_ULL(48)
+#define CPMU_CAP_FREEZE BIT_ULL(49)
+#define CPMU_CAP_INT BIT_ULL(50)
+#define CPMU_CAP_VERSION_MSK GENMASK_ULL(63, 60)
+
+#define CPMU_OVERFLOW_REG 0x10
+#define CPMU_FREEZE_REG 0x18
+#define CPMU_EVENT_CAP_REG(n) (0x100 + 8 * (n))
+#define CPMU_EVENT_CAP_SUPPORTED_EVENTS_MSK GENMASK_ULL(31, 0)
+#define CPMU_EVENT_CAP_GROUP_ID_MSK GENMASK_ULL(47, 32)
+#define CPMU_EVENT_CAP_VENDOR_ID_MSK GENMASK_ULL(63, 48)
+
+#define CPMU_COUNTER_CFG_REG(n) (0x200 + 8 * (n))
+#define CPMU_COUNTER_CFG_TYPE_MSK GENMASK_ULL(1, 0)
+#define CPMU_COUNTER_CFG_TYPE_FREE_RUN 0
+#define CPMU_COUNTER_CFG_TYPE_FIXED_FUN 1
+#define CPMU_COUNTER_CFG_TYPE_CONFIGURABLE 2
+#define CPMU_COUNTER_CFG_ENABLE BIT_ULL(8)
+#define CPMU_COUNTER_CFG_INT_ON_OVRFLW BIT_ULL(9)
+#define CPMU_COUNTER_CFG_FREEZE_ON_OVRFLW BIT_ULL(10)
+#define CPMU_COUNTER_CFG_EDGE BIT_ULL(11)
+#define CPMU_COUNTER_CFG_INVERT BIT_ULL(12)
+#define CPMU_COUNTER_CFG_THRESHOLD_MSK GENMASK_ULL(23, 16)
+#define CPMU_COUNTER_CFG_EVENTS_MSK GENMASK_ULL(55, 24)
+#define CPMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK GENMASK_ULL(63, 59)
+
+#define CPMU_FILTER_CFG_REG(n, f) (0x400 + 4 * ((f) + (n) * 8))
+#define CPMU_FILTER_CFG_VALUE_MSK GENMASK(15, 0)
+
+#define CPMU_COUNTER_REG(n) (0xc00 + 8 * (n))
+
+#define CPMU_REGMAP_SIZE 0xe00 /* Table 8-32 CXL 3.0 specification */
+struct cxl_cpmu {
+ struct device dev;
+ void __iomem *base;
+ int id;
+};
+
+#define to_cxl_cpmu(dev) container_of(dev, struct cxl_cpmu, dev)
+#endif
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 5a1bcdbda654..2768e1677e2b 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -166,6 +166,10 @@ struct cxl_regs {
struct_group_tagged(cxl_device_regs, device_regs,
void __iomem *status, *mbox, *memdev;
);
+
+ struct_group_tagged(cxl_cpmu_regs, cpmu_regs,
+ void __iomem *cpmu;
+ );
};
struct cxl_reg_map {
@@ -184,6 +188,10 @@ struct cxl_device_reg_map {
struct cxl_reg_map memdev;
};
+struct cxl_cpmu_reg_map {
+ struct cxl_reg_map cpmu;
+};
+
/**
* struct cxl_register_map - DVSEC harvested register block mapping parameters
* @base: virtual base of the register-block-BAR + @block_offset
@@ -201,6 +209,7 @@ struct cxl_register_map {
union {
struct cxl_component_reg_map component_map;
struct cxl_device_reg_map device_map;
+ struct cxl_cpmu_reg_map cpmu_map;
};
};
@@ -219,6 +228,10 @@ enum cxl_regloc_type;
int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type);
int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
struct cxl_register_map *map, int index);
+int cxl_map_cpmu_regs(struct pci_dev *pdev,
+ struct cxl_cpmu_regs *regs,
+ struct cxl_register_map *map);
+int cxl_cpmu_get_irq(struct cxl_cpmu_regs *regs);
void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
resource_size_t length);
@@ -626,6 +639,7 @@ void cxl_driver_unregister(struct cxl_driver *cxl_drv);
#define CXL_DEVICE_MEMORY_EXPANDER 5
#define CXL_DEVICE_REGION 6
#define CXL_DEVICE_PMEM_REGION 7
+#define CXL_DEVICE_CPMU 8
#define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*")
#define CXL_MODALIAS_FMT "cxl:t%d"
@@ -653,6 +667,7 @@ static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev)
}
#endif
+int devm_cxl_cpmu_add(struct device *parent, struct cxl_cpmu_regs *regs, int idx);
/*
* Unit test builds overrides this to __weak, find the 'strong' version
* of these symbols in tools/testing/cxl/.
diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
index eec597dbe763..a842c3d1341a 100644
--- a/drivers/cxl/cxlpci.h
+++ b/drivers/cxl/cxlpci.h
@@ -59,6 +59,7 @@ enum cxl_regloc_type {
CXL_REGLOC_RBI_COMPONENT,
CXL_REGLOC_RBI_VIRT,
CXL_REGLOC_RBI_MEMDEV,
+ CXL_REGLOC_RBI_CPMU,
CXL_REGLOC_RBI_TYPES
};
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 1758380247ec..e1276fdc8609 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -428,12 +428,39 @@ static void devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds)
}
}
+static void cxl_pci_free_irq_vectors(void *data)
+{
+ pci_free_irq_vectors(data);
+}
+
+static int cxl_alloc_irq_vectors(struct cxl_dev_state *cxlds, int vectors)
+{
+ struct device *dev = cxlds->dev;
+ struct pci_dev *pdev = to_pci_dev(dev);
+ int rc;
+
+ rc = pci_alloc_irq_vectors(pdev, vectors, vectors,
+ PCI_IRQ_MSI | PCI_IRQ_MSIX);
+ if (rc < 0)
+ return rc;
+ if (rc != vectors) {
+ pci_err(pdev, "Not enough interrupts; use polling where supported\n");
+ /* Some got allocated; clean them up */
+ cxl_pci_free_irq_vectors(pdev);
+ return -ENOSPC;
+ }
+
+ return devm_add_action_or_reset(dev, cxl_pci_free_irq_vectors, pdev);
+}
+
static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
+ struct cxl_cpmu_regs *cpmu_regs_array = NULL;
struct cxl_register_map map;
struct cxl_memdev *cxlmd;
struct cxl_dev_state *cxlds;
- int rc;
+ int i, rc, cpmu_count;
+ int max_interrupt = -1;
/*
* Double check the anonymous union trickery in struct cxl_regs
@@ -494,6 +521,53 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
if (rc)
return rc;
+ /*
+ * Before registering sub devices that use interrupts, the maximum
+ * interrupt used on the device should be established to allow the correct
+ * number of irq vectors to be requested. Separate the registration process
+ * into before / after interrupt vector request.
+ */
+ cpmu_count = cxl_count_regblock(pdev, CXL_REGLOC_RBI_CPMU);
+ if (cpmu_count) {
+ cpmu_regs_array = kmalloc_array(cpmu_count, sizeof(cpmu_regs_array),
+ GFP_KERNEL);
+ if (!cpmu_regs_array)
+ return -ENOMEM;
+ }
+ /* Pass one - just enough to find out what interrupts are used */
+ for (i = 0; i < cpmu_count; i++) {
+ int irq;
+
+ rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_CPMU, &map, i);
+ if (rc) {
+ kfree(cpmu_regs_array);
+ return rc;
+ }
+
+ rc = cxl_map_cpmu_regs(pdev, &cpmu_regs_array[i], &map);
+ if (rc) {
+ kfree(cpmu_regs_array);
+ return rc;
+ }
+
+ irq = cxl_cpmu_get_irq(&cpmu_regs_array[i]);
+ max_interrupt = max(max_interrupt, irq);
+ }
+
+ if (max_interrupt >= 0) {
+ pci_set_master(pdev);
+ rc = cxl_alloc_irq_vectors(cxlds, max_interrupt + 1);
+ if (rc) {
+ kfree(cpmu_regs_array);
+ return rc;
+ }
+ }
+
+ /* Pass 2 - register the CPMU instances */
+ for (i = 0; i < cpmu_count; i++)
+ devm_cxl_cpmu_add(cxlds->dev, &cpmu_regs_array[i], i);
+ kfree(cpmu_regs_array);
+
cxlmd = devm_cxl_add_memdev(cxlds);
if (IS_ERR(cxlmd))
return PTR_ERR(cxlmd);
--
2.32.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [RFC PATCH v2 3/4] cxl: CXL Performance Monitoring Unit driver
2022-08-24 10:36 [RFC PATCH v2 0/4] CXL 3.0 Performance Monitoring Unit support Jonathan Cameron
2022-08-24 10:36 ` [RFC PATCH v2 1/4] cxl: Add function to count regblocks of a given type Jonathan Cameron
2022-08-24 10:36 ` [RFC PATCH v2 2/4] cxl/pci: Find and register CXL PMU devices Jonathan Cameron
@ 2022-08-24 10:36 ` Jonathan Cameron
2022-09-22 20:19 ` Dave Jiang
2022-08-24 10:36 ` [RFC PATCH v2 4/4] docs: perf: Minimal introduction the the CXL PMU device and driver Jonathan Cameron
3 siblings, 1 reply; 12+ messages in thread
From: Jonathan Cameron @ 2022-08-24 10:36 UTC (permalink / raw)
To: linux-cxl, Dan Williams, Alison Schofield, Vishal Verma,
Ira Weiny, Ben Widawsky, linux-perf-users, Will Deacon,
Mark Rutland
Cc: linuxarm
CXL rev 3.0 introduces a standard performance monitoring hardware
block to CXL. Instances are discovered using CXL Register Locator DVSEC
entries. Each CXL component may have multiple PMUs.
This initial driver supports on a subset of types of counter.
It support counters that are either fixed or configurable, but requires
that they support the ability to freeze and write value whilst frozen.
Development done with QEMU model which will be posted shortly.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
--
RFC questions:
- Creation of the devices. Currently hung off the cxl_pci driver.
May want to rethink to avoid needing to replicate registration code
for other CXL components.
- Needs more testing, but wanted to share early in case major refactoring
needed.
- Where to put the driver. Previous discussions on similar drivers
led to them being under drivers/perf (hisi_pcie_pmu)
---
drivers/cxl/Kconfig | 12 +
drivers/cxl/Makefile | 1 +
drivers/cxl/cpmu.c | 945 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 958 insertions(+)
diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
index 768ced3d6fe8..d9e6775c05a5 100644
--- a/drivers/cxl/Kconfig
+++ b/drivers/cxl/Kconfig
@@ -111,4 +111,16 @@ config CXL_REGION
select MEMREGION
select GET_FREE_REGION
+config CXL_CPMU
+ tristate "CXL Performance Monitoring Unit"
+ default CXL_BUS
+ help
+ Support performance monitoring as defined in CXL rev 3.0
+ section 13.2: Performance Monitoring. CXL components may have
+ one or more CXL Performance Monitoring Units (CPMUs).
+
+ Say 'y/m' to enable a driver that will attach to performance
+ monitoring units and provide standard perf based interfaces.
+
+ If unsure say 'm'.
endif
diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile
index a78270794150..f55c2751ac10 100644
--- a/drivers/cxl/Makefile
+++ b/drivers/cxl/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_CXL_MEM) += cxl_mem.o
obj-$(CONFIG_CXL_ACPI) += cxl_acpi.o
obj-$(CONFIG_CXL_PMEM) += cxl_pmem.o
obj-$(CONFIG_CXL_PORT) += cxl_port.o
+obj-$(CONFIG_CXL_CPMU) += cpmu.o
cxl_mem-y := mem.o
cxl_pci-y := pci.o
diff --git a/drivers/cxl/cpmu.c b/drivers/cxl/cpmu.c
new file mode 100644
index 000000000000..6549a553641b
--- /dev/null
+++ b/drivers/cxl/cpmu.c
@@ -0,0 +1,945 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/*
+ * Copyright(c) 2022 Huawei
+ *
+ * The CXL 3.0 specification includes a standard performance monitoring unit,
+ * called the CLX PMU, or CPMU. In order to allow a high degree of
+ * implementation flexibility the specification provides a wide range of
+ * options all of which are self describing.
+ *
+ * Details in CXL rev 3.0 section 8.2.7 CPMU Register Interface
+ *
+ * TODO:
+ * o May be useful to name some summed event groups. Figure out which.
+ * CPMU event selection is based on summing of bitmaps of events within
+ * a given event group. With a limited supply of configurable counters, this
+ * provides flexibility between very specific events such as d2h_req_rdcurr
+ * (one type of read request) or combining events counted by the hardware
+ * counter to allow d2h_req_rd to be counted as sum of fine grained events
+ * d2h_req_rd = d2h_req_rdcurr + d2h_req_rdown + d2h_req_rdshared +
+ * d2h_req_rdany + d2h_req_rdownnodata
+ * Thus d2h_req_rd requires one configurable counter instead of 5 if the
+ * counters were summed in userspace.
+ * Current interface allows userspace to specify the bitmap directly, but
+ * it may make sense to provide explicit attributes for commonly used
+ * combinations.
+ * o Support free running counters - copy the intel uncore PMU handling for these.
+ * o CPMUs which do not support freeze.
+ * o Add filter validation in cpmu_event_init() so problems are detected earlier.
+ * o Reject configurations that the hardware is ignoring
+ * (e.g. invert when not invertable)
+ * o Support CPMUs with no interrupts using an HRTIMER.
+ */
+
+#include <linux/bitops.h>
+#include <linux/bits.h>
+#include <linux/bug.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/pci.h>
+#include <linux/perf_event.h>
+#include "cpmu.h"
+#include "cxl.h"
+
+/* CXL rev 3.0 Table 13-5 Events under CXL Vendor ID */
+#define CPMU_GID_CLOCK_TICKS 0x00
+#define CPMU_GID_D2H_REQ 0x0010
+#define CPMU_GID_D2H_RSP 0x0011
+#define CPMU_GID_H2D_REQ 0x0012
+#define CPMU_GID_H2D_RSP 0x0013
+#define CPMU_GID_CACHE_DATA 0x0014
+#define CPMU_GID_M2S_REQ 0x0020
+#define CPMU_GID_M2S_RWD 0x0021
+#define CPMU_GID_M2S_BIRSP 0x0022
+#define CPMU_GID_S2M_BISNP 0x0023
+#define CPMU_GID_S2M_NDR 0x0024
+#define CPMU_GID_S2M_DRS 0x0025
+#define CPMU_GID_DDR 0x8000
+
+static int cpmu_cpuhp_state_num;
+
+struct cpmu_event {
+ u16 vid;
+ u16 gid;
+ u32 msk;
+ bool configurable;
+ union {
+ int counter_idx; /* fixed counters */
+ int event_idx; /* configurable counters */
+ };
+ struct list_head node;
+};
+
+#define CPMU_MAX_COUNTERS 32
+struct cpmu_info {
+ struct pmu pmu;
+ void __iomem *base;
+ struct perf_event **hw_events;
+ struct list_head cpmu_events;
+ DECLARE_BITMAP(conf_counter_bm, CPMU_MAX_COUNTERS);
+ u16 counter_width;
+ u8 num_counters;
+ u8 num_event_capabilities;
+ int on_cpu;
+ struct hlist_node node;
+ bool freeze_for_enable;
+ bool filter_hdm;
+ int irq;
+};
+
+#define pmu_to_cpmu_info(_pmu) container_of(_pmu, struct cpmu_info, pmu)
+
+/*
+ * All CPMU counters are discoverable via the Event Capabilities Registers.
+ * Each Event Capability register contains a a VID / GroupID.
+ * A counter may then count any combination (by summing) of events in
+ * that group which are in the Supported Events Bitmask.
+ * However, there are some complexities to the scheme.
+ * - Fixed function counters refer to an Event Capabilities register.
+ * That event capability register is not then used for Configurable
+ * counters.
+ * TODO: Support summed events.
+ */
+static int cpmu_parse_caps(struct device *dev, struct cpmu_info *info)
+{
+ DECLARE_BITMAP(fixed_counter_event_cap_bm, 32) = {0};
+ void __iomem *base = info->base;
+ u64 val, eval;
+ int i;
+
+ val = readq(base + CPMU_CAP_REG);
+ info->freeze_for_enable = FIELD_GET(CPMU_CAP_WRITEABLE_WHEN_FROZEN, val) &
+ FIELD_GET(CPMU_CAP_FREEZE, val);
+ if (!info->freeze_for_enable) {
+ dev_err(dev, "Driver does not support CPMUs that do not support freeze for enable\n");
+ return -ENODEV;
+ }
+
+ info->num_counters = FIELD_GET(CPMU_CAP_NUM_COUNTERS_MSK, val) + 1;
+ info->counter_width = FIELD_GET(CPMU_CAP_COUNTER_WIDTH_MSK, val);
+ info->num_event_capabilities = FIELD_GET(CPMU_CAP_NUM_EVN_CAP_REG_SUP_MSK, val) + 1;
+
+ info->filter_hdm = FIELD_GET(CPMU_CAP_FILTERS_SUP_MSK, val);
+ if (FIELD_GET(CPMU_CAP_INT, val))
+ info->irq = FIELD_GET(CPMU_CAP_MSI_N_MSK, val);
+ else
+ info->irq = -1;
+
+ /* First handle fixed function counters; note if configurable counters found */
+ for (i = 0; i < info->num_counters; i++) {
+ struct cpmu_event *cpmu_ev;
+ u32 events_msk;
+ u8 group_idx;
+
+ val = readq(base + CPMU_COUNTER_CFG_REG(i));
+
+ if (FIELD_GET(CPMU_COUNTER_CFG_TYPE_MSK, val) ==
+ CPMU_COUNTER_CFG_TYPE_CONFIGURABLE) {
+ set_bit(i, info->conf_counter_bm);
+ }
+
+ if (FIELD_GET(CPMU_COUNTER_CFG_TYPE_MSK, val) !=
+ CPMU_COUNTER_CFG_TYPE_FIXED_FUN)
+ continue;
+
+ /* In this case we know which fields are const */
+ group_idx = FIELD_GET(CPMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK, val);
+ events_msk = FIELD_GET(CPMU_COUNTER_CFG_EVENTS_MSK, val);
+ eval = readq(base + CPMU_EVENT_CAP_REG(group_idx));
+ cpmu_ev = devm_kzalloc(dev, sizeof(*cpmu_ev), GFP_KERNEL);
+ if (!cpmu_ev)
+ return -ENOMEM;
+
+ cpmu_ev->vid = FIELD_GET(CPMU_EVENT_CAP_VENDOR_ID_MSK, eval);
+ cpmu_ev->gid = FIELD_GET(CPMU_EVENT_CAP_GROUP_ID_MSK, eval);
+ /* For a fixed purpose counter use the events mask from the counter CFG */
+ cpmu_ev->msk = events_msk;
+ cpmu_ev->configurable = false;
+ cpmu_ev->counter_idx = i;
+ /* This list add is never unwound as all entries deleted on remove */
+ list_add(&cpmu_ev->node, &info->cpmu_events);
+ /*
+ * Configurable counters must not use an Event Capability registers that
+ * is in use for a Fixed counter
+ */
+ set_bit(group_idx, fixed_counter_event_cap_bm);
+ }
+
+ if (!bitmap_empty(info->conf_counter_bm, CPMU_MAX_COUNTERS)) {
+ struct cpmu_event *cpmu_ev;
+ int j;
+ /* Walk event capabilities unused by fixed counters */
+ for_each_clear_bit(j, fixed_counter_event_cap_bm,
+ info->num_event_capabilities) {
+ cpmu_ev = devm_kzalloc(dev, sizeof(*cpmu_ev), GFP_KERNEL);
+ if (!cpmu_ev)
+ return -ENOMEM;
+
+ eval = readq(base + CPMU_EVENT_CAP_REG(j));
+ cpmu_ev->vid = FIELD_GET(CPMU_EVENT_CAP_VENDOR_ID_MSK, eval);
+ cpmu_ev->gid = FIELD_GET(CPMU_EVENT_CAP_GROUP_ID_MSK, eval);
+ cpmu_ev->msk = FIELD_GET(CPMU_EVENT_CAP_SUPPORTED_EVENTS_MSK, eval);
+ cpmu_ev->event_idx = j;
+ cpmu_ev->configurable = true;
+ list_add(&cpmu_ev->node, &info->cpmu_events);
+ }
+ }
+
+ return 0;
+}
+
+static ssize_t cpmu_event_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct perf_pmu_events_attr *pmu_attr =
+ container_of(attr, struct perf_pmu_events_attr, attr);
+
+ return sysfs_emit(buf, "config=%#llx\n", pmu_attr->id);
+}
+
+#define CPMU_PMU_EVENT_ATTR(_name, _vid, _gid, _msk) \
+ PMU_EVENT_ATTR_ID(_name, cpmu_event_sysfs_show, \
+ ((u64)(_vid) << 48) | ((u64)(_gid) << 32) | (u64)(_msk))
+
+static struct attribute *cpmu_event_attrs[] = {
+ CPMU_PMU_EVENT_ATTR(clock_ticks, 0x1e98, CPMU_GID_CLOCK_TICKS, BIT(0)),
+ /* CXL rev 3.0 Table 3-17 - Device to Host Requests */
+ CPMU_PMU_EVENT_ATTR(d2h_req_rdcurr, 0x1e98, CPMU_GID_D2H_REQ, BIT(1)),
+ CPMU_PMU_EVENT_ATTR(d2h_req_rdown, 0x1e98, CPMU_GID_D2H_REQ, BIT(2)),
+ CPMU_PMU_EVENT_ATTR(d2h_req_rdshared, 0x1e98, CPMU_GID_D2H_REQ, BIT(3)),
+ CPMU_PMU_EVENT_ATTR(d2h_req_rdany, 0x1e98, CPMU_GID_D2H_REQ, BIT(4)),
+ CPMU_PMU_EVENT_ATTR(d2h_req_rdownnodata, 0x1e98, CPMU_GID_D2H_REQ, BIT(5)),
+ CPMU_PMU_EVENT_ATTR(d2h_req_itomwr, 0x1e98, CPMU_GID_D2H_REQ, BIT(6)),
+ CPMU_PMU_EVENT_ATTR(d2h_req_wrcurr, 0x1e98, CPMU_GID_D2H_REQ, BIT(7)),
+ CPMU_PMU_EVENT_ATTR(d2h_req_clflush, 0x1e98, CPMU_GID_D2H_REQ, BIT(8)),
+ CPMU_PMU_EVENT_ATTR(d2h_req_cleanevict, 0x1e98, CPMU_GID_D2H_REQ, BIT(9)),
+ CPMU_PMU_EVENT_ATTR(d2h_req_dirtyevict, 0x1e98, CPMU_GID_D2H_REQ, BIT(10)),
+ CPMU_PMU_EVENT_ATTR(d2h_req_cleanevictnodata, 0x1e98, CPMU_GID_D2H_REQ, BIT(11)),
+ CPMU_PMU_EVENT_ATTR(d2h_req_wowrinv, 0x1e98, CPMU_GID_D2H_REQ, BIT(12)),
+ CPMU_PMU_EVENT_ATTR(d2h_req_wowrinvf, 0x1e98, CPMU_GID_D2H_REQ, BIT(13)),
+ CPMU_PMU_EVENT_ATTR(d2h_req_wrinv, 0x1e98, CPMU_GID_D2H_REQ, BIT(14)),
+ CPMU_PMU_EVENT_ATTR(d2h_req_cacheflushed, 0x1e98, CPMU_GID_D2H_REQ, BIT(16)),
+ /* CXL rev 3.0 Table 3-20 - D2H Repsonse Encodings */
+ CPMU_PMU_EVENT_ATTR(d2h_rsp_rspihiti, 0x1e98, CPMU_GID_D2H_RSP, BIT(4)),
+ CPMU_PMU_EVENT_ATTR(d2h_rsp_rspvhitv, 0x1e98, CPMU_GID_D2H_RSP, BIT(6)),
+ CPMU_PMU_EVENT_ATTR(d2h_rsp_rspihitse, 0x1e98, CPMU_GID_D2H_RSP, BIT(5)),
+ CPMU_PMU_EVENT_ATTR(d2h_rsp_rspshitse, 0x1e98, CPMU_GID_D2H_RSP, BIT(1)),
+ CPMU_PMU_EVENT_ATTR(d2h_rsp_rspsfwdm, 0x1e98, CPMU_GID_D2H_RSP, BIT(7)),
+ CPMU_PMU_EVENT_ATTR(d2h_rsp_rspifwdm, 0x1e98, CPMU_GID_D2H_RSP, BIT(15)),
+ CPMU_PMU_EVENT_ATTR(d2h_rsp_rspvfwdv, 0x1e98, CPMU_GID_D2H_RSP, BIT(22)),
+ /* CXL rev 3.0 Table 3-21 - CXL.cache - Mapping of H2D Requests to D2H Responses */
+ CPMU_PMU_EVENT_ATTR(h2d_req_snpdata, 0x1e98, CPMU_GID_H2D_REQ, BIT(1)),
+ CPMU_PMU_EVENT_ATTR(h2d_req_snpinv, 0x1e98, CPMU_GID_H2D_REQ, BIT(2)),
+ CPMU_PMU_EVENT_ATTR(h2d_req_snpcur, 0x1e98, CPMU_GID_H2D_REQ, BIT(3)),
+ /* CXL rev 3.0 Table 3-22 - H2D Response Opcode Encodings */
+ CPMU_PMU_EVENT_ATTR(h2d_rsp_writepull, 0x1e98, CPMU_GID_H2D_RSP, BIT(1)),
+ CPMU_PMU_EVENT_ATTR(h2d_rsp_go, 0x1e98, CPMU_GID_H2D_RSP, BIT(4)),
+ CPMU_PMU_EVENT_ATTR(h2d_rsp_gowritepull, 0x1e98, CPMU_GID_H2D_RSP, BIT(5)),
+ CPMU_PMU_EVENT_ATTR(h2d_rsp_extcmp, 0x1e98, CPMU_GID_H2D_RSP, BIT(6)),
+ CPMU_PMU_EVENT_ATTR(h2d_rsp_gowritepulldrop, 0x1e98, CPMU_GID_H2D_RSP, BIT(8)),
+ CPMU_PMU_EVENT_ATTR(h2d_rsp_fastgowritepull, 0x1e98, CPMU_GID_H2D_RSP, BIT(13)),
+ CPMU_PMU_EVENT_ATTR(h2d_rsp_goerrwritepull, 0x1e98, CPMU_GID_H2D_RSP, BIT(15)),
+ /* CXL rev 3.0 Table 13-5 directly lists these */
+ CPMU_PMU_EVENT_ATTR(cachedata_d2h_data, 0x1e98, CPMU_GID_CACHE_DATA, BIT(0)),
+ CPMU_PMU_EVENT_ATTR(cachedata_h2d_data, 0x1e98, CPMU_GID_CACHE_DATA, BIT(1)),
+ /* CXL rev 3.0 Table 3-29 M2S Req Memory Opcodes */
+ CPMU_PMU_EVENT_ATTR(m2s_req_meminv, 0x1e98, CPMU_GID_M2S_REQ, BIT(0)),
+ CPMU_PMU_EVENT_ATTR(m2s_req_memrd, 0x1e98, CPMU_GID_M2S_REQ, BIT(1)),
+ CPMU_PMU_EVENT_ATTR(m2s_req_memrddata, 0x1e98, CPMU_GID_M2S_REQ, BIT(2)),
+ CPMU_PMU_EVENT_ATTR(m2s_req_memrdfwd, 0x1e98, CPMU_GID_M2S_REQ, BIT(3)),
+ CPMU_PMU_EVENT_ATTR(m2s_req_memwrfwd, 0x1e98, CPMU_GID_M2S_REQ, BIT(4)),
+ CPMU_PMU_EVENT_ATTR(m2s_req_memspecrd, 0x1e98, CPMU_GID_M2S_REQ, BIT(8)),
+ CPMU_PMU_EVENT_ATTR(m2s_req_meminvnt, 0x1e98, CPMU_GID_M2S_REQ, BIT(9)),
+ CPMU_PMU_EVENT_ATTR(m2s_req_memcleanevict, 0x1e98, CPMU_GID_M2S_REQ, BIT(10)),
+ /* CXL rev 3.0 Table 3-35 M2S RwD Memory Opcodes */
+ CPMU_PMU_EVENT_ATTR(m2s_rwd_memwr, 0x1e98, CPMU_GID_M2S_RWD, BIT(1)),
+ CPMU_PMU_EVENT_ATTR(m2s_rwd_memwrptl, 0x1e98, CPMU_GID_M2S_RWD, BIT(2)),
+ CPMU_PMU_EVENT_ATTR(m2s_rwd_biconflict, 0x1e98, CPMU_GID_M2S_RWD, BIT(4)),
+ /* CXL rev 3.0 Table 3-38 M2S BIRsp Memory Opcodes */
+ CPMU_PMU_EVENT_ATTR(m2s_birsp_i, 0x1e98, CPMU_GID_M2S_BIRSP, BIT(0)),
+ CPMU_PMU_EVENT_ATTR(m2s_birsp_s, 0x1e98, CPMU_GID_M2S_BIRSP, BIT(1)),
+ CPMU_PMU_EVENT_ATTR(m2s_birsp_e, 0x1e98, CPMU_GID_M2S_BIRSP, BIT(2)),
+ CPMU_PMU_EVENT_ATTR(m2s_birsp_iblk, 0x1e98, CPMU_GID_M2S_BIRSP, BIT(4)),
+ CPMU_PMU_EVENT_ATTR(m2s_birsp_sblk, 0x1e98, CPMU_GID_M2S_BIRSP, BIT(5)),
+ CPMU_PMU_EVENT_ATTR(m2s_birsp_eblk, 0x1e98, CPMU_GID_M2S_BIRSP, BIT(6)),
+ /* CXL rev 3.0 Table 3-40 S2M BISnp Opcodes */
+ CPMU_PMU_EVENT_ATTR(s2m_bisnp_cur, 0x1e98, CPMU_GID_S2M_BISNP, BIT(0)),
+ CPMU_PMU_EVENT_ATTR(s2m_bisnp_data, 0x1e98, CPMU_GID_S2M_BISNP, BIT(1)),
+ CPMU_PMU_EVENT_ATTR(s2m_bisnp_inv, 0x1e98, CPMU_GID_S2M_BISNP, BIT(2)),
+ CPMU_PMU_EVENT_ATTR(s2m_bisnp_curblk, 0x1e98, CPMU_GID_S2M_BISNP, BIT(4)),
+ CPMU_PMU_EVENT_ATTR(s2m_bisnp_datblk, 0x1e98, CPMU_GID_S2M_BISNP, BIT(5)),
+ CPMU_PMU_EVENT_ATTR(s2m_bisnp_invblk, 0x1e98, CPMU_GID_S2M_BISNP, BIT(6)),
+ /* CXL rev 3.0 Table 3-43 S2M NDR Opcopdes */
+ CPMU_PMU_EVENT_ATTR(s2m_ndr_cmp, 0x1e98, CPMU_GID_S2M_NDR, BIT(0)),
+ CPMU_PMU_EVENT_ATTR(s2m_ndr_cmps, 0x1e98, CPMU_GID_S2M_NDR, BIT(1)),
+ CPMU_PMU_EVENT_ATTR(s2m_ndr_cmpe, 0x1e98, CPMU_GID_S2M_NDR, BIT(2)),
+ CPMU_PMU_EVENT_ATTR(s2m_ndr_biconflictack, 0x1e98, CPMU_GID_S2M_NDR, BIT(3)),
+ /* CXL rev 3.0 Table 3-46 S2M DRS opcodes */
+ CPMU_PMU_EVENT_ATTR(s2m_drs_memdata, 0x1e98, CPMU_GID_S2M_DRS, BIT(0)),
+ CPMU_PMU_EVENT_ATTR(s2m_drs_memdatanxm, 0x1e98, CPMU_GID_S2M_DRS, BIT(1)),
+ /* CXL rev 3.0 Table 13-5 directly lists these */
+ CPMU_PMU_EVENT_ATTR(ddr_act, 0x1e98, CPMU_GID_DDR, BIT(0)),
+ CPMU_PMU_EVENT_ATTR(ddr_pre, 0x1e98, CPMU_GID_DDR, BIT(1)),
+ CPMU_PMU_EVENT_ATTR(ddr_casrd, 0x1e98, CPMU_GID_DDR, BIT(2)),
+ CPMU_PMU_EVENT_ATTR(ddr_caswr, 0x1e98, CPMU_GID_DDR, BIT(3)),
+ CPMU_PMU_EVENT_ATTR(ddr_refresh, 0x1e98, CPMU_GID_DDR, BIT(4)),
+ CPMU_PMU_EVENT_ATTR(ddr_selfrefreshent, 0x1e98, CPMU_GID_DDR, BIT(5)),
+ CPMU_PMU_EVENT_ATTR(ddr_rfm, 0x1e98, CPMU_GID_DDR, BIT(6)),
+ NULL
+};
+
+static umode_t cpmu_event_is_visible(struct kobject *kobj, struct attribute *attr, int a)
+{
+ struct device_attribute *dev_attr = container_of(attr, struct device_attribute, attr);
+ struct perf_pmu_events_attr *pmu_attr =
+ container_of(dev_attr, struct perf_pmu_events_attr, attr);
+ struct device *dev = kobj_to_dev(kobj);
+ struct cpmu_info *info = dev_get_drvdata(dev);
+ struct cpmu_event *cpmu_ev;
+ int match_vid = FIELD_GET(GENMASK(63, 48), pmu_attr->id);
+ int match_gid = FIELD_GET(GENMASK(47, 32), pmu_attr->id);
+ int match_msk = FIELD_GET(GENMASK(31, 0), pmu_attr->id);
+
+ list_for_each_entry(cpmu_ev, &info->cpmu_events, node) {
+ if (match_vid != cpmu_ev->vid || match_gid != cpmu_ev->gid)
+ continue;
+
+ if (!cpmu_ev->configurable) {
+ /* Precise match for fixed counter */
+ if (match_msk == cpmu_ev->msk)
+ return attr->mode;
+ } else {
+ /* Request mask must be subset of supported */
+ if (!(match_msk & ~cpmu_ev->msk))
+ return attr->mode;
+ }
+ }
+
+ return 0;
+}
+
+static const struct attribute_group cpmu_events = {
+ .name = "events",
+ .attrs = cpmu_event_attrs,
+ .is_visible = cpmu_event_is_visible,
+};
+
+static ssize_t cpmu_format_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct dev_ext_attribute *eattr;
+
+ eattr = container_of(attr, struct dev_ext_attribute, attr);
+
+ return sysfs_emit(buf, "%s\n", (char *)eattr->var);
+}
+
+#define CPMU_FORMAT_ATTR(_name, _format)\
+ (&((struct dev_ext_attribute[]) { \
+ { \
+ .attr = __ATTR(_name, 0444, \
+ cpmu_format_sysfs_show, NULL), \
+ .var = (void *)_format \
+ } \
+ })[0].attr.attr)
+
+enum {
+ cpmu_mask_attr,
+ cpmu_gid_attr,
+ cpmu_vid_attr,
+ cpmu_threshold_attr,
+ cpmu_invert_attr,
+ cpmu_edge_attr,
+ cpmu_hdm_filter_en_attr,
+ cpmu_hdm_attr,
+};
+
+static struct attribute *cpmu_format_attr[] = {
+ [cpmu_mask_attr] = CPMU_FORMAT_ATTR(mask, "config:0-31"),
+ [cpmu_gid_attr] = CPMU_FORMAT_ATTR(gid, "config:32-47"),
+ [cpmu_vid_attr] = CPMU_FORMAT_ATTR(vid, "config:48-63"),
+ [cpmu_threshold_attr] = CPMU_FORMAT_ATTR(threshold, "config1:0-15"),
+ [cpmu_invert_attr] = CPMU_FORMAT_ATTR(invert, "config1:16"),
+ [cpmu_edge_attr] = CPMU_FORMAT_ATTR(edge, "config1:17"),
+ [cpmu_hdm_filter_en_attr] = CPMU_FORMAT_ATTR(hdm_filter_en, "config1:18"),
+ [cpmu_hdm_attr] = CPMU_FORMAT_ATTR(hdm, "config2:0-15"),
+ NULL
+};
+
+static umode_t cpmu_format_is_visible(struct kobject *kobj, struct attribute *attr, int a)
+{
+ struct device *dev = kobj_to_dev(kobj);
+ struct cpmu_info *info = dev_get_drvdata(dev);
+
+ /*
+ * Filter capability at the CPMU level, so hide the attributes if the particular
+ * filter is not supported.
+ */
+ if (attr == cpmu_format_attr[cpmu_hdm_filter_en_attr] ||
+ attr == cpmu_format_attr[cpmu_hdm_attr]) {
+ if (info->filter_hdm)
+ return 0444;
+ else
+ return 0;
+ } else {
+ return 0444;
+ }
+}
+
+static const struct attribute_group cpmu_format_group = {
+ .name = "format",
+ .attrs = cpmu_format_attr,
+ .is_visible = cpmu_format_is_visible,
+};
+
+static u32 cpmu_config_get_mask(struct perf_event *event)
+{
+ return FIELD_GET(GENMASK(31, 0), event->attr.config);
+}
+
+static u16 cpmu_config_get_gid(struct perf_event *event)
+{
+ return FIELD_GET(GENMASK(47, 32), event->attr.config);
+}
+
+static u16 cpmu_config_get_vid(struct perf_event *event)
+{
+ return FIELD_GET(GENMASK(63, 48), event->attr.config);
+}
+
+static u8 cpmu_config1_get_threshold(struct perf_event *event)
+{
+ return FIELD_GET(GENMASK(15, 0), event->attr.config1);
+}
+
+static bool cpmu_config1_get_invert(struct perf_event *event)
+{
+ return FIELD_GET(BIT(16), event->attr.config1);
+}
+
+static bool cpmu_config1_get_edge(struct perf_event *event)
+{
+ return FIELD_GET(BIT(17), event->attr.config1);
+}
+
+/*
+ * CPMU specification allows for 8 filters, each with a 16 bit value...
+ * So we need to find 8x16bits to store it in.
+ * So far only one filter has been defined - HDM Decoder.
+ * As the value used for disable is 0xffff, a separate enable switch
+ * is needed.
+ */
+
+static bool cpmu_config1_hdm_filter_en(struct perf_event *event)
+{
+ return FIELD_GET(BIT(14), event->attr.config1);
+}
+
+static u16 cpmu_config2_get_hdm_decoder(struct perf_event *event)
+{
+ return FIELD_GET(GENMASK(15, 0), event->attr.config2);
+}
+
+static ssize_t cpumask_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct cpmu_info *info = dev_get_drvdata(dev);
+
+ return cpumap_print_to_pagebuf(true, buf, cpumask_of(info->on_cpu));
+}
+static DEVICE_ATTR_RO(cpumask);
+
+static struct attribute *cpmu_cpumask_attrs[] = {
+ &dev_attr_cpumask.attr,
+ NULL
+};
+
+static const struct attribute_group cpmu_cpumask_group = {
+ .attrs = cpmu_cpumask_attrs,
+};
+
+static const struct attribute_group *cpmu_attr_groups[] = {
+ &cpmu_events,
+ &cpmu_format_group,
+ &cpmu_cpumask_group,
+ NULL
+};
+
+static int cpmu_event_init(struct perf_event *event)
+{
+ struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
+
+ event->cpu = info->on_cpu;
+ /* Top level type sanity check - is this a Hardware Event being requested */
+ if (event->attr.type != event->pmu->type)
+ return -ENOENT;
+
+ if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
+ return -EOPNOTSUPP;
+ /* TODO: Validation of any filter */
+
+ return 0;
+}
+
+static void cpmu_pmu_enable(struct pmu *pmu)
+{
+ struct cpmu_info *info = pmu_to_cpmu_info(pmu);
+ void __iomem *base = info->base;
+ int num;
+
+ /* We don't have a global enable, but we 'might' have a global freeze which we can use */
+ if (info->freeze_for_enable) {
+ /* Check if something is enabled */
+ for (num = 0; num < info->num_counters; num++) {
+ if (info->hw_events[num])
+ break;
+ }
+ if (num == info->num_counters)
+ return;
+
+ /* Can assume frozen at this stage */
+ writeq(0, base + CPMU_FREEZE_REG);
+
+ return;
+ }
+}
+
+static void cpmu_pmu_disable(struct pmu *pmu)
+{
+ struct cpmu_info *info = pmu_to_cpmu_info(pmu);
+ void __iomem *base = info->base;
+
+ if (info->freeze_for_enable) {
+ /*
+ * Whilst bits above number of counters are RsvdZ
+ * they are unlikely to be repurposed given
+ * number of counters is allowed be 64 leaving
+ * no reserved bits. Hence this is only slightly
+ * naughty.
+ */
+ writeq(GENMASK(63, 0), base + CPMU_FREEZE_REG);
+ return;
+ }
+}
+
+static int cpmu_find_matching_event_cap(struct cpmu_info *info,
+ struct perf_event *event)
+{
+ struct cpmu_event *cpmu_ev;
+ u16 gid = cpmu_config_get_gid(event);
+ u16 vid = cpmu_config_get_vid(event);
+ u32 mask = cpmu_config_get_mask(event);
+
+ list_for_each_entry(cpmu_ev, &info->cpmu_events, node) {
+ if (vid != cpmu_ev->vid || gid != cpmu_ev->gid)
+ continue;
+
+ if (~cpmu_ev->msk & mask)
+ break;
+ return cpmu_ev->event_idx;
+ }
+
+ return -EINVAL;
+}
+
+static void cpmu_event_start(struct perf_event *event, int flags)
+{
+ struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+ void __iomem *base = info->base;
+ u64 cfg;
+ u64 prev_cnt;
+
+ if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
+ return;
+
+ WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
+ hwc->state = 0;
+
+ /*
+ * Currently only hdm filter is defined, this code will
+ * want generalizing when more are defined.
+ */
+ if (info->filter_hdm) {
+ if (cpmu_config1_hdm_filter_en(event))
+ cfg = cpmu_config2_get_hdm_decoder(event);
+
+ else
+ cfg = GENMASK(15, 0);
+ writeq(cfg, base + CPMU_FILTER_CFG_REG(hwc->idx, 0));
+ }
+
+ cfg = readq(base + CPMU_COUNTER_CFG_REG(hwc->idx));
+ cfg |= FIELD_PREP(CPMU_COUNTER_CFG_INT_ON_OVRFLW, 1);
+ cfg |= FIELD_PREP(CPMU_COUNTER_CFG_ENABLE, 1);
+ cfg |= FIELD_PREP(CPMU_COUNTER_CFG_EDGE, cpmu_config1_get_edge(event) ? 1 : 0);
+ cfg |= FIELD_PREP(CPMU_COUNTER_CFG_INVERT, cpmu_config1_get_invert(event) ? 1 : 0);
+
+ /* Fixed purpose counters have next two fields RO */
+ if (test_bit(hwc->idx, info->conf_counter_bm)) {
+ int event_idx = cpmu_find_matching_event_cap(info, event);
+
+ if (event_idx < 0) {
+ dev_dbg(info->pmu.dev, "Could not find matching event capability\n");
+ return;
+ }
+ cfg |= FIELD_PREP(CPMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK, event_idx);
+ cfg |= FIELD_PREP(CPMU_COUNTER_CFG_EVENTS_MSK, cpmu_config_get_mask(event));
+ }
+ cfg &= ~CPMU_COUNTER_CFG_THRESHOLD_MSK;
+ /*
+ * For events that generate only 1 count per clock the CXL 3.0 spec
+ * states the threshold shall be set to 1 but if set to 0 it will
+ * count the raw value anwyay?
+ * There is definition ofwhat events will count multiple per cycle
+ * and hence to which non 1 values of threshold can apply.
+ * (CXL 3.0 8.2.7.2.1 Counter Configuration - threshold field definition)
+ */
+ cfg |= FIELD_PREP(CPMU_COUNTER_CFG_THRESHOLD_MSK,
+ cpmu_config1_get_threshold(event));
+ writeq(cfg, base + CPMU_COUNTER_CFG_REG(hwc->idx));
+
+ local64_set(&hwc->prev_count, 0);
+ writeq(0, base + CPMU_COUNTER_REG(hwc->idx));
+
+ if (flags & PERF_EF_RELOAD) {
+ prev_cnt = local64_read(&hwc->prev_count);
+ writeq(prev_cnt, base + CPMU_COUNTER_REG(hwc->idx));
+ }
+
+ perf_event_update_userpage(event);
+}
+
+static u64 cpmu_read_counter(struct perf_event *event)
+{
+ struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
+ void __iomem *base = info->base;
+
+ return readq(base + CPMU_COUNTER_REG(event->hw.idx));
+}
+
+static void __cpmu_read(struct perf_event *event, bool overflow)
+{
+ struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+ u64 new_cnt, prev_cnt, delta;
+
+ do {
+ prev_cnt = local64_read(&hwc->prev_count);
+ new_cnt = cpmu_read_counter(event);
+ } while (local64_cmpxchg(&hwc->prev_count, prev_cnt, new_cnt) != prev_cnt);
+
+ /*
+ * If we know an overflow occur then take that into account.
+ * Note counter is not reset as that would lose events
+ */
+ delta = (new_cnt - prev_cnt) & GENMASK(info->counter_width - 1, 0);
+ if (overflow && delta < GENMASK(info->counter_width - 1, 0))
+ delta += (1UL << info->counter_width);
+
+ local64_add(delta, &event->count);
+}
+
+static void cpmu_read(struct perf_event *event)
+{
+ __cpmu_read(event, false);
+}
+
+static void cpmu_event_stop(struct perf_event *event, int flags)
+{
+ struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
+ void __iomem *base = info->base;
+ struct hw_perf_event *hwc = &event->hw;
+ u64 cfg;
+
+ cpmu_read(event);
+ WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
+ hwc->state |= PERF_HES_STOPPED;
+
+ cfg = readq(base + CPMU_COUNTER_CFG_REG(hwc->idx));
+ cfg &= ~(FIELD_PREP(CPMU_COUNTER_CFG_INT_ON_OVRFLW, 1) |
+ FIELD_PREP(CPMU_COUNTER_CFG_ENABLE, 1));
+ writeq(cfg, base + CPMU_COUNTER_CFG_REG(hwc->idx));
+
+ if (hwc->state & PERF_HES_UPTODATE)
+ return;
+
+ hwc->state |= PERF_HES_UPTODATE;
+}
+
+static int cpmu_get_event_idx(struct perf_event *event)
+{
+ struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
+ struct cpmu_event *cpmu_ev;
+ u32 mask;
+ u16 gid, vid;
+
+ vid = cpmu_config_get_vid(event);
+ gid = cpmu_config_get_gid(event);
+ mask = cpmu_config_get_mask(event);
+
+ list_for_each_entry(cpmu_ev, &info->cpmu_events, node) {
+ int idx;
+
+ if (vid != cpmu_ev->vid || gid != cpmu_ev->gid)
+ continue;
+
+ /*
+ * For fixed counters, must match exactly.
+ * No need to support duplicates so if first in use
+ * return an error.
+ */
+ if (!cpmu_ev->configurable) {
+ if (cpmu_ev->msk != mask)
+ continue;
+ if (info->hw_events[cpmu_ev->counter_idx])
+ return -EINVAL;
+
+ return cpmu_ev->counter_idx;
+ }
+
+ /* Requested mask needs to be subset of available */
+ if (~cpmu_ev->msk & mask)
+ continue;
+
+ /* Found the group, now see if any configurable counters left */
+ for_each_set_bit(idx, info->conf_counter_bm, 64) {
+ if (!info->hw_events[idx])
+ return idx;
+ }
+ }
+
+ return -EINVAL;
+}
+
+/*
+ * Reset ensures no possibility of any information leaking to wrong
+ * counter. Note that all fields written during start()
+ */
+static void cpmu_reset_counter(struct cpmu_info *info, int idx)
+{
+ void __iomem *base = info->base;
+
+ /* Much of this register is read only */
+ writeq(0, base + CPMU_EVENT_CAP_REG(idx));
+ /* Filters are not per counter, so not reset here */
+ writeq(0, base + CPMU_COUNTER_REG(idx));
+}
+
+static int cpmu_event_add(struct perf_event *event, int flags)
+{
+ struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+ int idx;
+
+ hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
+
+ idx = cpmu_get_event_idx(event);
+ if (idx < 0)
+ return idx;
+
+ hwc->idx = idx;
+ info->hw_events[idx] = event;
+
+ cpmu_reset_counter(info, idx);
+
+ if (flags & PERF_EF_START)
+ cpmu_event_start(event, PERF_EF_RELOAD);
+
+ return 0;
+}
+
+static void cpmu_event_del(struct perf_event *event, int flags)
+{
+ struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+
+ cpmu_event_stop(event, PERF_EF_UPDATE);
+ info->hw_events[hwc->idx] = NULL;
+ perf_event_update_userpage(event);
+}
+
+static irqreturn_t cpmu_irq(int irq, void *data)
+{
+ struct cpmu_info *info = data;
+ void __iomem *base = info->base;
+ u64 overflowed;
+ DECLARE_BITMAP(overflowedbm, 64);
+ int i;
+
+ overflowed = readq(base + CPMU_OVERFLOW_REG);
+
+ /* Interrupt may be shared, so maybe it isn't ours */
+ if (!overflowed)
+ return IRQ_NONE;
+
+ bitmap_from_arr64(overflowedbm, &overflowed, 64);
+ for_each_set_bit(i, overflowedbm, info->num_counters) {
+ struct perf_event *event = info->hw_events[i];
+
+ if (!event) {
+ dev_dbg(info->pmu.dev,
+ "overflow but on non enabled counter %d\n", i);
+ continue;
+ }
+
+ __cpmu_read(event, true);
+ }
+
+ writeq(overflowed, base + CPMU_OVERFLOW_REG);
+
+ return IRQ_HANDLED;
+}
+
+static int cxl_cpmu_probe(struct device *dev)
+{
+ struct cxl_cpmu *cpmu = to_cxl_cpmu(dev);
+ struct pci_dev *pdev = to_pci_dev(dev->parent);
+ struct cpmu_info *info;
+ char *irq_name;
+ int rc, irq;
+
+ info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
+ if (!info)
+ return -ENOMEM;
+
+ INIT_LIST_HEAD(&info->cpmu_events);
+
+ info->base = cpmu->base;
+
+ info->on_cpu = -1;
+ rc = cpmu_parse_caps(dev, info);
+ if (rc)
+ return rc;
+
+ info->hw_events = devm_kcalloc(dev, sizeof(*info->hw_events),
+ info->num_counters, GFP_KERNEL);
+ if (!info->hw_events)
+ return -ENOMEM;
+
+ info->pmu = (struct pmu) {
+ .name = dev_name(dev),
+ .module = THIS_MODULE,
+ .event_init = cpmu_event_init,
+ .pmu_enable = cpmu_pmu_enable,
+ .pmu_disable = cpmu_pmu_disable,
+ .add = cpmu_event_add,
+ .del = cpmu_event_del,
+ .start = cpmu_event_start,
+ .stop = cpmu_event_stop,
+ .read = cpmu_read,
+ .task_ctx_nr = perf_invalid_context,
+ .attr_groups = cpmu_attr_groups,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
+ };
+
+ if (info->irq <= 0)
+ return -EINVAL;
+
+
+ rc = pci_irq_vector(pdev, info->irq);
+ if (rc < 0)
+ return rc;
+ irq = rc;
+
+ irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_overflow\n", dev_name(dev));
+ if (!irq_name)
+ return -ENOMEM;
+
+ rc = devm_request_irq(dev, irq, cpmu_irq, IRQF_SHARED, irq_name, info);
+ if (rc)
+ return rc;
+ info->irq = irq;
+
+ rc = cpuhp_state_add_instance(cpmu_cpuhp_state_num, &info->node);
+ if (rc)
+ return rc;
+
+ rc = perf_pmu_register(&info->pmu, info->pmu.name, -1);
+ if (rc)
+ return rc;
+
+ dev_set_drvdata(dev, info);
+
+ return 0;
+}
+
+static void cxl_cpmu_remove(struct device *dev)
+{
+ struct cpmu_info *info = dev_get_drvdata(dev);
+
+ perf_pmu_unregister(&info->pmu);
+ cpuhp_state_remove_instance_nocalls(cpmu_cpuhp_state_num, &info->node);
+}
+
+static struct cxl_driver cxl_cpmu_driver = {
+ .name = "cxl_cpmu",
+ .probe = cxl_cpmu_probe,
+ .remove = cxl_cpmu_remove,
+ .id = CXL_DEVICE_CPMU,
+};
+
+static int cpmu_online_cpu(unsigned int cpu, struct hlist_node *node)
+{
+ struct cpmu_info *info = hlist_entry_safe(node, struct cpmu_info, node);
+
+ if (info->on_cpu != -1)
+ return 0;
+
+ info->on_cpu = cpu;
+ WARN_ON(irq_set_affinity(info->irq, cpumask_of(cpu)));
+
+ return 0;
+}
+
+static int cpmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
+{
+ struct cpmu_info *info = hlist_entry_safe(node, struct cpmu_info, node);
+ unsigned int target;
+
+ if (info->on_cpu != cpu)
+ return 0;
+
+ info->on_cpu = -1;
+ target = cpumask_first(cpu_online_mask);
+ if (target >= nr_cpu_ids) {
+ dev_err(info->pmu.dev, "Unable to find a suitable CPU\n");
+ return 0;
+ }
+
+ perf_pmu_migrate_context(&info->pmu, cpu, target);
+ info->on_cpu = target;
+ WARN_ON(irq_set_affinity(info->irq, cpumask_of(target)));
+
+ return 0;
+}
+
+static __init int cxl_cpmu_init(void)
+{
+ int rc;
+
+ rc = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
+ "AP_PERF_CPMU_ONLINE",
+ cpmu_online_cpu, cpmu_offline_cpu);
+ if (rc < 0)
+ return rc;
+ cpmu_cpuhp_state_num = rc;
+
+ rc = cxl_driver_register(&cxl_cpmu_driver);
+ if (rc)
+ cpuhp_remove_multi_state(cpmu_cpuhp_state_num);
+
+ return rc;
+}
+
+static __exit void cxl_cpmu_exit(void)
+{
+ cxl_driver_unregister(&cxl_cpmu_driver);
+ cpuhp_remove_multi_state(cpmu_cpuhp_state_num);
+}
+
+MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS(CXL);
+module_init(cxl_cpmu_init);
+module_exit(cxl_cpmu_exit);
--
2.32.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [RFC PATCH v2 4/4] docs: perf: Minimal introduction the the CXL PMU device and driver.
2022-08-24 10:36 [RFC PATCH v2 0/4] CXL 3.0 Performance Monitoring Unit support Jonathan Cameron
` (2 preceding siblings ...)
2022-08-24 10:36 ` [RFC PATCH v2 3/4] cxl: CXL Performance Monitoring Unit driver Jonathan Cameron
@ 2022-08-24 10:36 ` Jonathan Cameron
2022-09-22 20:41 ` Dave Jiang
3 siblings, 1 reply; 12+ messages in thread
From: Jonathan Cameron @ 2022-08-24 10:36 UTC (permalink / raw)
To: linux-cxl, Dan Williams, Alison Schofield, Vishal Verma,
Ira Weiny, Ben Widawsky, linux-perf-users, Will Deacon,
Mark Rutland
Cc: linuxarm
Very basic introduction to the device and the current driver support
provided. I expect to expand on this in future versions of this patch
set.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
--
RFC:
- I'll post separately about this shortly, but it seems very odd
to me that there is no way to assign a parent to an event_sources
device. As a result we get the messy approach of playing match
the name to figure out what the CPMU instance is connected to.
---
Documentation/admin-guide/perf/cxl.rst | 60 ++++++++++++++++++++++++
Documentation/admin-guide/perf/index.rst | 1 +
2 files changed, 61 insertions(+)
diff --git a/Documentation/admin-guide/perf/cxl.rst b/Documentation/admin-guide/perf/cxl.rst
new file mode 100644
index 000000000000..6ffc057591fb
--- /dev/null
+++ b/Documentation/admin-guide/perf/cxl.rst
@@ -0,0 +1,60 @@
+======================================
+CXL Performance Monitoring Unit (CPMU)
+======================================
+
+The CXL rev 3.0 specification provides a definition of CXL Performance
+Monitoring Unit in section 13.2: Performance Monitoring.
+
+CXL components (e.g. Root Port, Switch Upstream Port, End Point) may have
+any number of CPMU instances. CPMU capabilities are fully discoverable from
+the devices. The specification provides event definitions for all CXL protocol
+message types and a set of additional events for things commonly counted on
+CXL devices (e.g. DRAM events).
+
+CPMU driver
+===========
+
+The CPMU driver register a perf PMU with the name cpmu<id> on the CXL bus.
+
+ /sys/bus/cxl/device/cpmu<id>
+
+The associated PMU is registered as
+
+ /sys/bus/event_sources/devices/cpmu<id>
+
+In common with other CXL bus devices, the id has no specific meaning and the
+relationship to specific CXL device should be established via the device parent
+of the device on the CXL bus.
+
+PMU driver provides description of available events and filter options in sysfs.
+
+The "format" directory describes all formats of the config (event vendor id,
+group id and mask) config1 (threshold, filter enables) and config2 (filter
+parameters) fields of the perf_event_attr structure. The "events" directory
+describes all documented events show in perf list.
+
+The events shown in perf list are the most fine grained events with a single
+bit of the event mask set. More general events may be enable by setting
+multiple mask bits in config. For example, all Device to Host Read Requests
+may be captured on a single counter by setting the bits for all of
+
+* d2h_req_rdcurr
+* d2h_req_rdown
+* d2h_req_rdshared
+* d2h_req_rdany
+* d2h_req_rdownnodata
+
+Example of usage::
+
+ $#perf list
+ cpmu0/clock_ticks/ [Kernel PMU event]
+ cpmu0/d2h_req_itomwr/ [Kernel PMU event]
+ cpmu0/d2h_req_rdany/ [Kernel PMU event]
+ cpmu0/d2h_req_rdcurr/ [Kernel PMU event]
+ -----------------------------------------------------------
+
+ $# perf stat -e cpmu0/clock_ticks/ -e cpmu0/d2h_req_itowrm/
+
+The driver does not support sampling. So "perf record" and attaching to
+a task are unsupported.
+
diff --git a/Documentation/admin-guide/perf/index.rst b/Documentation/admin-guide/perf/index.rst
index 9c9ece88ce53..f12cfe76e1f0 100644
--- a/Documentation/admin-guide/perf/index.rst
+++ b/Documentation/admin-guide/perf/index.rst
@@ -18,3 +18,4 @@ Performance monitor support
xgene-pmu
arm_dsu_pmu
thunderx2-pmu
+ cxl
--
2.32.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [RFC PATCH v2 2/4] cxl/pci: Find and register CXL PMU devices
2022-08-24 10:36 ` [RFC PATCH v2 2/4] cxl/pci: Find and register CXL PMU devices Jonathan Cameron
@ 2022-09-01 22:36 ` Dave Jiang
2022-10-18 11:19 ` Jonathan Cameron
0 siblings, 1 reply; 12+ messages in thread
From: Dave Jiang @ 2022-09-01 22:36 UTC (permalink / raw)
To: Jonathan Cameron, linux-cxl, Dan Williams, Alison Schofield,
Vishal Verma, Ira Weiny, Ben Widawsky, linux-perf-users,
Will Deacon, Mark Rutland
Cc: linuxarm
On 8/24/2022 3:36 AM, Jonathan Cameron wrote:
> CXL PMU devices can be found from entries in the Register
> Locator DVSEC.
>
> In order to register the minimum number of IRQ vectors necessary
> to support all CPMUs found, separate the registration into two
> steps. First find the devices, and query the IRQs used and then
> register the devices. Between these two steps, request the
> IRQ vectors necessary and enable bus master support.
>
> Future IRQ users for CXL type 3 devices (e.g. DOEs) will need to
> follow a similar pattern the number of vectors necessary is known
> before any parts of the driver stack rely on their availability.
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> ---
>
> Open questions
> 1) Is this IRQ vector 'count' / request then use approach flexible
> enough for other interrupt users on these devices.
> 2) Does hanging the CPMU off the PCI device make sense. These can
> occur in Switch upstream ports as well.
> 3) Naming. It would be nice if the device naming indicated which
> EP these were associated with, but that wouldn't be inline
> with the rest of the CXL bus device naming. What is best
> option here?
> ---
> drivers/cxl/core/Makefile | 1 +
> drivers/cxl/core/core.h | 3 ++
> drivers/cxl/core/cpmu.c | 69 +++++++++++++++++++++++++++++++++++
> drivers/cxl/core/port.c | 2 ++
> drivers/cxl/core/regs.c | 29 +++++++++++++++
> drivers/cxl/cpmu.h | 54 ++++++++++++++++++++++++++++
> drivers/cxl/cxl.h | 15 ++++++++
> drivers/cxl/cxlpci.h | 1 +
> drivers/cxl/pci.c | 76 ++++++++++++++++++++++++++++++++++++++-
> 9 files changed, 249 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile
> index 79c7257f4107..1318e8a6830f 100644
> --- a/drivers/cxl/core/Makefile
> +++ b/drivers/cxl/core/Makefile
> @@ -10,4 +10,5 @@ cxl_core-y += memdev.o
> cxl_core-y += mbox.o
> cxl_core-y += pci.o
> cxl_core-y += hdm.o
> +cxl_core-y += cpmu.o
> cxl_core-$(CONFIG_CXL_REGION) += region.o
> diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
> index 1d8f87be283f..d2b12cdfd61f 100644
> --- a/drivers/cxl/core/core.h
> +++ b/drivers/cxl/core/core.h
> @@ -14,12 +14,14 @@ extern struct device_attribute dev_attr_create_pmem_region;
> extern struct device_attribute dev_attr_delete_region;
> extern struct device_attribute dev_attr_region;
> extern const struct device_type cxl_pmem_region_type;
> +extern const struct device_type cxl_cpmu_type;
> extern const struct device_type cxl_region_type;
> void cxl_decoder_kill_region(struct cxl_endpoint_decoder *cxled);
> #define CXL_REGION_ATTR(x) (&dev_attr_##x.attr)
> #define CXL_REGION_TYPE(x) (&cxl_region_type)
> #define SET_CXL_REGION_ATTR(x) (&dev_attr_##x.attr),
> #define CXL_PMEM_REGION_TYPE(x) (&cxl_pmem_region_type)
> +#define CXL_CPMU_TYPE(x) (&cxl_cpmu_region_type)
> int cxl_region_init(void);
> void cxl_region_exit(void);
> #else
> @@ -37,6 +39,7 @@ static inline void cxl_region_exit(void)
> #define CXL_REGION_TYPE(x) NULL
> #define SET_CXL_REGION_ATTR(x)
> #define CXL_PMEM_REGION_TYPE(x) NULL
> +#define CXL_CPMU_TYPE(x) NULL
> #endif
>
> struct cxl_send_command;
> diff --git a/drivers/cxl/core/cpmu.c b/drivers/cxl/core/cpmu.c
> new file mode 100644
> index 000000000000..cad02f3d43c3
> --- /dev/null
> +++ b/drivers/cxl/core/cpmu.c
> @@ -0,0 +1,69 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/* Copyright(c) 2022 Huawei. All rights reserved. */
> +
> +#include <linux/device.h>
> +#include <linux/slab.h>
> +#include <linux/idr.h>
> +#include <cxlmem.h>
> +#include <cpmu.h>
> +#include <cxl.h>
> +#include "core.h"
> +
> +static DEFINE_IDA(cpmu_ida);
> +
> +static void cxl_cpmu_release(struct device *dev)
> +{
> + struct cxl_cpmu *cpmu = container_of(dev, struct cxl_cpmu, dev);
> +
> + ida_free(&cpmu_ida, cpmu->id);
> + kfree(cpmu);
> +}
> +
> +const struct device_type cxl_cpmu_type = {
> + .name = "cxl_cpmu",
> + .release = cxl_cpmu_release,
> +};
> +
> +static void remove_dev(void *dev)
> +{
> + device_del(dev);
> +}
> +
> +int devm_cxl_cpmu_add(struct device *parent, struct cxl_cpmu_regs *regs, int index)
> +{
> + struct cxl_cpmu *cpmu;
> + struct device *dev;
> + int rc;
> +
> + cpmu = kzalloc(sizeof(*cpmu), GFP_KERNEL);
> + if (!cpmu)
> + return -ENOMEM;
> +
> + cpmu->base = regs->cpmu;
> + dev = &cpmu->dev;
> + device_initialize(dev);
> + device_set_pm_not_required(dev);
> + dev->parent = parent;
> + dev->bus = &cxl_bus_type;
> + dev->type = &cxl_cpmu_type;
> + rc = ida_alloc(&cpmu_ida, GFP_KERNEL);
> + if (rc < 0)
> + goto err;
> + cpmu->id = rc;
> +
> + rc = dev_set_name(dev, "cpmu%d", cpmu->id);
> + if (rc)
> + goto err;
> +
> + rc = device_add(dev);
> + if (rc)
> + goto err;
> +
> + return devm_add_action_or_reset(parent, remove_dev, dev);
> +
> +err:
> + put_device(&cpmu->dev);
> + return rc;
> +}
> +EXPORT_SYMBOL_NS_GPL(devm_cxl_cpmu_add, CXL);
> +
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 1629c7a4033f..66bde8e2edb8 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -55,6 +55,8 @@ static int cxl_device_id(struct device *dev)
> return CXL_DEVICE_MEMORY_EXPANDER;
> if (dev->type == CXL_REGION_TYPE())
> return CXL_DEVICE_REGION;
> + if (dev->type == &cxl_cpmu_type)
> + return CXL_DEVICE_CPMU;
> return 0;
> }
>
> diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
> index 2f651211d120..1ba1a77ecbf1 100644
> --- a/drivers/cxl/core/regs.c
> +++ b/drivers/cxl/core/regs.c
> @@ -6,6 +6,7 @@
> #include <linux/pci.h>
> #include <cxlmem.h>
> #include <cxlpci.h>
> +#include <cpmu.h>
>
> /**
> * DOC: cxl registers
> @@ -331,3 +332,31 @@ int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type)
> }
> EXPORT_SYMBOL_NS_GPL(cxl_count_regblock, CXL);
>
> +int cxl_map_cpmu_regs(struct pci_dev *pdev,
> + struct cxl_cpmu_regs *regs,
> + struct cxl_register_map *map)
> +{
> + struct device *dev = &pdev->dev;
> + resource_size_t phys_addr;
> +
> + phys_addr = pci_resource_start(pdev, map->barno) + map->block_offset;
> + regs->cpmu = devm_cxl_iomap_block(dev, phys_addr, CPMU_REGMAP_SIZE);
> + if (!regs->cpmu)
> + return -ENOMEM;
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_map_cpmu_regs, CXL);
> +
> +int cxl_cpmu_get_irq(struct cxl_cpmu_regs *regs)
> +{
> + int irq = -1;
> + u64 val;
> +
> + val = readq(regs->cpmu + CPMU_CAP_REG);
> + if (FIELD_GET(CPMU_CAP_INT, val))
> + irq = FIELD_GET(CPMU_CAP_MSI_N_MSK, val);
> +
> + return irq;
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_cpmu_get_irq, CXL);
> diff --git a/drivers/cxl/cpmu.h b/drivers/cxl/cpmu.h
> new file mode 100644
> index 000000000000..2db885524330
> --- /dev/null
> +++ b/drivers/cxl/cpmu.h
> @@ -0,0 +1,54 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright(c) 2022 Huawei
> + * CXL Specification rev 3.0 Setion 8.2.7 (CPMU Register Interface)
> + */
> +#ifndef CXL_CPMU_H
> +#define CXL_CPMU_H
> +
> +#define CPMU_CAP_REG 0x0
> +#define CPMU_CAP_NUM_COUNTERS_MSK GENMASK_ULL(4, 0)
> +#define CPMU_CAP_COUNTER_WIDTH_MSK GENMASK_ULL(15, 8)
> +#define CPMU_CAP_NUM_EVN_CAP_REG_SUP_MSK GENMASK_ULL(24, 20)
> +#define CPMU_CAP_FILTERS_SUP_MSK GENMASK_ULL(39, 32)
> +#define CPMU_CAP_MSI_N_MSK GENMASK_ULL(47, 44)
> +#define CPMU_CAP_WRITEABLE_WHEN_FROZEN BIT_ULL(48)
> +#define CPMU_CAP_FREEZE BIT_ULL(49)
> +#define CPMU_CAP_INT BIT_ULL(50)
> +#define CPMU_CAP_VERSION_MSK GENMASK_ULL(63, 60)
> +
> +#define CPMU_OVERFLOW_REG 0x10
> +#define CPMU_FREEZE_REG 0x18
> +#define CPMU_EVENT_CAP_REG(n) (0x100 + 8 * (n))
> +#define CPMU_EVENT_CAP_SUPPORTED_EVENTS_MSK GENMASK_ULL(31, 0)
> +#define CPMU_EVENT_CAP_GROUP_ID_MSK GENMASK_ULL(47, 32)
> +#define CPMU_EVENT_CAP_VENDOR_ID_MSK GENMASK_ULL(63, 48)
> +
> +#define CPMU_COUNTER_CFG_REG(n) (0x200 + 8 * (n))
> +#define CPMU_COUNTER_CFG_TYPE_MSK GENMASK_ULL(1, 0)
> +#define CPMU_COUNTER_CFG_TYPE_FREE_RUN 0
> +#define CPMU_COUNTER_CFG_TYPE_FIXED_FUN 1
> +#define CPMU_COUNTER_CFG_TYPE_CONFIGURABLE 2
> +#define CPMU_COUNTER_CFG_ENABLE BIT_ULL(8)
> +#define CPMU_COUNTER_CFG_INT_ON_OVRFLW BIT_ULL(9)
> +#define CPMU_COUNTER_CFG_FREEZE_ON_OVRFLW BIT_ULL(10)
> +#define CPMU_COUNTER_CFG_EDGE BIT_ULL(11)
> +#define CPMU_COUNTER_CFG_INVERT BIT_ULL(12)
> +#define CPMU_COUNTER_CFG_THRESHOLD_MSK GENMASK_ULL(23, 16)
> +#define CPMU_COUNTER_CFG_EVENTS_MSK GENMASK_ULL(55, 24)
> +#define CPMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK GENMASK_ULL(63, 59)
> +
> +#define CPMU_FILTER_CFG_REG(n, f) (0x400 + 4 * ((f) + (n) * 8))
> +#define CPMU_FILTER_CFG_VALUE_MSK GENMASK(15, 0)
> +
> +#define CPMU_COUNTER_REG(n) (0xc00 + 8 * (n))
> +
> +#define CPMU_REGMAP_SIZE 0xe00 /* Table 8-32 CXL 3.0 specification */
> +struct cxl_cpmu {
> + struct device dev;
> + void __iomem *base;
> + int id;
> +};
> +
> +#define to_cxl_cpmu(dev) container_of(dev, struct cxl_cpmu, dev)
> +#endif
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 5a1bcdbda654..2768e1677e2b 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -166,6 +166,10 @@ struct cxl_regs {
> struct_group_tagged(cxl_device_regs, device_regs,
> void __iomem *status, *mbox, *memdev;
> );
> +
> + struct_group_tagged(cxl_cpmu_regs, cpmu_regs,
> + void __iomem *cpmu;
> + );
> };
>
> struct cxl_reg_map {
> @@ -184,6 +188,10 @@ struct cxl_device_reg_map {
> struct cxl_reg_map memdev;
> };
>
> +struct cxl_cpmu_reg_map {
> + struct cxl_reg_map cpmu;
> +};
> +
> /**
> * struct cxl_register_map - DVSEC harvested register block mapping parameters
> * @base: virtual base of the register-block-BAR + @block_offset
> @@ -201,6 +209,7 @@ struct cxl_register_map {
> union {
> struct cxl_component_reg_map component_map;
> struct cxl_device_reg_map device_map;
> + struct cxl_cpmu_reg_map cpmu_map;
> };
> };
>
> @@ -219,6 +228,10 @@ enum cxl_regloc_type;
> int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type);
> int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
> struct cxl_register_map *map, int index);
> +int cxl_map_cpmu_regs(struct pci_dev *pdev,
> + struct cxl_cpmu_regs *regs,
> + struct cxl_register_map *map);
> +int cxl_cpmu_get_irq(struct cxl_cpmu_regs *regs);
> void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
> resource_size_t length);
>
> @@ -626,6 +639,7 @@ void cxl_driver_unregister(struct cxl_driver *cxl_drv);
> #define CXL_DEVICE_MEMORY_EXPANDER 5
> #define CXL_DEVICE_REGION 6
> #define CXL_DEVICE_PMEM_REGION 7
> +#define CXL_DEVICE_CPMU 8
>
> #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*")
> #define CXL_MODALIAS_FMT "cxl:t%d"
> @@ -653,6 +667,7 @@ static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev)
> }
> #endif
>
> +int devm_cxl_cpmu_add(struct device *parent, struct cxl_cpmu_regs *regs, int idx);
> /*
> * Unit test builds overrides this to __weak, find the 'strong' version
> * of these symbols in tools/testing/cxl/.
> diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
> index eec597dbe763..a842c3d1341a 100644
> --- a/drivers/cxl/cxlpci.h
> +++ b/drivers/cxl/cxlpci.h
> @@ -59,6 +59,7 @@ enum cxl_regloc_type {
> CXL_REGLOC_RBI_COMPONENT,
> CXL_REGLOC_RBI_VIRT,
> CXL_REGLOC_RBI_MEMDEV,
> + CXL_REGLOC_RBI_CPMU,
> CXL_REGLOC_RBI_TYPES
> };
>
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 1758380247ec..e1276fdc8609 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -428,12 +428,39 @@ static void devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds)
> }
> }
>
> +static void cxl_pci_free_irq_vectors(void *data)
> +{
> + pci_free_irq_vectors(data);
> +}
> +
> +static int cxl_alloc_irq_vectors(struct cxl_dev_state *cxlds, int vectors)
> +{
> + struct device *dev = cxlds->dev;
> + struct pci_dev *pdev = to_pci_dev(dev);
> + int rc;
> +
> + rc = pci_alloc_irq_vectors(pdev, vectors, vectors,
> + PCI_IRQ_MSI | PCI_IRQ_MSIX);
> + if (rc < 0)
> + return rc;
> + if (rc != vectors) {
I don't think you'll hit here since you passed in vectors for min and
max. You'll get -ENOSPC and return from the earlier check.
https://elixir.bootlin.com/linux/v6.0-rc3/source/drivers/pci/msi/msi.c#L1005
DJ
> + pci_err(pdev, "Not enough interrupts; use polling where supported\n");
> + /* Some got allocated; clean them up */
> + cxl_pci_free_irq_vectors(pdev);
> + return -ENOSPC;
> + }
> +
> + return devm_add_action_or_reset(dev, cxl_pci_free_irq_vectors, pdev);
> +}
> +
> static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> {
> + struct cxl_cpmu_regs *cpmu_regs_array = NULL;
> struct cxl_register_map map;
> struct cxl_memdev *cxlmd;
> struct cxl_dev_state *cxlds;
> - int rc;
> + int i, rc, cpmu_count;
> + int max_interrupt = -1;
>
> /*
> * Double check the anonymous union trickery in struct cxl_regs
> @@ -494,6 +521,53 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> if (rc)
> return rc;
>
> + /*
> + * Before registering sub devices that use interrupts, the maximum
> + * interrupt used on the device should be established to allow the correct
> + * number of irq vectors to be requested. Separate the registration process
> + * into before / after interrupt vector request.
> + */
> + cpmu_count = cxl_count_regblock(pdev, CXL_REGLOC_RBI_CPMU);
> + if (cpmu_count) {
> + cpmu_regs_array = kmalloc_array(cpmu_count, sizeof(cpmu_regs_array),
> + GFP_KERNEL);
> + if (!cpmu_regs_array)
> + return -ENOMEM;
> + }
> + /* Pass one - just enough to find out what interrupts are used */
> + for (i = 0; i < cpmu_count; i++) {
> + int irq;
> +
> + rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_CPMU, &map, i);
> + if (rc) {
> + kfree(cpmu_regs_array);
> + return rc;
> + }
> +
> + rc = cxl_map_cpmu_regs(pdev, &cpmu_regs_array[i], &map);
> + if (rc) {
> + kfree(cpmu_regs_array);
> + return rc;
> + }
> +
> + irq = cxl_cpmu_get_irq(&cpmu_regs_array[i]);
> + max_interrupt = max(max_interrupt, irq);
> + }
> +
> + if (max_interrupt >= 0) {
> + pci_set_master(pdev);
> + rc = cxl_alloc_irq_vectors(cxlds, max_interrupt + 1);
> + if (rc) {
> + kfree(cpmu_regs_array);
> + return rc;
> + }
> + }
> +
> + /* Pass 2 - register the CPMU instances */
> + for (i = 0; i < cpmu_count; i++)
> + devm_cxl_cpmu_add(cxlds->dev, &cpmu_regs_array[i], i);
> + kfree(cpmu_regs_array);
> +
> cxlmd = devm_cxl_add_memdev(cxlds);
> if (IS_ERR(cxlmd))
> return PTR_ERR(cxlmd);
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RFC PATCH v2 3/4] cxl: CXL Performance Monitoring Unit driver
2022-08-24 10:36 ` [RFC PATCH v2 3/4] cxl: CXL Performance Monitoring Unit driver Jonathan Cameron
@ 2022-09-22 20:19 ` Dave Jiang
2022-10-18 11:26 ` Jonathan Cameron
0 siblings, 1 reply; 12+ messages in thread
From: Dave Jiang @ 2022-09-22 20:19 UTC (permalink / raw)
To: Jonathan Cameron, linux-cxl, Dan Williams, Alison Schofield,
Vishal Verma, Ira Weiny, Ben Widawsky, linux-perf-users,
Will Deacon, Mark Rutland
Cc: linuxarm
On 8/24/2022 3:36 AM, Jonathan Cameron wrote:
> CXL rev 3.0 introduces a standard performance monitoring hardware
> block to CXL. Instances are discovered using CXL Register Locator DVSEC
> entries. Each CXL component may have multiple PMUs.
>
> This initial driver supports on a subset of types of counter.
> It support counters that are either fixed or configurable, but requires
> that they support the ability to freeze and write value whilst frozen.
>
> Development done with QEMU model which will be posted shortly.
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Besides couple nits in comments below, Reviewed-by: Dave Jiang
<dave.jiang@intel.com>
>
> --
> RFC questions:
> - Creation of the devices. Currently hung off the cxl_pci driver.
> May want to rethink to avoid needing to replicate registration code
> for other CXL components.
> - Needs more testing, but wanted to share early in case major refactoring
> needed.
> - Where to put the driver. Previous discussions on similar drivers
> led to them being under drivers/perf (hisi_pcie_pmu)
> ---
> drivers/cxl/Kconfig | 12 +
> drivers/cxl/Makefile | 1 +
> drivers/cxl/cpmu.c | 945 +++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 958 insertions(+)
>
> diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
> index 768ced3d6fe8..d9e6775c05a5 100644
> --- a/drivers/cxl/Kconfig
> +++ b/drivers/cxl/Kconfig
> @@ -111,4 +111,16 @@ config CXL_REGION
> select MEMREGION
> select GET_FREE_REGION
>
> +config CXL_CPMU
> + tristate "CXL Performance Monitoring Unit"
> + default CXL_BUS
> + help
> + Support performance monitoring as defined in CXL rev 3.0
> + section 13.2: Performance Monitoring. CXL components may have
> + one or more CXL Performance Monitoring Units (CPMUs).
> +
> + Say 'y/m' to enable a driver that will attach to performance
> + monitoring units and provide standard perf based interfaces.
> +
> + If unsure say 'm'.
> endif
> diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile
> index a78270794150..f55c2751ac10 100644
> --- a/drivers/cxl/Makefile
> +++ b/drivers/cxl/Makefile
> @@ -5,6 +5,7 @@ obj-$(CONFIG_CXL_MEM) += cxl_mem.o
> obj-$(CONFIG_CXL_ACPI) += cxl_acpi.o
> obj-$(CONFIG_CXL_PMEM) += cxl_pmem.o
> obj-$(CONFIG_CXL_PORT) += cxl_port.o
> +obj-$(CONFIG_CXL_CPMU) += cpmu.o
>
> cxl_mem-y := mem.o
> cxl_pci-y := pci.o
> diff --git a/drivers/cxl/cpmu.c b/drivers/cxl/cpmu.c
> new file mode 100644
> index 000000000000..6549a553641b
> --- /dev/null
> +++ b/drivers/cxl/cpmu.c
> @@ -0,0 +1,945 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +
> +/*
> + * Copyright(c) 2022 Huawei
> + *
> + * The CXL 3.0 specification includes a standard performance monitoring unit,
> + * called the CLX PMU, or CPMU. In order to allow a high degree of
> + * implementation flexibility the specification provides a wide range of
> + * options all of which are self describing.
> + *
> + * Details in CXL rev 3.0 section 8.2.7 CPMU Register Interface
> + *
> + * TODO:
> + * o May be useful to name some summed event groups. Figure out which.
> + * CPMU event selection is based on summing of bitmaps of events within
> + * a given event group. With a limited supply of configurable counters, this
> + * provides flexibility between very specific events such as d2h_req_rdcurr
> + * (one type of read request) or combining events counted by the hardware
> + * counter to allow d2h_req_rd to be counted as sum of fine grained events
> + * d2h_req_rd = d2h_req_rdcurr + d2h_req_rdown + d2h_req_rdshared +
> + * d2h_req_rdany + d2h_req_rdownnodata
> + * Thus d2h_req_rd requires one configurable counter instead of 5 if the
> + * counters were summed in userspace.
> + * Current interface allows userspace to specify the bitmap directly, but
> + * it may make sense to provide explicit attributes for commonly used
> + * combinations.
> + * o Support free running counters - copy the intel uncore PMU handling for these.
> + * o CPMUs which do not support freeze.
> + * o Add filter validation in cpmu_event_init() so problems are detected earlier.
> + * o Reject configurations that the hardware is ignoring
> + * (e.g. invert when not invertable)
> + * o Support CPMUs with no interrupts using an HRTIMER.
> + */
> +
> +#include <linux/bitops.h>
> +#include <linux/bits.h>
> +#include <linux/bug.h>
> +#include <linux/device.h>
> +#include <linux/list.h>
> +#include <linux/pci.h>
> +#include <linux/perf_event.h>
> +#include "cpmu.h"
> +#include "cxl.h"
> +
> +/* CXL rev 3.0 Table 13-5 Events under CXL Vendor ID */
> +#define CPMU_GID_CLOCK_TICKS 0x00
> +#define CPMU_GID_D2H_REQ 0x0010
> +#define CPMU_GID_D2H_RSP 0x0011
> +#define CPMU_GID_H2D_REQ 0x0012
> +#define CPMU_GID_H2D_RSP 0x0013
> +#define CPMU_GID_CACHE_DATA 0x0014
> +#define CPMU_GID_M2S_REQ 0x0020
> +#define CPMU_GID_M2S_RWD 0x0021
> +#define CPMU_GID_M2S_BIRSP 0x0022
> +#define CPMU_GID_S2M_BISNP 0x0023
> +#define CPMU_GID_S2M_NDR 0x0024
> +#define CPMU_GID_S2M_DRS 0x0025
> +#define CPMU_GID_DDR 0x8000
> +
> +static int cpmu_cpuhp_state_num;
> +
> +struct cpmu_event {
> + u16 vid;
> + u16 gid;
> + u32 msk;
> + bool configurable;
> + union {
> + int counter_idx; /* fixed counters */
> + int event_idx; /* configurable counters */
> + };
> + struct list_head node;
> +};
> +
> +#define CPMU_MAX_COUNTERS 32
> +struct cpmu_info {
> + struct pmu pmu;
> + void __iomem *base;
> + struct perf_event **hw_events;
> + struct list_head cpmu_events;
> + DECLARE_BITMAP(conf_counter_bm, CPMU_MAX_COUNTERS);
> + u16 counter_width;
> + u8 num_counters;
> + u8 num_event_capabilities;
> + int on_cpu;
> + struct hlist_node node;
> + bool freeze_for_enable;
> + bool filter_hdm;
> + int irq;
> +};
> +
> +#define pmu_to_cpmu_info(_pmu) container_of(_pmu, struct cpmu_info, pmu)
> +
> +/*
> + * All CPMU counters are discoverable via the Event Capabilities Registers.
> + * Each Event Capability register contains a a VID / GroupID.
> + * A counter may then count any combination (by summing) of events in
> + * that group which are in the Supported Events Bitmask.
> + * However, there are some complexities to the scheme.
> + * - Fixed function counters refer to an Event Capabilities register.
> + * That event capability register is not then used for Configurable
> + * counters.
> + * TODO: Support summed events.
> + */
> +static int cpmu_parse_caps(struct device *dev, struct cpmu_info *info)
> +{
> + DECLARE_BITMAP(fixed_counter_event_cap_bm, 32) = {0};
> + void __iomem *base = info->base;
> + u64 val, eval;
> + int i;
> +
> + val = readq(base + CPMU_CAP_REG);
> + info->freeze_for_enable = FIELD_GET(CPMU_CAP_WRITEABLE_WHEN_FROZEN, val) &
> + FIELD_GET(CPMU_CAP_FREEZE, val);
> + if (!info->freeze_for_enable) {
> + dev_err(dev, "Driver does not support CPMUs that do not support freeze for enable\n");
> + return -ENODEV;
> + }
> +
> + info->num_counters = FIELD_GET(CPMU_CAP_NUM_COUNTERS_MSK, val) + 1;
> + info->counter_width = FIELD_GET(CPMU_CAP_COUNTER_WIDTH_MSK, val);
> + info->num_event_capabilities = FIELD_GET(CPMU_CAP_NUM_EVN_CAP_REG_SUP_MSK, val) + 1;
> +
> + info->filter_hdm = FIELD_GET(CPMU_CAP_FILTERS_SUP_MSK, val);
> + if (FIELD_GET(CPMU_CAP_INT, val))
> + info->irq = FIELD_GET(CPMU_CAP_MSI_N_MSK, val);
> + else
> + info->irq = -1;
> +
> + /* First handle fixed function counters; note if configurable counters found */
> + for (i = 0; i < info->num_counters; i++) {
> + struct cpmu_event *cpmu_ev;
> + u32 events_msk;
> + u8 group_idx;
> +
> + val = readq(base + CPMU_COUNTER_CFG_REG(i));
> +
> + if (FIELD_GET(CPMU_COUNTER_CFG_TYPE_MSK, val) ==
> + CPMU_COUNTER_CFG_TYPE_CONFIGURABLE) {
> + set_bit(i, info->conf_counter_bm);
> + }
> +
> + if (FIELD_GET(CPMU_COUNTER_CFG_TYPE_MSK, val) !=
> + CPMU_COUNTER_CFG_TYPE_FIXED_FUN)
> + continue;
> +
> + /* In this case we know which fields are const */
> + group_idx = FIELD_GET(CPMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK, val);
> + events_msk = FIELD_GET(CPMU_COUNTER_CFG_EVENTS_MSK, val);
> + eval = readq(base + CPMU_EVENT_CAP_REG(group_idx));
> + cpmu_ev = devm_kzalloc(dev, sizeof(*cpmu_ev), GFP_KERNEL);
> + if (!cpmu_ev)
> + return -ENOMEM;
> +
> + cpmu_ev->vid = FIELD_GET(CPMU_EVENT_CAP_VENDOR_ID_MSK, eval);
> + cpmu_ev->gid = FIELD_GET(CPMU_EVENT_CAP_GROUP_ID_MSK, eval);
> + /* For a fixed purpose counter use the events mask from the counter CFG */
> + cpmu_ev->msk = events_msk;
> + cpmu_ev->configurable = false;
> + cpmu_ev->counter_idx = i;
> + /* This list add is never unwound as all entries deleted on remove */
> + list_add(&cpmu_ev->node, &info->cpmu_events);
> + /*
> + * Configurable counters must not use an Event Capability registers that
> + * is in use for a Fixed counter
> + */
> + set_bit(group_idx, fixed_counter_event_cap_bm);
> + }
> +
> + if (!bitmap_empty(info->conf_counter_bm, CPMU_MAX_COUNTERS)) {
> + struct cpmu_event *cpmu_ev;
> + int j;
> + /* Walk event capabilities unused by fixed counters */
> + for_each_clear_bit(j, fixed_counter_event_cap_bm,
> + info->num_event_capabilities) {
> + cpmu_ev = devm_kzalloc(dev, sizeof(*cpmu_ev), GFP_KERNEL);
> + if (!cpmu_ev)
> + return -ENOMEM;
> +
> + eval = readq(base + CPMU_EVENT_CAP_REG(j));
> + cpmu_ev->vid = FIELD_GET(CPMU_EVENT_CAP_VENDOR_ID_MSK, eval);
> + cpmu_ev->gid = FIELD_GET(CPMU_EVENT_CAP_GROUP_ID_MSK, eval);
> + cpmu_ev->msk = FIELD_GET(CPMU_EVENT_CAP_SUPPORTED_EVENTS_MSK, eval);
> + cpmu_ev->event_idx = j;
> + cpmu_ev->configurable = true;
> + list_add(&cpmu_ev->node, &info->cpmu_events);
> + }
> + }
> +
> + return 0;
> +}
> +
> +static ssize_t cpmu_event_sysfs_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct perf_pmu_events_attr *pmu_attr =
> + container_of(attr, struct perf_pmu_events_attr, attr);
> +
> + return sysfs_emit(buf, "config=%#llx\n", pmu_attr->id);
> +}
> +
> +#define CPMU_PMU_EVENT_ATTR(_name, _vid, _gid, _msk) \
> + PMU_EVENT_ATTR_ID(_name, cpmu_event_sysfs_show, \
> + ((u64)(_vid) << 48) | ((u64)(_gid) << 32) | (u64)(_msk))
> +
> +static struct attribute *cpmu_event_attrs[] = {
> + CPMU_PMU_EVENT_ATTR(clock_ticks, 0x1e98, CPMU_GID_CLOCK_TICKS, BIT(0)),
> + /* CXL rev 3.0 Table 3-17 - Device to Host Requests */
> + CPMU_PMU_EVENT_ATTR(d2h_req_rdcurr, 0x1e98, CPMU_GID_D2H_REQ, BIT(1)),
> + CPMU_PMU_EVENT_ATTR(d2h_req_rdown, 0x1e98, CPMU_GID_D2H_REQ, BIT(2)),
> + CPMU_PMU_EVENT_ATTR(d2h_req_rdshared, 0x1e98, CPMU_GID_D2H_REQ, BIT(3)),
> + CPMU_PMU_EVENT_ATTR(d2h_req_rdany, 0x1e98, CPMU_GID_D2H_REQ, BIT(4)),
> + CPMU_PMU_EVENT_ATTR(d2h_req_rdownnodata, 0x1e98, CPMU_GID_D2H_REQ, BIT(5)),
> + CPMU_PMU_EVENT_ATTR(d2h_req_itomwr, 0x1e98, CPMU_GID_D2H_REQ, BIT(6)),
> + CPMU_PMU_EVENT_ATTR(d2h_req_wrcurr, 0x1e98, CPMU_GID_D2H_REQ, BIT(7)),
> + CPMU_PMU_EVENT_ATTR(d2h_req_clflush, 0x1e98, CPMU_GID_D2H_REQ, BIT(8)),
> + CPMU_PMU_EVENT_ATTR(d2h_req_cleanevict, 0x1e98, CPMU_GID_D2H_REQ, BIT(9)),
> + CPMU_PMU_EVENT_ATTR(d2h_req_dirtyevict, 0x1e98, CPMU_GID_D2H_REQ, BIT(10)),
> + CPMU_PMU_EVENT_ATTR(d2h_req_cleanevictnodata, 0x1e98, CPMU_GID_D2H_REQ, BIT(11)),
> + CPMU_PMU_EVENT_ATTR(d2h_req_wowrinv, 0x1e98, CPMU_GID_D2H_REQ, BIT(12)),
> + CPMU_PMU_EVENT_ATTR(d2h_req_wowrinvf, 0x1e98, CPMU_GID_D2H_REQ, BIT(13)),
> + CPMU_PMU_EVENT_ATTR(d2h_req_wrinv, 0x1e98, CPMU_GID_D2H_REQ, BIT(14)),
> + CPMU_PMU_EVENT_ATTR(d2h_req_cacheflushed, 0x1e98, CPMU_GID_D2H_REQ, BIT(16)),
> + /* CXL rev 3.0 Table 3-20 - D2H Repsonse Encodings */
> + CPMU_PMU_EVENT_ATTR(d2h_rsp_rspihiti, 0x1e98, CPMU_GID_D2H_RSP, BIT(4)),
> + CPMU_PMU_EVENT_ATTR(d2h_rsp_rspvhitv, 0x1e98, CPMU_GID_D2H_RSP, BIT(6)),
> + CPMU_PMU_EVENT_ATTR(d2h_rsp_rspihitse, 0x1e98, CPMU_GID_D2H_RSP, BIT(5)),
> + CPMU_PMU_EVENT_ATTR(d2h_rsp_rspshitse, 0x1e98, CPMU_GID_D2H_RSP, BIT(1)),
> + CPMU_PMU_EVENT_ATTR(d2h_rsp_rspsfwdm, 0x1e98, CPMU_GID_D2H_RSP, BIT(7)),
> + CPMU_PMU_EVENT_ATTR(d2h_rsp_rspifwdm, 0x1e98, CPMU_GID_D2H_RSP, BIT(15)),
> + CPMU_PMU_EVENT_ATTR(d2h_rsp_rspvfwdv, 0x1e98, CPMU_GID_D2H_RSP, BIT(22)),
> + /* CXL rev 3.0 Table 3-21 - CXL.cache - Mapping of H2D Requests to D2H Responses */
> + CPMU_PMU_EVENT_ATTR(h2d_req_snpdata, 0x1e98, CPMU_GID_H2D_REQ, BIT(1)),
> + CPMU_PMU_EVENT_ATTR(h2d_req_snpinv, 0x1e98, CPMU_GID_H2D_REQ, BIT(2)),
> + CPMU_PMU_EVENT_ATTR(h2d_req_snpcur, 0x1e98, CPMU_GID_H2D_REQ, BIT(3)),
> + /* CXL rev 3.0 Table 3-22 - H2D Response Opcode Encodings */
> + CPMU_PMU_EVENT_ATTR(h2d_rsp_writepull, 0x1e98, CPMU_GID_H2D_RSP, BIT(1)),
> + CPMU_PMU_EVENT_ATTR(h2d_rsp_go, 0x1e98, CPMU_GID_H2D_RSP, BIT(4)),
> + CPMU_PMU_EVENT_ATTR(h2d_rsp_gowritepull, 0x1e98, CPMU_GID_H2D_RSP, BIT(5)),
> + CPMU_PMU_EVENT_ATTR(h2d_rsp_extcmp, 0x1e98, CPMU_GID_H2D_RSP, BIT(6)),
> + CPMU_PMU_EVENT_ATTR(h2d_rsp_gowritepulldrop, 0x1e98, CPMU_GID_H2D_RSP, BIT(8)),
> + CPMU_PMU_EVENT_ATTR(h2d_rsp_fastgowritepull, 0x1e98, CPMU_GID_H2D_RSP, BIT(13)),
> + CPMU_PMU_EVENT_ATTR(h2d_rsp_goerrwritepull, 0x1e98, CPMU_GID_H2D_RSP, BIT(15)),
> + /* CXL rev 3.0 Table 13-5 directly lists these */
> + CPMU_PMU_EVENT_ATTR(cachedata_d2h_data, 0x1e98, CPMU_GID_CACHE_DATA, BIT(0)),
> + CPMU_PMU_EVENT_ATTR(cachedata_h2d_data, 0x1e98, CPMU_GID_CACHE_DATA, BIT(1)),
> + /* CXL rev 3.0 Table 3-29 M2S Req Memory Opcodes */
> + CPMU_PMU_EVENT_ATTR(m2s_req_meminv, 0x1e98, CPMU_GID_M2S_REQ, BIT(0)),
> + CPMU_PMU_EVENT_ATTR(m2s_req_memrd, 0x1e98, CPMU_GID_M2S_REQ, BIT(1)),
> + CPMU_PMU_EVENT_ATTR(m2s_req_memrddata, 0x1e98, CPMU_GID_M2S_REQ, BIT(2)),
> + CPMU_PMU_EVENT_ATTR(m2s_req_memrdfwd, 0x1e98, CPMU_GID_M2S_REQ, BIT(3)),
> + CPMU_PMU_EVENT_ATTR(m2s_req_memwrfwd, 0x1e98, CPMU_GID_M2S_REQ, BIT(4)),
> + CPMU_PMU_EVENT_ATTR(m2s_req_memspecrd, 0x1e98, CPMU_GID_M2S_REQ, BIT(8)),
> + CPMU_PMU_EVENT_ATTR(m2s_req_meminvnt, 0x1e98, CPMU_GID_M2S_REQ, BIT(9)),
> + CPMU_PMU_EVENT_ATTR(m2s_req_memcleanevict, 0x1e98, CPMU_GID_M2S_REQ, BIT(10)),
> + /* CXL rev 3.0 Table 3-35 M2S RwD Memory Opcodes */
> + CPMU_PMU_EVENT_ATTR(m2s_rwd_memwr, 0x1e98, CPMU_GID_M2S_RWD, BIT(1)),
> + CPMU_PMU_EVENT_ATTR(m2s_rwd_memwrptl, 0x1e98, CPMU_GID_M2S_RWD, BIT(2)),
> + CPMU_PMU_EVENT_ATTR(m2s_rwd_biconflict, 0x1e98, CPMU_GID_M2S_RWD, BIT(4)),
> + /* CXL rev 3.0 Table 3-38 M2S BIRsp Memory Opcodes */
> + CPMU_PMU_EVENT_ATTR(m2s_birsp_i, 0x1e98, CPMU_GID_M2S_BIRSP, BIT(0)),
> + CPMU_PMU_EVENT_ATTR(m2s_birsp_s, 0x1e98, CPMU_GID_M2S_BIRSP, BIT(1)),
> + CPMU_PMU_EVENT_ATTR(m2s_birsp_e, 0x1e98, CPMU_GID_M2S_BIRSP, BIT(2)),
> + CPMU_PMU_EVENT_ATTR(m2s_birsp_iblk, 0x1e98, CPMU_GID_M2S_BIRSP, BIT(4)),
> + CPMU_PMU_EVENT_ATTR(m2s_birsp_sblk, 0x1e98, CPMU_GID_M2S_BIRSP, BIT(5)),
> + CPMU_PMU_EVENT_ATTR(m2s_birsp_eblk, 0x1e98, CPMU_GID_M2S_BIRSP, BIT(6)),
> + /* CXL rev 3.0 Table 3-40 S2M BISnp Opcodes */
> + CPMU_PMU_EVENT_ATTR(s2m_bisnp_cur, 0x1e98, CPMU_GID_S2M_BISNP, BIT(0)),
> + CPMU_PMU_EVENT_ATTR(s2m_bisnp_data, 0x1e98, CPMU_GID_S2M_BISNP, BIT(1)),
> + CPMU_PMU_EVENT_ATTR(s2m_bisnp_inv, 0x1e98, CPMU_GID_S2M_BISNP, BIT(2)),
> + CPMU_PMU_EVENT_ATTR(s2m_bisnp_curblk, 0x1e98, CPMU_GID_S2M_BISNP, BIT(4)),
> + CPMU_PMU_EVENT_ATTR(s2m_bisnp_datblk, 0x1e98, CPMU_GID_S2M_BISNP, BIT(5)),
> + CPMU_PMU_EVENT_ATTR(s2m_bisnp_invblk, 0x1e98, CPMU_GID_S2M_BISNP, BIT(6)),
> + /* CXL rev 3.0 Table 3-43 S2M NDR Opcopdes */
> + CPMU_PMU_EVENT_ATTR(s2m_ndr_cmp, 0x1e98, CPMU_GID_S2M_NDR, BIT(0)),
> + CPMU_PMU_EVENT_ATTR(s2m_ndr_cmps, 0x1e98, CPMU_GID_S2M_NDR, BIT(1)),
> + CPMU_PMU_EVENT_ATTR(s2m_ndr_cmpe, 0x1e98, CPMU_GID_S2M_NDR, BIT(2)),
> + CPMU_PMU_EVENT_ATTR(s2m_ndr_biconflictack, 0x1e98, CPMU_GID_S2M_NDR, BIT(3)),
> + /* CXL rev 3.0 Table 3-46 S2M DRS opcodes */
> + CPMU_PMU_EVENT_ATTR(s2m_drs_memdata, 0x1e98, CPMU_GID_S2M_DRS, BIT(0)),
> + CPMU_PMU_EVENT_ATTR(s2m_drs_memdatanxm, 0x1e98, CPMU_GID_S2M_DRS, BIT(1)),
> + /* CXL rev 3.0 Table 13-5 directly lists these */
> + CPMU_PMU_EVENT_ATTR(ddr_act, 0x1e98, CPMU_GID_DDR, BIT(0)),
> + CPMU_PMU_EVENT_ATTR(ddr_pre, 0x1e98, CPMU_GID_DDR, BIT(1)),
> + CPMU_PMU_EVENT_ATTR(ddr_casrd, 0x1e98, CPMU_GID_DDR, BIT(2)),
> + CPMU_PMU_EVENT_ATTR(ddr_caswr, 0x1e98, CPMU_GID_DDR, BIT(3)),
> + CPMU_PMU_EVENT_ATTR(ddr_refresh, 0x1e98, CPMU_GID_DDR, BIT(4)),
> + CPMU_PMU_EVENT_ATTR(ddr_selfrefreshent, 0x1e98, CPMU_GID_DDR, BIT(5)),
> + CPMU_PMU_EVENT_ATTR(ddr_rfm, 0x1e98, CPMU_GID_DDR, BIT(6)),
> + NULL
> +};
> +
> +static umode_t cpmu_event_is_visible(struct kobject *kobj, struct attribute *attr, int a)
> +{
> + struct device_attribute *dev_attr = container_of(attr, struct device_attribute, attr);
> + struct perf_pmu_events_attr *pmu_attr =
> + container_of(dev_attr, struct perf_pmu_events_attr, attr);
> + struct device *dev = kobj_to_dev(kobj);
> + struct cpmu_info *info = dev_get_drvdata(dev);
> + struct cpmu_event *cpmu_ev;
> + int match_vid = FIELD_GET(GENMASK(63, 48), pmu_attr->id);
> + int match_gid = FIELD_GET(GENMASK(47, 32), pmu_attr->id);
> + int match_msk = FIELD_GET(GENMASK(31, 0), pmu_attr->id);
> +
> + list_for_each_entry(cpmu_ev, &info->cpmu_events, node) {
> + if (match_vid != cpmu_ev->vid || match_gid != cpmu_ev->gid)
> + continue;
> +
> + if (!cpmu_ev->configurable) {
> + /* Precise match for fixed counter */
> + if (match_msk == cpmu_ev->msk)
> + return attr->mode;
> + } else {
> + /* Request mask must be subset of supported */
> + if (!(match_msk & ~cpmu_ev->msk))
> + return attr->mode;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static const struct attribute_group cpmu_events = {
> + .name = "events",
> + .attrs = cpmu_event_attrs,
> + .is_visible = cpmu_event_is_visible,
> +};
> +
> +static ssize_t cpmu_format_sysfs_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct dev_ext_attribute *eattr;
> +
> + eattr = container_of(attr, struct dev_ext_attribute, attr);
> +
> + return sysfs_emit(buf, "%s\n", (char *)eattr->var);
> +}
> +
> +#define CPMU_FORMAT_ATTR(_name, _format)\
> + (&((struct dev_ext_attribute[]) { \
> + { \
> + .attr = __ATTR(_name, 0444, \
> + cpmu_format_sysfs_show, NULL), \
> + .var = (void *)_format \
> + } \
> + })[0].attr.attr)
> +
> +enum {
> + cpmu_mask_attr,
> + cpmu_gid_attr,
> + cpmu_vid_attr,
> + cpmu_threshold_attr,
> + cpmu_invert_attr,
> + cpmu_edge_attr,
> + cpmu_hdm_filter_en_attr,
> + cpmu_hdm_attr,
> +};
> +
> +static struct attribute *cpmu_format_attr[] = {
> + [cpmu_mask_attr] = CPMU_FORMAT_ATTR(mask, "config:0-31"),
> + [cpmu_gid_attr] = CPMU_FORMAT_ATTR(gid, "config:32-47"),
> + [cpmu_vid_attr] = CPMU_FORMAT_ATTR(vid, "config:48-63"),
> + [cpmu_threshold_attr] = CPMU_FORMAT_ATTR(threshold, "config1:0-15"),
> + [cpmu_invert_attr] = CPMU_FORMAT_ATTR(invert, "config1:16"),
> + [cpmu_edge_attr] = CPMU_FORMAT_ATTR(edge, "config1:17"),
> + [cpmu_hdm_filter_en_attr] = CPMU_FORMAT_ATTR(hdm_filter_en, "config1:18"),
> + [cpmu_hdm_attr] = CPMU_FORMAT_ATTR(hdm, "config2:0-15"),
> + NULL
> +};
> +
> +static umode_t cpmu_format_is_visible(struct kobject *kobj, struct attribute *attr, int a)
> +{
> + struct device *dev = kobj_to_dev(kobj);
> + struct cpmu_info *info = dev_get_drvdata(dev);
> +
> + /*
> + * Filter capability at the CPMU level, so hide the attributes if the particular
> + * filter is not supported.
> + */
> + if (attr == cpmu_format_attr[cpmu_hdm_filter_en_attr] ||
> + attr == cpmu_format_attr[cpmu_hdm_attr]) {
> + if (info->filter_hdm)
> + return 0444;
> + else
> + return 0;
> + } else {
> + return 0444;
> + }
> +}
> +
> +static const struct attribute_group cpmu_format_group = {
> + .name = "format",
> + .attrs = cpmu_format_attr,
> + .is_visible = cpmu_format_is_visible,
> +};
> +
> +static u32 cpmu_config_get_mask(struct perf_event *event)
> +{
> + return FIELD_GET(GENMASK(31, 0), event->attr.config);
> +}
> +
> +static u16 cpmu_config_get_gid(struct perf_event *event)
> +{
> + return FIELD_GET(GENMASK(47, 32), event->attr.config);
> +}
> +
> +static u16 cpmu_config_get_vid(struct perf_event *event)
> +{
> + return FIELD_GET(GENMASK(63, 48), event->attr.config);
> +}
> +
> +static u8 cpmu_config1_get_threshold(struct perf_event *event)
> +{
> + return FIELD_GET(GENMASK(15, 0), event->attr.config1);
> +}
> +
> +static bool cpmu_config1_get_invert(struct perf_event *event)
> +{
> + return FIELD_GET(BIT(16), event->attr.config1);
> +}
> +
> +static bool cpmu_config1_get_edge(struct perf_event *event)
> +{
> + return FIELD_GET(BIT(17), event->attr.config1);
> +}
> +
> +/*
> + * CPMU specification allows for 8 filters, each with a 16 bit value...
> + * So we need to find 8x16bits to store it in.
> + * So far only one filter has been defined - HDM Decoder.
> + * As the value used for disable is 0xffff, a separate enable switch
> + * is needed.
> + */
> +
> +static bool cpmu_config1_hdm_filter_en(struct perf_event *event)
> +{
> + return FIELD_GET(BIT(14), event->attr.config1);
> +}
> +
> +static u16 cpmu_config2_get_hdm_decoder(struct perf_event *event)
> +{
> + return FIELD_GET(GENMASK(15, 0), event->attr.config2);
> +}
> +
> +static ssize_t cpumask_show(struct device *dev, struct device_attribute *attr,
> + char *buf)
> +{
> + struct cpmu_info *info = dev_get_drvdata(dev);
> +
> + return cpumap_print_to_pagebuf(true, buf, cpumask_of(info->on_cpu));
> +}
> +static DEVICE_ATTR_RO(cpumask);
> +
> +static struct attribute *cpmu_cpumask_attrs[] = {
> + &dev_attr_cpumask.attr,
> + NULL
> +};
> +
> +static const struct attribute_group cpmu_cpumask_group = {
> + .attrs = cpmu_cpumask_attrs,
> +};
> +
> +static const struct attribute_group *cpmu_attr_groups[] = {
> + &cpmu_events,
> + &cpmu_format_group,
> + &cpmu_cpumask_group,
> + NULL
> +};
> +
> +static int cpmu_event_init(struct perf_event *event)
> +{
> + struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
> +
> + event->cpu = info->on_cpu;
> + /* Top level type sanity check - is this a Hardware Event being requested */
> + if (event->attr.type != event->pmu->type)
> + return -ENOENT;
> +
> + if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
> + return -EOPNOTSUPP;
> + /* TODO: Validation of any filter */
> +
> + return 0;
> +}
> +
> +static void cpmu_pmu_enable(struct pmu *pmu)
> +{
> + struct cpmu_info *info = pmu_to_cpmu_info(pmu);
> + void __iomem *base = info->base;
> + int num;
> +
> + /* We don't have a global enable, but we 'might' have a global freeze which we can use */
> + if (info->freeze_for_enable) {
> + /* Check if something is enabled */
> + for (num = 0; num < info->num_counters; num++) {
> + if (info->hw_events[num])
> + break;
> + }
> + if (num == info->num_counters)
> + return;
> +
> + /* Can assume frozen at this stage */
> + writeq(0, base + CPMU_FREEZE_REG);
> +
> + return;
> + }
> +}
> +
> +static void cpmu_pmu_disable(struct pmu *pmu)
> +{
> + struct cpmu_info *info = pmu_to_cpmu_info(pmu);
> + void __iomem *base = info->base;
> +
> + if (info->freeze_for_enable) {
> + /*
> + * Whilst bits above number of counters are RsvdZ
> + * they are unlikely to be repurposed given
> + * number of counters is allowed be 64 leaving
> + * no reserved bits. Hence this is only slightly
> + * naughty.
> + */
> + writeq(GENMASK(63, 0), base + CPMU_FREEZE_REG);
> + return;
> + }
> +}
> +
> +static int cpmu_find_matching_event_cap(struct cpmu_info *info,
> + struct perf_event *event)
> +{
> + struct cpmu_event *cpmu_ev;
> + u16 gid = cpmu_config_get_gid(event);
> + u16 vid = cpmu_config_get_vid(event);
> + u32 mask = cpmu_config_get_mask(event);
> +
> + list_for_each_entry(cpmu_ev, &info->cpmu_events, node) {
> + if (vid != cpmu_ev->vid || gid != cpmu_ev->gid)
> + continue;
> +
> + if (~cpmu_ev->msk & mask)
> + break;
> + return cpmu_ev->event_idx;
> + }
> +
> + return -EINVAL;
> +}
> +
> +static void cpmu_event_start(struct perf_event *event, int flags)
> +{
> + struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
> + struct hw_perf_event *hwc = &event->hw;
> + void __iomem *base = info->base;
> + u64 cfg;
> + u64 prev_cnt;
> +
> + if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
> + return;
> +
> + WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
> + hwc->state = 0;
> +
> + /*
> + * Currently only hdm filter is defined, this code will
> + * want generalizing when more are defined.
> + */
> + if (info->filter_hdm) {
> + if (cpmu_config1_hdm_filter_en(event))
> + cfg = cpmu_config2_get_hdm_decoder(event);
> +
> + else
> + cfg = GENMASK(15, 0);
> + writeq(cfg, base + CPMU_FILTER_CFG_REG(hwc->idx, 0));
> + }
> +
> + cfg = readq(base + CPMU_COUNTER_CFG_REG(hwc->idx));
> + cfg |= FIELD_PREP(CPMU_COUNTER_CFG_INT_ON_OVRFLW, 1);
> + cfg |= FIELD_PREP(CPMU_COUNTER_CFG_ENABLE, 1);
> + cfg |= FIELD_PREP(CPMU_COUNTER_CFG_EDGE, cpmu_config1_get_edge(event) ? 1 : 0);
> + cfg |= FIELD_PREP(CPMU_COUNTER_CFG_INVERT, cpmu_config1_get_invert(event) ? 1 : 0);
> +
> + /* Fixed purpose counters have next two fields RO */
> + if (test_bit(hwc->idx, info->conf_counter_bm)) {
> + int event_idx = cpmu_find_matching_event_cap(info, event);
> +
> + if (event_idx < 0) {
> + dev_dbg(info->pmu.dev, "Could not find matching event capability\n");
> + return;
> + }
> + cfg |= FIELD_PREP(CPMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK, event_idx);
> + cfg |= FIELD_PREP(CPMU_COUNTER_CFG_EVENTS_MSK, cpmu_config_get_mask(event));
> + }
> + cfg &= ~CPMU_COUNTER_CFG_THRESHOLD_MSK;
> + /*
> + * For events that generate only 1 count per clock the CXL 3.0 spec
> + * states the threshold shall be set to 1 but if set to 0 it will
> + * count the raw value anwyay?
> + * There is definition ofwhat events will count multiple per cycle
Missing space between "of" and "what".
> + * and hence to which non 1 values of threshold can apply.
> + * (CXL 3.0 8.2.7.2.1 Counter Configuration - threshold field definition)
> + */
> + cfg |= FIELD_PREP(CPMU_COUNTER_CFG_THRESHOLD_MSK,
> + cpmu_config1_get_threshold(event));
> + writeq(cfg, base + CPMU_COUNTER_CFG_REG(hwc->idx));
> +
> + local64_set(&hwc->prev_count, 0);
> + writeq(0, base + CPMU_COUNTER_REG(hwc->idx));
> +
> + if (flags & PERF_EF_RELOAD) {
> + prev_cnt = local64_read(&hwc->prev_count);
> + writeq(prev_cnt, base + CPMU_COUNTER_REG(hwc->idx));
> + }
> +
> + perf_event_update_userpage(event);
> +}
> +
> +static u64 cpmu_read_counter(struct perf_event *event)
> +{
> + struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
> + void __iomem *base = info->base;
> +
> + return readq(base + CPMU_COUNTER_REG(event->hw.idx));
> +}
> +
> +static void __cpmu_read(struct perf_event *event, bool overflow)
> +{
> + struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
> + struct hw_perf_event *hwc = &event->hw;
> + u64 new_cnt, prev_cnt, delta;
> +
> + do {
> + prev_cnt = local64_read(&hwc->prev_count);
> + new_cnt = cpmu_read_counter(event);
> + } while (local64_cmpxchg(&hwc->prev_count, prev_cnt, new_cnt) != prev_cnt);
> +
> + /*
> + * If we know an overflow occur then take that into account.
> + * Note counter is not reset as that would lose events
> + */
> + delta = (new_cnt - prev_cnt) & GENMASK(info->counter_width - 1, 0);
> + if (overflow && delta < GENMASK(info->counter_width - 1, 0))
> + delta += (1UL << info->counter_width);
> +
> + local64_add(delta, &event->count);
> +}
> +
> +static void cpmu_read(struct perf_event *event)
> +{
> + __cpmu_read(event, false);
> +}
> +
> +static void cpmu_event_stop(struct perf_event *event, int flags)
> +{
> + struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
> + void __iomem *base = info->base;
> + struct hw_perf_event *hwc = &event->hw;
> + u64 cfg;
> +
> + cpmu_read(event);
> + WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
> + hwc->state |= PERF_HES_STOPPED;
> +
> + cfg = readq(base + CPMU_COUNTER_CFG_REG(hwc->idx));
> + cfg &= ~(FIELD_PREP(CPMU_COUNTER_CFG_INT_ON_OVRFLW, 1) |
> + FIELD_PREP(CPMU_COUNTER_CFG_ENABLE, 1));
> + writeq(cfg, base + CPMU_COUNTER_CFG_REG(hwc->idx));
> +
> + if (hwc->state & PERF_HES_UPTODATE)
> + return;
> +
> + hwc->state |= PERF_HES_UPTODATE;
> +}
> +
> +static int cpmu_get_event_idx(struct perf_event *event)
> +{
> + struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
> + struct cpmu_event *cpmu_ev;
> + u32 mask;
> + u16 gid, vid;
> +
> + vid = cpmu_config_get_vid(event);
> + gid = cpmu_config_get_gid(event);
> + mask = cpmu_config_get_mask(event);
> +
> + list_for_each_entry(cpmu_ev, &info->cpmu_events, node) {
> + int idx;
> +
> + if (vid != cpmu_ev->vid || gid != cpmu_ev->gid)
> + continue;
> +
> + /*
> + * For fixed counters, must match exactly.
> + * No need to support duplicates so if first in use
> + * return an error.
> + */
> + if (!cpmu_ev->configurable) {
> + if (cpmu_ev->msk != mask)
> + continue;
> + if (info->hw_events[cpmu_ev->counter_idx])
> + return -EINVAL;
> +
> + return cpmu_ev->counter_idx;
> + }
> +
> + /* Requested mask needs to be subset of available */
> + if (~cpmu_ev->msk & mask)
> + continue;
> +
> + /* Found the group, now see if any configurable counters left */
> + for_each_set_bit(idx, info->conf_counter_bm, 64) {
> + if (!info->hw_events[idx])
> + return idx;
> + }
> + }
> +
> + return -EINVAL;
> +}
> +
> +/*
> + * Reset ensures no possibility of any information leaking to wrong
> + * counter. Note that all fields written during start()
> + */
> +static void cpmu_reset_counter(struct cpmu_info *info, int idx)
> +{
> + void __iomem *base = info->base;
> +
> + /* Much of this register is read only */
> + writeq(0, base + CPMU_EVENT_CAP_REG(idx));
> + /* Filters are not per counter, so not reset here */
s/not/no/
DJ
> + writeq(0, base + CPMU_COUNTER_REG(idx));
> +}
> +
> +static int cpmu_event_add(struct perf_event *event, int flags)
> +{
> + struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
> + struct hw_perf_event *hwc = &event->hw;
> + int idx;
> +
> + hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
> +
> + idx = cpmu_get_event_idx(event);
> + if (idx < 0)
> + return idx;
> +
> + hwc->idx = idx;
> + info->hw_events[idx] = event;
> +
> + cpmu_reset_counter(info, idx);
> +
> + if (flags & PERF_EF_START)
> + cpmu_event_start(event, PERF_EF_RELOAD);
> +
> + return 0;
> +}
> +
> +static void cpmu_event_del(struct perf_event *event, int flags)
> +{
> + struct cpmu_info *info = pmu_to_cpmu_info(event->pmu);
> + struct hw_perf_event *hwc = &event->hw;
> +
> + cpmu_event_stop(event, PERF_EF_UPDATE);
> + info->hw_events[hwc->idx] = NULL;
> + perf_event_update_userpage(event);
> +}
> +
> +static irqreturn_t cpmu_irq(int irq, void *data)
> +{
> + struct cpmu_info *info = data;
> + void __iomem *base = info->base;
> + u64 overflowed;
> + DECLARE_BITMAP(overflowedbm, 64);
> + int i;
> +
> + overflowed = readq(base + CPMU_OVERFLOW_REG);
> +
> + /* Interrupt may be shared, so maybe it isn't ours */
> + if (!overflowed)
> + return IRQ_NONE;
> +
> + bitmap_from_arr64(overflowedbm, &overflowed, 64);
> + for_each_set_bit(i, overflowedbm, info->num_counters) {
> + struct perf_event *event = info->hw_events[i];
> +
> + if (!event) {
> + dev_dbg(info->pmu.dev,
> + "overflow but on non enabled counter %d\n", i);
> + continue;
> + }
> +
> + __cpmu_read(event, true);
> + }
> +
> + writeq(overflowed, base + CPMU_OVERFLOW_REG);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int cxl_cpmu_probe(struct device *dev)
> +{
> + struct cxl_cpmu *cpmu = to_cxl_cpmu(dev);
> + struct pci_dev *pdev = to_pci_dev(dev->parent);
> + struct cpmu_info *info;
> + char *irq_name;
> + int rc, irq;
> +
> + info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
> + if (!info)
> + return -ENOMEM;
> +
> + INIT_LIST_HEAD(&info->cpmu_events);
> +
> + info->base = cpmu->base;
> +
> + info->on_cpu = -1;
> + rc = cpmu_parse_caps(dev, info);
> + if (rc)
> + return rc;
> +
> + info->hw_events = devm_kcalloc(dev, sizeof(*info->hw_events),
> + info->num_counters, GFP_KERNEL);
> + if (!info->hw_events)
> + return -ENOMEM;
> +
> + info->pmu = (struct pmu) {
> + .name = dev_name(dev),
> + .module = THIS_MODULE,
> + .event_init = cpmu_event_init,
> + .pmu_enable = cpmu_pmu_enable,
> + .pmu_disable = cpmu_pmu_disable,
> + .add = cpmu_event_add,
> + .del = cpmu_event_del,
> + .start = cpmu_event_start,
> + .stop = cpmu_event_stop,
> + .read = cpmu_read,
> + .task_ctx_nr = perf_invalid_context,
> + .attr_groups = cpmu_attr_groups,
> + .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
> + };
> +
> + if (info->irq <= 0)
> + return -EINVAL;
> +
> +
> + rc = pci_irq_vector(pdev, info->irq);
> + if (rc < 0)
> + return rc;
> + irq = rc;
> +
> + irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_overflow\n", dev_name(dev));
> + if (!irq_name)
> + return -ENOMEM;
> +
> + rc = devm_request_irq(dev, irq, cpmu_irq, IRQF_SHARED, irq_name, info);
> + if (rc)
> + return rc;
> + info->irq = irq;
> +
> + rc = cpuhp_state_add_instance(cpmu_cpuhp_state_num, &info->node);
> + if (rc)
> + return rc;
> +
> + rc = perf_pmu_register(&info->pmu, info->pmu.name, -1);
> + if (rc)
> + return rc;
> +
> + dev_set_drvdata(dev, info);
> +
> + return 0;
> +}
> +
> +static void cxl_cpmu_remove(struct device *dev)
> +{
> + struct cpmu_info *info = dev_get_drvdata(dev);
> +
> + perf_pmu_unregister(&info->pmu);
> + cpuhp_state_remove_instance_nocalls(cpmu_cpuhp_state_num, &info->node);
> +}
> +
> +static struct cxl_driver cxl_cpmu_driver = {
> + .name = "cxl_cpmu",
> + .probe = cxl_cpmu_probe,
> + .remove = cxl_cpmu_remove,
> + .id = CXL_DEVICE_CPMU,
> +};
> +
> +static int cpmu_online_cpu(unsigned int cpu, struct hlist_node *node)
> +{
> + struct cpmu_info *info = hlist_entry_safe(node, struct cpmu_info, node);
> +
> + if (info->on_cpu != -1)
> + return 0;
> +
> + info->on_cpu = cpu;
> + WARN_ON(irq_set_affinity(info->irq, cpumask_of(cpu)));
> +
> + return 0;
> +}
> +
> +static int cpmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
> +{
> + struct cpmu_info *info = hlist_entry_safe(node, struct cpmu_info, node);
> + unsigned int target;
> +
> + if (info->on_cpu != cpu)
> + return 0;
> +
> + info->on_cpu = -1;
> + target = cpumask_first(cpu_online_mask);
> + if (target >= nr_cpu_ids) {
> + dev_err(info->pmu.dev, "Unable to find a suitable CPU\n");
> + return 0;
> + }
> +
> + perf_pmu_migrate_context(&info->pmu, cpu, target);
> + info->on_cpu = target;
> + WARN_ON(irq_set_affinity(info->irq, cpumask_of(target)));
> +
> + return 0;
> +}
> +
> +static __init int cxl_cpmu_init(void)
> +{
> + int rc;
> +
> + rc = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
> + "AP_PERF_CPMU_ONLINE",
> + cpmu_online_cpu, cpmu_offline_cpu);
> + if (rc < 0)
> + return rc;
> + cpmu_cpuhp_state_num = rc;
> +
> + rc = cxl_driver_register(&cxl_cpmu_driver);
> + if (rc)
> + cpuhp_remove_multi_state(cpmu_cpuhp_state_num);
> +
> + return rc;
> +}
> +
> +static __exit void cxl_cpmu_exit(void)
> +{
> + cxl_driver_unregister(&cxl_cpmu_driver);
> + cpuhp_remove_multi_state(cpmu_cpuhp_state_num);
> +}
> +
> +MODULE_LICENSE("GPL");
> +MODULE_IMPORT_NS(CXL);
> +module_init(cxl_cpmu_init);
> +module_exit(cxl_cpmu_exit);
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RFC PATCH v2 1/4] cxl: Add function to count regblocks of a given type.
2022-08-24 10:36 ` [RFC PATCH v2 1/4] cxl: Add function to count regblocks of a given type Jonathan Cameron
@ 2022-09-22 20:19 ` Dave Jiang
0 siblings, 0 replies; 12+ messages in thread
From: Dave Jiang @ 2022-09-22 20:19 UTC (permalink / raw)
To: Jonathan Cameron, linux-cxl, Dan Williams, Alison Schofield,
Vishal Verma, Ira Weiny, Ben Widawsky, linux-perf-users,
Will Deacon, Mark Rutland
Cc: linuxarm
On 8/24/2022 3:36 AM, Jonathan Cameron wrote:
> Until the recently release CXL 3.0 specification, there
> was only ever one instance of any given register block pointed
> to by the Register Block Locator DVSEC. Now, the specification allows
> for multiple CXL PMU instances, each with their own register block.
>
> To enable this add an index parameter to cxl_find_regblock()
> and use that to implement cxl_count_regblock().
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> drivers/cxl/core/pci.c | 2 +-
> drivers/cxl/core/port.c | 2 +-
> drivers/cxl/core/regs.c | 35 ++++++++++++++++++++++++++++++++---
> drivers/cxl/cxl.h | 3 ++-
> drivers/cxl/pci.c | 2 +-
> 5 files changed, 37 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 9240df53ed87..f29cdc9df330 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -49,7 +49,7 @@ static int match_add_dports(struct pci_dev *pdev, void *data)
> &lnkcap))
> return 0;
>
> - rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
> + rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map, 0);
> if (rc)
> dev_dbg(&port->dev, "failed to find component registers\n");
>
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index bffde862de0b..1629c7a4033f 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -1235,7 +1235,7 @@ static resource_size_t find_component_registers(struct device *dev)
>
> pdev = to_pci_dev(dev);
>
> - cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
> + cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map, 0);
> return cxl_regmap_to_base(pdev, &map);
> }
>
> diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
> index 39a129c57d40..2f651211d120 100644
> --- a/drivers/cxl/core/regs.c
> +++ b/drivers/cxl/core/regs.c
> @@ -262,6 +262,7 @@ static void cxl_decode_regblock(u32 reg_lo, u32 reg_hi,
> * @pdev: The CXL PCI device to enumerate.
> * @type: Register Block Indicator id
> * @map: Enumeration output, clobbered on error
> + * @index: Index into which particular instance of a regblock we want.
> *
> * Return: 0 if register block enumerated, negative error code otherwise
> *
> @@ -269,9 +270,10 @@ static void cxl_decode_regblock(u32 reg_lo, u32 reg_hi,
> * by @type.
> */
> int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
> - struct cxl_register_map *map)
> + struct cxl_register_map *map, int index)
> {
> u32 regloc_size, regblocks;
> + int instance = 0;
> int regloc, i;
>
> map->block_offset = U64_MAX;
> @@ -294,11 +296,38 @@ int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
>
> cxl_decode_regblock(reg_lo, reg_hi, map);
>
> - if (map->reg_type == type)
> - return 0;
> + if (map->reg_type == type) {
> + if (index == instance)
> + return 0;
> + instance++;
> + }
> }
>
> map->block_offset = U64_MAX;
> return -ENODEV;
> }
> EXPORT_SYMBOL_NS_GPL(cxl_find_regblock, CXL);
> +
> +/**
> + * cxl_count_regblock() - Count instances of a given regblock type.
> + * @pdev: The CXL PCI device to enumerate.
> + * @type: Register Block Indicator id
> + *
> + * Some regblocks may be repeated. Count how many instances.
> + *
> + * Return: count of matching regblocks.
> + */
> +int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type)
> +{
> + struct cxl_register_map map;
> + int rc, count = 0;
> +
> + while (1) {
> + rc = cxl_find_regblock(pdev, type, &map, count);
> + if (rc)
> + return count;
> + count++;
> + }
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_count_regblock, CXL);
> +
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index f680450f0b16..5a1bcdbda654 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -216,8 +216,9 @@ int cxl_map_device_regs(struct pci_dev *pdev,
> struct cxl_register_map *map);
>
> enum cxl_regloc_type;
> +int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type);
> int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
> - struct cxl_register_map *map);
> + struct cxl_register_map *map, int index);
> void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
> resource_size_t length);
>
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index faeb5d9d7a7a..1758380247ec 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -373,7 +373,7 @@ static int cxl_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
> {
> int rc;
>
> - rc = cxl_find_regblock(pdev, type, map);
> + rc = cxl_find_regblock(pdev, type, map, 0);
> if (rc)
> return rc;
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RFC PATCH v2 4/4] docs: perf: Minimal introduction the the CXL PMU device and driver.
2022-08-24 10:36 ` [RFC PATCH v2 4/4] docs: perf: Minimal introduction the the CXL PMU device and driver Jonathan Cameron
@ 2022-09-22 20:41 ` Dave Jiang
0 siblings, 0 replies; 12+ messages in thread
From: Dave Jiang @ 2022-09-22 20:41 UTC (permalink / raw)
To: Jonathan Cameron, linux-cxl, Dan Williams, Alison Schofield,
Vishal Verma, Ira Weiny, Ben Widawsky, linux-perf-users,
Will Deacon, Mark Rutland
Cc: linuxarm
On 8/24/2022 3:36 AM, Jonathan Cameron wrote:
> Very basic introduction to the device and the current driver support
> provided. I expect to expand on this in future versions of this patch
> set.
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> --
> RFC:
> - I'll post separately about this shortly, but it seems very odd
> to me that there is no way to assign a parent to an event_sources
> device. As a result we get the messy approach of playing match
> the name to figure out what the CPMU instance is connected to.
> ---
> Documentation/admin-guide/perf/cxl.rst | 60 ++++++++++++++++++++++++
> Documentation/admin-guide/perf/index.rst | 1 +
> 2 files changed, 61 insertions(+)
>
> diff --git a/Documentation/admin-guide/perf/cxl.rst b/Documentation/admin-guide/perf/cxl.rst
> new file mode 100644
> index 000000000000..6ffc057591fb
> --- /dev/null
> +++ b/Documentation/admin-guide/perf/cxl.rst
> @@ -0,0 +1,60 @@
> +======================================
> +CXL Performance Monitoring Unit (CPMU)
> +======================================
> +
> +The CXL rev 3.0 specification provides a definition of CXL Performance
> +Monitoring Unit in section 13.2: Performance Monitoring.
> +
> +CXL components (e.g. Root Port, Switch Upstream Port, End Point) may have
> +any number of CPMU instances. CPMU capabilities are fully discoverable from
> +the devices. The specification provides event definitions for all CXL protocol
> +message types and a set of additional events for things commonly counted on
> +CXL devices (e.g. DRAM events).
> +
> +CPMU driver
> +===========
> +
> +The CPMU driver register a perf PMU with the name cpmu<id> on the CXL bus.
> +
> + /sys/bus/cxl/device/cpmu<id>
> +
> +The associated PMU is registered as
> +
> + /sys/bus/event_sources/devices/cpmu<id>
> +
> +In common with other CXL bus devices, the id has no specific meaning and the
> +relationship to specific CXL device should be established via the device parent
> +of the device on the CXL bus.
> +
> +PMU driver provides description of available events and filter options in sysfs.
> +
> +The "format" directory describes all formats of the config (event vendor id,
> +group id and mask) config1 (threshold, filter enables) and config2 (filter
> +parameters) fields of the perf_event_attr structure. The "events" directory
> +describes all documented events show in perf list.
"all the documented events shown in perf list."
DJ
> +
> +The events shown in perf list are the most fine grained events with a single
> +bit of the event mask set. More general events may be enable by setting
> +multiple mask bits in config. For example, all Device to Host Read Requests
> +may be captured on a single counter by setting the bits for all of
> +
> +* d2h_req_rdcurr
> +* d2h_req_rdown
> +* d2h_req_rdshared
> +* d2h_req_rdany
> +* d2h_req_rdownnodata
> +
> +Example of usage::
> +
> + $#perf list
> + cpmu0/clock_ticks/ [Kernel PMU event]
> + cpmu0/d2h_req_itomwr/ [Kernel PMU event]
> + cpmu0/d2h_req_rdany/ [Kernel PMU event]
> + cpmu0/d2h_req_rdcurr/ [Kernel PMU event]
> + -----------------------------------------------------------
> +
> + $# perf stat -e cpmu0/clock_ticks/ -e cpmu0/d2h_req_itowrm/
> +
> +The driver does not support sampling. So "perf record" and attaching to
> +a task are unsupported.
> +
> diff --git a/Documentation/admin-guide/perf/index.rst b/Documentation/admin-guide/perf/index.rst
> index 9c9ece88ce53..f12cfe76e1f0 100644
> --- a/Documentation/admin-guide/perf/index.rst
> +++ b/Documentation/admin-guide/perf/index.rst
> @@ -18,3 +18,4 @@ Performance monitor support
> xgene-pmu
> arm_dsu_pmu
> thunderx2-pmu
> + cxl
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RFC PATCH v2 2/4] cxl/pci: Find and register CXL PMU devices
2022-09-01 22:36 ` Dave Jiang
@ 2022-10-18 11:19 ` Jonathan Cameron
2022-10-21 17:26 ` Dave Jiang
0 siblings, 1 reply; 12+ messages in thread
From: Jonathan Cameron @ 2022-10-18 11:19 UTC (permalink / raw)
To: Dave Jiang
Cc: linux-cxl, Dan Williams, Alison Schofield, Vishal Verma,
Ira Weiny, Ben Widawsky, linux-perf-users, Will Deacon,
Mark Rutland, linuxarm
On Thu, 1 Sep 2022 15:36:23 -0700
Dave Jiang <dave.jiang@intel.com> wrote:
> On 8/24/2022 3:36 AM, Jonathan Cameron wrote:
> > CXL PMU devices can be found from entries in the Register
> > Locator DVSEC.
> >
> > In order to register the minimum number of IRQ vectors necessary
> > to support all CPMUs found, separate the registration into two
> > steps. First find the devices, and query the IRQs used and then
> > register the devices. Between these two steps, request the
> > IRQ vectors necessary and enable bus master support.
> >
> > Future IRQ users for CXL type 3 devices (e.g. DOEs) will need to
> > follow a similar pattern the number of vectors necessary is known
> > before any parts of the driver stack rely on their availability.
> >
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> >
> > +static int cxl_alloc_irq_vectors(struct cxl_dev_state *cxlds, int vectors)
> > +{
> > + struct device *dev = cxlds->dev;
> > + struct pci_dev *pdev = to_pci_dev(dev);
> > + int rc;
> > +
> > + rc = pci_alloc_irq_vectors(pdev, vectors, vectors,
> > + PCI_IRQ_MSI | PCI_IRQ_MSIX);
> > + if (rc < 0)
> > + return rc;
> > + if (rc != vectors) {
>
> I don't think you'll hit here since you passed in vectors for min and
> max. You'll get -ENOSPC and return from the earlier check.
>
> https://elixir.bootlin.com/linux/v6.0-rc3/source/drivers/pci/msi/msi.c#L1005
>
> DJ
>
Good point. This also applies to the version of the same function in
Davidlohr's patch set, so I've cut and paste your comment to there.
Jonathan
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RFC PATCH v2 3/4] cxl: CXL Performance Monitoring Unit driver
2022-09-22 20:19 ` Dave Jiang
@ 2022-10-18 11:26 ` Jonathan Cameron
0 siblings, 0 replies; 12+ messages in thread
From: Jonathan Cameron @ 2022-10-18 11:26 UTC (permalink / raw)
To: Dave Jiang
Cc: linux-cxl, Dan Williams, Alison Schofield, Vishal Verma,
Ira Weiny, Ben Widawsky, linux-perf-users, Will Deacon,
Mark Rutland, linuxarm
On Thu, 22 Sep 2022 13:19:06 -0700
Dave Jiang <dave.jiang@intel.com> wrote:
> On 8/24/2022 3:36 AM, Jonathan Cameron wrote:
> > CXL rev 3.0 introduces a standard performance monitoring hardware
> > block to CXL. Instances are discovered using CXL Register Locator DVSEC
> > entries. Each CXL component may have multiple PMUs.
> >
> > This initial driver supports on a subset of types of counter.
> > It support counters that are either fixed or configurable, but requires
> > that they support the ability to freeze and write value whilst frozen.
> >
> > Development done with QEMU model which will be posted shortly.
> >
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Besides couple nits in comments below, Reviewed-by: Dave Jiang
> <dave.jiang@intel.com>
Thanks,
> >> > +/*
> > + * Reset ensures no possibility of any information leaking to wrong
> > + * counter. Note that all fields written during start()
> > + */
> > +static void cpmu_reset_counter(struct cpmu_info *info, int idx)
> > +{
> > + void __iomem *base = info->base;
> > +
> > + /* Much of this register is read only */
> > + writeq(0, base + CPMU_EVENT_CAP_REG(idx));
> > + /* Filters are not per counter, so not reset here */
>
> s/not/no/
Good point. I went with 'so do not reset here'
I also did a scrub for consistent punctuation of those comments
that were full sentences.
>
> DJ
>
> > + writeq(0, base + CPMU_COUNTER_REG(idx));
> > +}
> > +
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RFC PATCH v2 2/4] cxl/pci: Find and register CXL PMU devices
2022-10-18 11:19 ` Jonathan Cameron
@ 2022-10-21 17:26 ` Dave Jiang
0 siblings, 0 replies; 12+ messages in thread
From: Dave Jiang @ 2022-10-21 17:26 UTC (permalink / raw)
To: Jonathan Cameron
Cc: linux-cxl, Dan Williams, Alison Schofield, Vishal Verma,
Ira Weiny, Ben Widawsky, linux-perf-users, Will Deacon,
Mark Rutland, linuxarm
On 10/18/2022 4:19 AM, Jonathan Cameron wrote:
> On Thu, 1 Sep 2022 15:36:23 -0700
> Dave Jiang <dave.jiang@intel.com> wrote:
>
>> On 8/24/2022 3:36 AM, Jonathan Cameron wrote:
>>> CXL PMU devices can be found from entries in the Register
>>> Locator DVSEC.
>>>
>>> In order to register the minimum number of IRQ vectors necessary
>>> to support all CPMUs found, separate the registration into two
>>> steps. First find the devices, and query the IRQs used and then
>>> register the devices. Between these two steps, request the
>>> IRQ vectors necessary and enable bus master support.
>>>
>>> Future IRQ users for CXL type 3 devices (e.g. DOEs) will need to
>>> follow a similar pattern the number of vectors necessary is known
>>> before any parts of the driver stack rely on their availability.
>>>
>>> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>>>
>
>>> +static int cxl_alloc_irq_vectors(struct cxl_dev_state *cxlds, int vectors)
>>> +{
>>> + struct device *dev = cxlds->dev;
>>> + struct pci_dev *pdev = to_pci_dev(dev);
>>> + int rc;
>>> +
>>> + rc = pci_alloc_irq_vectors(pdev, vectors, vectors,
>>> + PCI_IRQ_MSI | PCI_IRQ_MSIX);
>>> + if (rc < 0)
>>> + return rc;
>>> + if (rc != vectors) {
>> I don't think you'll hit here since you passed in vectors for min and
>> max. You'll get -ENOSPC and return from the earlier check.
>>
>> https://elixir.bootlin.com/linux/v6.0-rc3/source/drivers/pci/msi/msi.c#L1005
>>
>> DJ
>>
> Good point. This also applies to the version of the same function in
> Davidlohr's patch set, so I've cut and paste your comment to there.
Somehow I totally missed that reviewing his set. Ooops. Thanks!
>
> Jonathan
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-10-21 17:26 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-08-24 10:36 [RFC PATCH v2 0/4] CXL 3.0 Performance Monitoring Unit support Jonathan Cameron
2022-08-24 10:36 ` [RFC PATCH v2 1/4] cxl: Add function to count regblocks of a given type Jonathan Cameron
2022-09-22 20:19 ` Dave Jiang
2022-08-24 10:36 ` [RFC PATCH v2 2/4] cxl/pci: Find and register CXL PMU devices Jonathan Cameron
2022-09-01 22:36 ` Dave Jiang
2022-10-18 11:19 ` Jonathan Cameron
2022-10-21 17:26 ` Dave Jiang
2022-08-24 10:36 ` [RFC PATCH v2 3/4] cxl: CXL Performance Monitoring Unit driver Jonathan Cameron
2022-09-22 20:19 ` Dave Jiang
2022-10-18 11:26 ` Jonathan Cameron
2022-08-24 10:36 ` [RFC PATCH v2 4/4] docs: perf: Minimal introduction the the CXL PMU device and driver Jonathan Cameron
2022-09-22 20:41 ` Dave Jiang
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