From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Roger Lu <roger.lu@mediatek.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Enric Balletbo Serra <eballetbo@gmail.com>,
Kevin Hilman <khilman@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Nicolas Boichat <drinkcat@google.com>,
Stephen Boyd <sboyd@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>
Cc: Fan Chen <fan.chen@mediatek.com>,
HenryC Chen <HenryC.Chen@mediatek.com>,
YT Lee <yt.lee@mediatek.com>,
Xiaoqing Liu <Xiaoqing.Liu@mediatek.com>,
Charles Yang <Charles.Yang@mediatek.com>,
Angus Lin <Angus.Lin@mediatek.com>,
Mark Rutland <mark.rutland@arm.com>, Nishanth Menon <nm@ti.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org,
Project_Global_Chrome_Upstream_Group@mediatek.com,
Guenter Roeck <linux@roeck-us.net>
Subject: Re: [PATCH v21 7/8] arm64: dts: mt8192: add svs device information
Date: Fri, 7 Jan 2022 15:33:49 +0100 [thread overview]
Message-ID: <010f9b6a-d6bf-b27a-cb2d-c5fd181c3ac7@collabora.com> (raw)
In-Reply-To: <20220107095200.4389-8-roger.lu@mediatek.com>
Il 07/01/22 10:51, Roger Lu ha scritto:
> Add compitable/reg/irq/clock/efuse/reset setting in svs node.
Typo: compitable => compatible
.. also, you're not only adding the svs node, but also efuse: please add that
information in the commit description.
>
> Signed-off-by: Roger Lu <roger.lu@mediatek.com>
This patch seems to not apply on top of the current linux-next, can you please
rebase it? That would resolve issues with this series and would be picked sooner.
Apart from that...
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 39 ++++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index c7c7d4e017ae..c111e26489dd 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -9,6 +9,8 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> +#include <dt-bindings/reset/ti-syscon.h>
> +
>
> / {
> compatible = "mediatek,mt8192";
> @@ -268,6 +270,14 @@
> compatible = "mediatek,mt8192-infracfg", "syscon";
> reg = <0 0x10001000 0 0x1000>;
> #clock-cells = <1>;
> +
> + infracfg_rst: reset-controller {
> + compatible = "mediatek,infra-reset", "ti,syscon-reset";
> + #reset-cells = <1>;
> + ti,reset-bits = <
> + 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: svs */
> + >;
> + };
> };
>
> pericfg: syscon@10003000 {
> @@ -362,6 +372,20 @@
> status = "disabled";
> };
>
> + svs: svs@1100b000 {
> + compatible = "mediatek,mt8192-svs";
> + reg = <0 0x1100b000 0 0x1000>;
> + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&infracfg CLK_INFRA_THERM>;
> + clock-names = "main";
> + nvmem-cells = <&svs_calibration>,
> + <&lvts_e_data1>;
> + nvmem-cell-names = "svs-calibration-data",
> + "t-calibration-data";
> + resets = <&infracfg_rst 0>;
> + reset-names = "svs_rst";
> + };
> +
> spi1: spi@11010000 {
> compatible = "mediatek,mt8192-spi",
> "mediatek,mt6765-spi";
> @@ -479,6 +503,21 @@
> #clock-cells = <1>;
> };
>
> + efuse: efuse@11c10000 {
> + compatible = "mediatek,efuse";
> + reg = <0 0x11c10000 0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + lvts_e_data1: data1@1c0 {
> + reg = <0x1c0 0x58>;
> + };
> +
> + svs_calibration: calib@580 {
> + reg = <0x580 0x68>;
> + };
> + };
> +
> i2c3: i2c3@11cb0000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11cb0000 0 0x1000>,
>
--
AngeloGioacchino Del Regno
Software Engineer
Collabora Ltd.
Platinum Building, St John's Innovation Park, Cambridge CB4 0DS, UK
Registered in England & Wales, no. 5513718
next prev parent reply other threads:[~2022-01-07 14:34 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-07 9:51 [PATCH v21 0/8] soc: mediatek: SVS: introduce MTK SVS engine Roger Lu
2022-01-07 9:51 ` [PATCH v21 1/8] dt-bindings: soc: mediatek: add mtk svs dt-bindings Roger Lu
2022-01-07 19:01 ` Rob Herring
2022-01-07 9:51 ` [PATCH v21 2/8] arm64: dts: mt8183: add svs device information Roger Lu
2022-01-07 14:33 ` AngeloGioacchino Del Regno
2022-01-07 9:51 ` [PATCH v21 3/8] soc: mediatek: SVS: introduce MTK SVS engine Roger Lu
2022-01-07 14:33 ` AngeloGioacchino Del Regno
2022-01-24 6:39 ` Roger Lu
2022-01-07 9:51 ` [PATCH v21 4/8] soc: mediatek: SVS: add monitor mode Roger Lu
2022-01-07 14:34 ` AngeloGioacchino Del Regno
2022-01-24 7:28 ` Roger Lu
2022-01-07 9:51 ` [PATCH v21 5/8] soc: mediatek: SVS: add debug commands Roger Lu
2022-01-07 14:34 ` AngeloGioacchino Del Regno
2022-01-24 10:40 ` Roger Lu
2022-01-07 9:51 ` [PATCH v21 6/8] dt-bindings: soc: mediatek: add mt8192 svs dt-bindings Roger Lu
2022-01-12 1:48 ` Rob Herring
2022-01-07 9:51 ` [PATCH v21 7/8] arm64: dts: mt8192: add svs device information Roger Lu
2022-01-07 14:33 ` AngeloGioacchino Del Regno [this message]
2022-01-24 10:48 ` Roger Lu
2022-01-24 11:49 ` AngeloGioacchino Del Regno
2022-01-07 9:52 ` [PATCH v21 8/8] soc: mediatek: SVS: add mt8192 SVS GPU driver Roger Lu
2022-01-07 14:33 ` AngeloGioacchino Del Regno
2022-01-26 7:49 ` Roger Lu
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