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From: Roger Lu <roger.lu@mediatek.com>
To: AngeloGioacchino Del Regno 
	<angelogioacchino.delregno@collabora.com>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Enric Balletbo Serra <eballetbo@gmail.com>,
	Kevin Hilman <khilman@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Nicolas Boichat <drinkcat@google.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>
Cc: Fan Chen <fan.chen@mediatek.com>,
	HenryC Chen <HenryC.Chen@mediatek.com>,
	YT Lee <yt.lee@mediatek.com>,
	Xiaoqing Liu <Xiaoqing.Liu@mediatek.com>,
	Charles Yang <Charles.Yang@mediatek.com>,
	Angus Lin <Angus.Lin@mediatek.com>,
	Mark Rutland <mark.rutland@arm.com>, Nishanth Menon <nm@ti.com>,
	<devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <linux-pm@vger.kernel.org>,
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	Guenter Roeck <linux@roeck-us.net>
Subject: Re: [PATCH v21 3/8] soc: mediatek: SVS: introduce MTK SVS engine
Date: Mon, 24 Jan 2022 14:39:34 +0800	[thread overview]
Message-ID: <dc84332f190a8be7d5b004fc4d2a2c1341f9a357.camel@mediatek.com> (raw)
In-Reply-To: <63d8884d-d02d-53f9-8524-4a074ca5bfea@collabora.com>

Hi AngeloGioacchino,

Sorry for the late reply and thanks for the advice.

On Fri, 2022-01-07 at 15:33 +0100, AngeloGioacchino Del Regno wrote:
> Il 07/01/22 10:51, Roger Lu ha scritto:
> > The Smart Voltage Scaling(SVS) engine is a piece of hardware
> > which calculates suitable SVS bank voltages to OPP voltage table.
> > Then, DVFS driver could apply those SVS bank voltages to PMIC/Buck
> > when receiving OPP_EVENT_ADJUST_VOLTAGE.
> > 
> > Signed-off-by: Roger Lu <roger.lu@mediatek.com>
> > ---
> >   drivers/soc/mediatek/Kconfig   |   10 +
> >   drivers/soc/mediatek/Makefile  |    1 +
> >   drivers/soc/mediatek/mtk-svs.c | 1446 ++++++++++++++++++++++++++++++++
> >   3 files changed, 1457 insertions(+)
> >   create mode 100644 drivers/soc/mediatek/mtk-svs.c

[snip]

> > +
> > +struct svs_platform_data {
> > +	char *name;
> > +	struct svs_bank *banks;
> > +	bool (*efuse_parsing)(struct svs_platform *svsp);
> > +	unsigned long irqflags;
> > +	const u32 *regs;
> > +	u32 bank_max;
> > +	int (*probe)(struct svs_platform *svsp);
> > +};
> > +
> 
> Please move the definition of struct svs_platform_data at the beginning of
> the file for increased readability.

Okay. I'll move them at the beginning of the file in the next patch.

> 
> With that done,
> 
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>


  reply	other threads:[~2022-01-24  6:39 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-07  9:51 [PATCH v21 0/8] soc: mediatek: SVS: introduce MTK SVS engine Roger Lu
2022-01-07  9:51 ` [PATCH v21 1/8] dt-bindings: soc: mediatek: add mtk svs dt-bindings Roger Lu
2022-01-07 19:01   ` Rob Herring
2022-01-07  9:51 ` [PATCH v21 2/8] arm64: dts: mt8183: add svs device information Roger Lu
2022-01-07 14:33   ` AngeloGioacchino Del Regno
2022-01-07  9:51 ` [PATCH v21 3/8] soc: mediatek: SVS: introduce MTK SVS engine Roger Lu
2022-01-07 14:33   ` AngeloGioacchino Del Regno
2022-01-24  6:39     ` Roger Lu [this message]
2022-01-07  9:51 ` [PATCH v21 4/8] soc: mediatek: SVS: add monitor mode Roger Lu
2022-01-07 14:34   ` AngeloGioacchino Del Regno
2022-01-24  7:28     ` Roger Lu
2022-01-07  9:51 ` [PATCH v21 5/8] soc: mediatek: SVS: add debug commands Roger Lu
2022-01-07 14:34   ` AngeloGioacchino Del Regno
2022-01-24 10:40     ` Roger Lu
2022-01-07  9:51 ` [PATCH v21 6/8] dt-bindings: soc: mediatek: add mt8192 svs dt-bindings Roger Lu
2022-01-12  1:48   ` Rob Herring
2022-01-07  9:51 ` [PATCH v21 7/8] arm64: dts: mt8192: add svs device information Roger Lu
2022-01-07 14:33   ` AngeloGioacchino Del Regno
2022-01-24 10:48     ` Roger Lu
2022-01-24 11:49       ` AngeloGioacchino Del Regno
2022-01-07  9:52 ` [PATCH v21 8/8] soc: mediatek: SVS: add mt8192 SVS GPU driver Roger Lu
2022-01-07 14:33   ` AngeloGioacchino Del Regno
2022-01-26  7:49     ` Roger Lu

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