From: <ilialin@codeaurora.org>
To: 'Mark Rutland' <mark.rutland@arm.com>
Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-arm-msm@vger.kernel.org, sboyd@codeaurora.org,
devicetree@vger.kernel.org, will.deacon@arm.com,
rnayak@codeaurora.org, qualcomm-lt@lists.linaro.org,
celster@codeaurora.org, tfinkel@codeaurora.org
Subject: RE: [PATCH 01/10] soc: qcom: Separate kryo l2 accessors from PMU driver
Date: Thu, 4 Jan 2018 13:13:02 +0200 [thread overview]
Message-ID: <027b01d3854c$ff085060$fd18f120$@codeaurora.org> (raw)
In-Reply-To: <20171212140302.au4wart4uhwm7lfq@lakrids.cambridge.arm.com>
This is address in the V2: https://patchwork.kernel.org/patch/10144473/
> -----Original Message-----
> From: Mark Rutland [mailto:mark.rutland@arm.com]
> Sent: Tuesday, December 12, 2017 4:03 PM
> To: Ilia Lin <ilialin@codeaurora.org>
> Cc: linux-clk@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
linux-
> arm-msm@vger.kernel.org; sboyd@codeaurora.org;
> devicetree@vger.kernel.org; will.deacon@arm.com;
> rnayak@codeaurora.org; qualcomm-lt@lists.linaro.org;
> celster@codeaurora.org; tfinkel@codeaurora.org
> Subject: Re: [PATCH 01/10] soc: qcom: Separate kryo l2 accessors from PMU
> driver
>
> Hi,
>
> On Tue, Dec 12, 2017 at 02:31:28PM +0200, Ilia Lin wrote:
> > The driver provides kernel level API for other drivers to access the
> > MSM8996 L2 cache registers.
> > Separating the L2 access code from the PMU driver and making it public
> > to allow other drivers use it.
> > The accesses must be separated with a single spinlock, maintained in
> > this driver.
>
> > -static void set_l2_indirect_reg(u64 reg, u64 val) -{
> > - unsigned long flags;
> > -
> > - raw_spin_lock_irqsave(&l2_access_lock, flags);
> > - write_sysreg_s(reg, L2CPUSRSELR_EL1);
> > - isb();
> > - write_sysreg_s(val, L2CPUSRDR_EL1);
> > - isb();
> > - raw_spin_unlock_irqrestore(&l2_access_lock, flags);
> > -}
>
> > +/**
> > + * set_l2_indirect_reg: write value to an L2 register
> > + * @reg: Address of L2 register.
> > + * @value: Value to be written to register.
> > + *
> > + * Use architecturally required barriers for ordering between system
> > +register
> > + * accesses, and system registers with respect to device memory */
> > +void set_l2_indirect_reg(u64 reg, u64 val) {
> > + unsigned long flags;
> > + mb();
>
> We didn't need this for the PMU driver, so it's unfortuante that it now
has to
> pay the cost.
>
> Can we please factor this mb() into the callers that need it?
>
> > + raw_spin_lock_irqsave(&l2_access_lock, flags);
> > + write_sysreg_s(reg, L2CPUSRSELR_EL1);
> > + isb();
> > + write_sysreg_s(val, L2CPUSRDR_EL1);
> > + isb();
> > + raw_spin_unlock_irqrestore(&l2_access_lock, flags); }
> > +EXPORT_SYMBOL(set_l2_indirect_reg);
>
> [...]
>
> > +#ifdef CONFIG_ARCH_QCOM
> > +void set_l2_indirect_reg(u64 reg_addr, u64 val);
> > +u64 get_l2_indirect_reg(u64 reg_addr); #else static inline void
> > +set_l2_indirect_reg(u32 reg_addr, u32 val) {} static inline u32
> > +get_l2_indirect_reg(u32 reg_addr) {
> > + return 0;
> > +}
> > +#endif
> > +#endif
>
> Are there any drivers that will bne built for !CONFIG_ARCH_QCOM that
> reference this?
>
> It might be better to not have the stub versions, so that we get a
build-error
> if they are erroneously used.
>
> Thannks,
> Mark.
next prev parent reply other threads:[~2018-01-04 11:13 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-12 12:31 [PATCH 00/10] clk: qcom: CPU clock driver for msm8996 Ilia Lin
2017-12-12 12:31 ` [PATCH 01/10] soc: qcom: Separate kryo l2 accessors from PMU driver Ilia Lin
2017-12-12 14:03 ` Mark Rutland
2017-12-22 2:06 ` Stephen Boyd
2018-01-04 11:15 ` ilialin
2018-01-04 11:13 ` ilialin [this message]
2017-12-12 12:31 ` [PATCH 02/10] clk: qcom: Fix .set_rate to handle alpha PLLs w/wo dynamic update Ilia Lin
[not found] ` <1513081897-31612-3-git-send-email-ilialin-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-12-12 15:05 ` Julien Thierry
2018-01-04 11:14 ` ilialin
2017-12-12 12:31 ` [PATCH 03/10] clk: qcom: Make clk_alpha_pll_configure available to modules Ilia Lin
2017-12-12 12:31 ` [PATCH 04/10] clk: qcom: Add CPU clock driver for msm8996 Ilia Lin
2017-12-15 22:35 ` Rob Herring
2018-01-04 11:15 ` ilialin
[not found] ` <1513081897-31612-1-git-send-email-ilialin-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-12-12 12:31 ` [PATCH 05/10] clk: qcom: cpu-8996: Add support to switch to alternate PLL Ilia Lin
2017-12-12 12:31 ` [PATCH 06/10] clk: qcom: cpu-8996: Add support to switch below 600Mhz Ilia Lin
2017-12-12 12:31 ` [PATCH 08/10] clk: qcom: Add ACD path to CPU clock driver for msm8996 Ilia Lin
2017-12-12 12:31 ` [PATCH 07/10] clk: qcom: clk-cpu-8996: Prepare PLLs on probe Ilia Lin
2017-12-12 12:31 ` [PATCH 09/10] DT: QCOM: Add cpufreq-dt to msm8996 Ilia Lin
2017-12-12 12:31 ` [PATCH 10/10] DT: QCOM: Add thermal mitigation " Ilia Lin
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