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From: Shawn Lin <shawn.lin@rock-chips.com>
To: Doug Anderson <dianders@chromium.org>
Cc: shawn.lin@rock-chips.com, Ulf Hansson <ulf.hansson@linaro.org>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Heiko Stuebner <heiko@sntech.de>,
	Rob Herring <robh+dt@kernel.org>,
	Ziyuan Xu <xzy.xu@rock-chips.com>,
	Brian Norris <briannorris@chromium.org>,
	Adrian Hunter <adrian.hunter@intel.com>,
	"open list:ARM/Rockchip SoC..."
	<linux-rockchip@lists.infradead.org>,
	"linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 09/11] phy: rockchip-emmc: Set phyctrl_frqsel based on card clock
Date: Tue, 14 Jun 2016 08:24:43 +0800	[thread overview]
Message-ID: <036b0349-8343-f5de-7215-5a0843ebc6a9@rock-chips.com> (raw)
In-Reply-To: <CAD=FV=VA6vmfzHEOZwAFJvNXRDhPmf+bX-Jw1eFboOdP6kD3dg@mail.gmail.com>

在 2016/6/14 7:05, Doug Anderson 写道:
> Shawn,
>
> On Mon, Jun 13, 2016 at 1:54 AM, Shawn Lin <shawn.lin@rock-chips.com> wrote:
>> On 2016/6/8 6:44, Douglas Anderson wrote:
>>>
>>> The "phyctrl_frqsel" is described in the Arasan datasheet [1] as "the
>>> frequency range of DLL operation".  Although the Rockchip variant of
>>> this PHY has different ranges than the reference Arasan PHY it appears
>>> as if the functionality is similar.  We should set this phyctrl field
>>> properly.
>>>
>>> Note: as per Rockchip engineers, apparently the "phyctrl_frqsel" is
>>> actually only useful in HS200 / HS400 modes even though the DLL itself
>>> it used for some purposes in all modes.  See the discussion in the
>>> earlier change in this series: ("mmc: sdhci-of-arasan: Always power the
>>> PHY off/on when clock changes").  In any case, it shouldn't hurt to set
>>> this always.
>>>
>>> Note that this change should allow boards to run at HS200 / HS400 speed
>>> modes while running at 100 MHz or 150 MHz.  In fact, running HS400 at
>>> 150 MHz (giving 300 MB/s) is the main motivation of this series, since
>>> performance is still good but signal integrity problems are less
>>> prevelant at 150 MHz.
>>
>>
>> Thanks for doing this, but I think we should limit freq if assigning
>> max-frequency from DT more explicitly since the PHY could only support
>> 50/100/150/200M for hs200/400? Otherwise I can't say if the PHY could
>> always work well. i.e if geting 125000000 ... 174999999 , you code make
>> the phyctrl_frqsel to be 150M, so it will be 15% missing of precision
>> for tuning delay element. Ideally, the sample point should be in the
>> middle of window, but I don't know if there is a bad HW design makes
>> the window small enough which need special care about it.
>
> What would you suggest as a valid range, then?
>
>>From the public Arasan datasheet they seem to indicate +/- 15 MHz is
> sane.  Does that sound OK?  Presuming that all of your numbers
> (50/100/150/200) are centers, that means that we could support clock
> rates of:
>
> 35 MHz - 65 MHz
> 85 MHz - 115 MHz
> 135 MHz - 165 MHz
> 185 MHz - 200 MHz
>
>
> So how about if we add a warning for things that are outside of those
> ranges?  ...except no warning for < 35 MHz since presumably we're not
> using high speed modes when the DLL is that slow and so we're OK.

a warning should be ok.
If we ask 150M, but PLL only provide 175M maybe, then should we
fallback it to 150M or promote it to 200M when setting?

>
>
> NOTE: In rk3399 it's actually quite important to handle clocks that
> aren't exactly the right MHz.  When you ask for 150 MHz you actually
> end up a child of GPLL and actually end up at 148.5 MHz.  This should
> be close enough, but it's not exactly 150 MHz.  If we can't handle
> 148.5 MHz then the 150 MHz setting in the PHY is useless.
>
> Also note that on rk3399 we're fairly limited on the number of rates
> we can actually make since they need to be even divisors of 594 MHz or
> 800 MHz (assuming you don't rejigger all the PLLs in the SoC or
> something).  Most of the rates are actually in those ranges...

Yes I don't.

>
>
> -Doug
>
>
>


-- 
Best Regards
Shawn Lin


  reply	other threads:[~2016-06-14  0:24 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-07 22:44 [PATCH 0/11] Changes to support 150 MHz eMMC on rk3399 Douglas Anderson
     [not found] ` <1465339484-969-1-git-send-email-dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2016-06-07 22:44   ` [PATCH 01/11] phy: rockchip-emmc: Increase lock time allowance Douglas Anderson
     [not found]     ` <1465339484-969-2-git-send-email-dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2016-06-13  7:58       ` Shawn Lin
     [not found]         ` <3e19ff54-ee4a-c208-e137-1c0f8022f6b3-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-06-13 23:07           ` Doug Anderson
2016-06-07 22:44   ` [PATCH 02/11] mmc: sdhci-of-arasan: Always power the PHY off/on when clock changes Douglas Anderson
     [not found]     ` <1465339484-969-3-git-send-email-dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2016-06-13  8:08       ` Shawn Lin
2016-06-13 23:06         ` Doug Anderson
2016-06-07 22:44   ` [PATCH 03/11] Documentation: mmc: sdhci-of-arasan: Add soc-ctl-syscon for corecfg regs Douglas Anderson
2016-06-08 20:17     ` Rob Herring
2016-06-13  8:18     ` Shawn Lin
     [not found]       ` <45a7e8c7-5bd4-8c40-004a-b8906eff881a-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-06-13  9:32         ` Heiko Stübner
2016-06-13 23:07       ` Doug Anderson
2016-06-07 22:44   ` [PATCH 07/11] mmc: sdhci-of-arasan: Add ability to export card clock Douglas Anderson
2016-06-07 22:44   ` [PATCH 08/11] Documentation: phy: Let the rockchip eMMC PHY get an exported " Douglas Anderson
2016-06-10 13:36     ` Rob Herring
2016-06-13 23:05       ` Doug Anderson
2016-06-07 22:44   ` [PATCH 10/11] phy: rockchip-emmc: Minor code cleanup in rockchip_emmc_phy_power_off() Douglas Anderson
2016-06-13  8:56     ` Shawn Lin
2016-06-13 23:05       ` Doug Anderson
2016-06-07 22:44 ` [PATCH 04/11] mmc: sdhci-of-arasan: Properly set corecfg_baseclkfreq on rk3399 Douglas Anderson
2016-06-13  8:36   ` Shawn Lin
     [not found]     ` <f5dcc018-bd60-87a7-798b-efc261e443dd-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-06-13 23:06       ` Doug Anderson
2016-06-14  0:14         ` Shawn Lin
     [not found]           ` <47a2dcd9-9c3c-8fde-2be0-40e305c25e8d-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-06-14  0:43             ` Doug Anderson
     [not found]               ` <CAD=FV=UL5tU8RWtHF=-pE8SA0jUcBsqQDOU0BrruXOF7yGh5xg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-06-14  0:59                 ` Shawn Lin
2016-06-14  2:13                   ` Doug Anderson
2016-06-16  1:06                     ` Shawn Lin
2016-06-07 22:44 ` [PATCH 05/11] arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399 Douglas Anderson
2016-06-07 22:44 ` [PATCH 06/11] Documentation: mmc: sdhci-of-arasan: Add ability to export card clock Douglas Anderson
2016-06-08 20:19   ` Rob Herring
2016-06-08 20:52     ` Doug Anderson
2016-06-10 13:10       ` Rob Herring
2016-06-13 23:05         ` Doug Anderson
2016-06-07 22:44 ` [PATCH 09/11] phy: rockchip-emmc: Set phyctrl_frqsel based on " Douglas Anderson
     [not found]   ` <1465339484-969-10-git-send-email-dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2016-06-13  8:54     ` Shawn Lin
2016-06-13 23:05       ` Doug Anderson
2016-06-14  0:24         ` Shawn Lin [this message]
     [not found]           ` <036b0349-8343-f5de-7215-5a0843ebc6a9-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-06-14  0:45             ` Doug Anderson
2016-06-07 22:44 ` [PATCH 11/11] arm64: dts: rockchip: Provide emmcclk to PHY for rk3399 Douglas Anderson

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