From: Doug Anderson <dianders@chromium.org>
To: Shawn Lin <shawn.lin@rock-chips.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
Heiko Stuebner <heiko@sntech.de>,
Rob Herring <robh+dt@kernel.org>,
Ziyuan Xu <xzy.xu@rock-chips.com>,
Brian Norris <briannorris@chromium.org>,
Adrian Hunter <adrian.hunter@intel.com>,
"open list:ARM/Rockchip SoC..."
<linux-rockchip@lists.infradead.org>,
"linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
Michal Simek <michal.simek@xilinx.com>,
soren.brinkmann@xilinx.com,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 04/11] mmc: sdhci-of-arasan: Properly set corecfg_baseclkfreq on rk3399
Date: Mon, 13 Jun 2016 19:13:43 -0700 [thread overview]
Message-ID: <CAD=FV=WGwiQqRNMSSX9OR6nAOwuu7CbULuz7BcNp-S=duqpLLQ@mail.gmail.com> (raw)
In-Reply-To: <da1c9ae9-71d9-6e9d-7b9f-08485ee9178e@rock-chips.com>
Shawn,
On Mon, Jun 13, 2016 at 5:59 PM, Shawn Lin <shawn.lin@rock-chips.com> wrote:
>> Even in the case that an SoC designer didn't put a value into
>> corecfg_baseclkfreq that matched register[15:8], it seems very likely
>> that the rate returned from the clk_get_rate() would match.
>>
>> I guess what I'm saying is that, to me, it seems like my patch isn't
>> broken in any real systems. If we ever find a system that needs this
>> behavior in the future, we can add it. Until then, it seems like my
>> patch would be fine. Do you agree?
>
>
> I agree. But from the code itself, we should still use
> SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN to see if we could get
> it from internal register in case of some platforms don't
> provide the clk stuff.. Sounds sane? :)
Could we wait until there exists a SoC that needs to provide
baseclkfreq in its sdhci_arasan_soc_ctl_map table and that needs this
value copied from register[15:8]?
AKA:
A) If you have a SoC where clk_get_rate() is right and software needs
to set baseclkfreq manualy, then you should include "baseclkfreq" in
your sdhci_arasan_soc_ctl_map table. This is like rk3399. Note that
if _both_ clk_get_rate() and register[15:8] are right, that's fine.
We can still use clk_get_rate() since it will be exactly the same as
register[15:8].
B) If you have a SoC that doesn't even expose corecfg_baseclkfreq to
software control, just don't include "baseclkfreq" in your
sdhci_arasan_soc_ctl_map table. Easy. This is how my patch treats
anyone using the current "generic" bindings, but you could easily just
specify an offset of "-1" for baseclkfreq if you didn't want to use
the generic bindings but couldn't control baseclkfreq.
C) If you have a SoC that provides a valid value in register[15:8] and
clk_get_rate() is wrong and software is required to copy the value
from register[15:8] to baseclkfreq, technically we should fix
clk_get_rate() anyway. It's good when common clock framework provides
correct values. NOTE: It seems very unlikely to me that
register[15:8] would be right AND that software would be required to
copy this value to baseclkfreq, but I suppose there are some pretty
crazy hardware designs out there.
D) If you have a SoC that provides a valid value in register[15:8] and
clk_get_rate() is wrong and can't be fixed (REALLY?) and software is
required to copy the value from register[15:8] to baseclkfreq, we will
need to add new code. My assertion is that such a SoC doesn't exist
and is unlikely to ever exist, so I am hesitant to add extra code to
support this SoC.
With my patch, A) and B) are certainly handled. I think C) is
unlikely to exist, but if it did exist then I'd say we should fix
clk_get_rate(). I think D) is VERY unlikely to exist. If I'm shown
proof of D) existing, I'm happy to submit a patch for it. Until we
see proof of D)'s existence, I don't think we should clutter the code
with support for it.
-Doug
next prev parent reply other threads:[~2016-06-14 2:13 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-07 22:44 [PATCH 0/11] Changes to support 150 MHz eMMC on rk3399 Douglas Anderson
[not found] ` <1465339484-969-1-git-send-email-dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2016-06-07 22:44 ` [PATCH 01/11] phy: rockchip-emmc: Increase lock time allowance Douglas Anderson
[not found] ` <1465339484-969-2-git-send-email-dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2016-06-13 7:58 ` Shawn Lin
[not found] ` <3e19ff54-ee4a-c208-e137-1c0f8022f6b3-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-06-13 23:07 ` Doug Anderson
2016-06-07 22:44 ` [PATCH 02/11] mmc: sdhci-of-arasan: Always power the PHY off/on when clock changes Douglas Anderson
[not found] ` <1465339484-969-3-git-send-email-dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2016-06-13 8:08 ` Shawn Lin
2016-06-13 23:06 ` Doug Anderson
2016-06-07 22:44 ` [PATCH 03/11] Documentation: mmc: sdhci-of-arasan: Add soc-ctl-syscon for corecfg regs Douglas Anderson
2016-06-08 20:17 ` Rob Herring
2016-06-13 8:18 ` Shawn Lin
[not found] ` <45a7e8c7-5bd4-8c40-004a-b8906eff881a-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-06-13 9:32 ` Heiko Stübner
2016-06-13 23:07 ` Doug Anderson
2016-06-07 22:44 ` [PATCH 07/11] mmc: sdhci-of-arasan: Add ability to export card clock Douglas Anderson
2016-06-07 22:44 ` [PATCH 08/11] Documentation: phy: Let the rockchip eMMC PHY get an exported " Douglas Anderson
2016-06-10 13:36 ` Rob Herring
2016-06-13 23:05 ` Doug Anderson
2016-06-07 22:44 ` [PATCH 10/11] phy: rockchip-emmc: Minor code cleanup in rockchip_emmc_phy_power_off() Douglas Anderson
2016-06-13 8:56 ` Shawn Lin
2016-06-13 23:05 ` Doug Anderson
2016-06-07 22:44 ` [PATCH 04/11] mmc: sdhci-of-arasan: Properly set corecfg_baseclkfreq on rk3399 Douglas Anderson
2016-06-13 8:36 ` Shawn Lin
[not found] ` <f5dcc018-bd60-87a7-798b-efc261e443dd-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-06-13 23:06 ` Doug Anderson
2016-06-14 0:14 ` Shawn Lin
[not found] ` <47a2dcd9-9c3c-8fde-2be0-40e305c25e8d-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-06-14 0:43 ` Doug Anderson
[not found] ` <CAD=FV=UL5tU8RWtHF=-pE8SA0jUcBsqQDOU0BrruXOF7yGh5xg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-06-14 0:59 ` Shawn Lin
2016-06-14 2:13 ` Doug Anderson [this message]
2016-06-16 1:06 ` Shawn Lin
2016-06-07 22:44 ` [PATCH 05/11] arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399 Douglas Anderson
2016-06-07 22:44 ` [PATCH 06/11] Documentation: mmc: sdhci-of-arasan: Add ability to export card clock Douglas Anderson
2016-06-08 20:19 ` Rob Herring
2016-06-08 20:52 ` Doug Anderson
2016-06-10 13:10 ` Rob Herring
2016-06-13 23:05 ` Doug Anderson
2016-06-07 22:44 ` [PATCH 09/11] phy: rockchip-emmc: Set phyctrl_frqsel based on " Douglas Anderson
[not found] ` <1465339484-969-10-git-send-email-dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2016-06-13 8:54 ` Shawn Lin
2016-06-13 23:05 ` Doug Anderson
2016-06-14 0:24 ` Shawn Lin
[not found] ` <036b0349-8343-f5de-7215-5a0843ebc6a9-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-06-14 0:45 ` Doug Anderson
2016-06-07 22:44 ` [PATCH 11/11] arm64: dts: rockchip: Provide emmcclk to PHY for rk3399 Douglas Anderson
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