From: Francesco Lavra <francescolavra.fl@gmail.com>
To: Shawn Lin <shawn.lin@rock-chips.com>,
Heiko Stuebner <heiko@sntech.de>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Rob Herring <robh+dt@kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
Bjorn Helgaas <bhelgaas@google.com>
Cc: devicetree@vger.kernel.org, Simon Xue <xxm@rock-chips.com>,
Jingoo Han <jingoohan1@gmail.com>,
linux-rockchip@lists.infradead.org, linux-pci@vger.kernel.org,
William Wu <william.wu@rock-chips.com>
Subject: Re: [PATCH 5/6] PCI: rockchip: add DesignWare based PCIe controller
Date: Sat, 18 Jan 2020 17:36:25 +0100 [thread overview]
Message-ID: <0975b4e4-4bee-3f8e-5276-2bc78e6dabc0@gmail.com> (raw)
In-Reply-To: <1578986701-72072-1-git-send-email-shawn.lin@rock-chips.com>
On 1/14/20 8:25 AM, Shawn Lin wrote:
> +static int rockchip_pcie_reset_control_release(struct rockchip_pcie *rockchip)
> +{
> + struct device *dev = rockchip->pci->dev;
> + struct property *prop;
> + const char *name;
> + int ret, count, i = 0;
> +
> + count = of_property_count_strings(dev->of_node, "reset-names");
> + if (count < 1)
> + return -ENODEV;
> +
> + rockchip->rsts = devm_kcalloc(dev, count,
> + sizeof(struct reset_bulk_data),
> + GFP_KERNEL);
> + if (!rockchip->rsts)
> + return -ENOMEM;
> +
> + of_property_for_each_string(dev->of_node, "reset-names",
> + prop, name) {
> + rockchip->rsts[i].id = name;
> + if (!rockchip->rsts[i].id)
> + return -ENOMEM;
> + i++;
> + }
> +
> + for (i = 0; i < count; i++) {
> + rockchip->rsts[i].rst = devm_reset_control_get_exclusive(dev,
> + rockchip->rsts[i].id);
> + if (IS_ERR_OR_NULL(rockchip->rsts[i].rst)) {
> + dev_err(dev, "failed to get %s\n",
> + rockchip->clks[i].id);
> + return -PTR_ERR(rockchip->rsts[i].rst);
IS_ERR_OR_NULL() should be replaced with IS_ERR(), because
devm_reset_control_get_exclusive() never returns a NULL value.
Also, in case of error you should return the value from PTR_ERR(),
without the minus sign.
next prev parent reply other threads:[~2020-01-18 16:36 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-14 7:22 [PATCH 0/6] Add Rockchip new PCIe controller and combo phy support Shawn Lin
2020-01-14 7:22 ` [PATCH 1/6] dt-bindings: add binding for Rockchip combo phy using an Innosilicon IP Shawn Lin
2020-01-14 23:43 ` Rob Herring
2020-01-16 0:03 ` [PATCH 1/6] dt-bindings: add binding for Rockchip combo phy using an Innosilicon IP【请注意，邮件由linux-rockchip-bounces+shawn.lin=rock-chips.com@lists.infradead.org代发】 Shawn Lin
2020-01-14 7:22 ` [PATCH 2/6] phy/rockchip: inno-combophy: Add initial support Shawn Lin
2020-01-14 7:22 ` [PATCH 3/6] PCI: dwc: Skip allocating own MSI domain if using external MSI domain Shawn Lin
2020-01-14 7:22 ` [PATCH 4/6] dt-bindings: rockchip: Add DesignWare based PCIe controller Shawn Lin
2020-01-15 0:05 ` Rob Herring
2020-01-14 7:25 ` [PATCH 5/6] PCI: rockchip: add " Shawn Lin
2020-01-15 17:24 ` Bjorn Helgaas
2020-01-16 0:14 ` Shawn Lin
2020-01-16 21:36 ` Jingoo Han
2020-01-18 16:36 ` Francesco Lavra [this message]
2020-01-20 0:55 ` Shawn Lin
2020-01-14 7:25 ` [PATCH 6/6] MAINTAINERS: Update PCIe drivers for Rockchip Shawn Lin
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