From: Shawn Lin <shawn.lin@rock-chips.com>
To: Heiko Stuebner <heiko@sntech.de>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Rob Herring <robh+dt@kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
Bjorn Helgaas <bhelgaas@google.com>
Cc: Jingoo Han <jingoohan1@gmail.com>,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
William Wu <william.wu@rock-chips.com>,
Simon Xue <xxm@rock-chips.com>,
linux-rockchip@lists.infradead.org,
Shawn Lin <shawn.lin@rock-chips.com>
Subject: [PATCH 3/6] PCI: dwc: Skip allocating own MSI domain if using external MSI domain
Date: Tue, 14 Jan 2020 15:22:57 +0800 [thread overview]
Message-ID: <1578986580-71974-4-git-send-email-shawn.lin@rock-chips.com> (raw)
In-Reply-To: <1578986580-71974-1-git-send-email-shawn.lin@rock-chips.com>
On some platform, external MSI domain is using instead of the one
created by designware driver. For instance, if using GIC-V3-ITS
as a MSI domain, we only need set msi-map in the devicetree but
never need any bit in the designware driver to handle MSI stuff.
So skip allocating its own MSI domain for that case.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Simon Xue <xxm@rock-chips.com>
---
drivers/pci/controller/dwc/pcie-designware-host.c | 10 +++++++++-
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 395feb8..e78d094 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -257,6 +257,10 @@ int dw_pcie_allocate_domains(struct pcie_port *pp)
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node);
+ /* Rely on the external MSI domain */
+ if (pp->msi_ext)
+ return 0;
+
pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors,
&dw_pcie_msi_domain_ops, pp);
if (!pp->irq_domain) {
@@ -278,6 +282,9 @@ int dw_pcie_allocate_domains(struct pcie_port *pp)
void dw_pcie_free_msi(struct pcie_port *pp)
{
+ if (pp->msi_ext)
+ return;
+
if (pp->msi_irq) {
irq_set_chained_handler(pp->msi_irq, NULL);
irq_set_handler_data(pp->msi_irq, NULL);
@@ -413,7 +420,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
if (ret)
pci->num_viewport = 2;
- if (pci_msi_enabled()) {
+ if (pci_msi_enabled() &&
+ !pp->msi_ext) {
/*
* If a specific SoC driver needs to change the
* default number of vectors, it needs to implement
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index a22ea59..eeafa52 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -201,6 +201,7 @@ struct pcie_port {
u32 irq_mask[MAX_MSI_CTRLS];
struct pci_bus *root_bus;
raw_spinlock_t lock;
+ int msi_ext;
DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
};
--
1.9.1
next prev parent reply other threads:[~2020-01-14 7:24 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-14 7:22 [PATCH 0/6] Add Rockchip new PCIe controller and combo phy support Shawn Lin
2020-01-14 7:22 ` [PATCH 1/6] dt-bindings: add binding for Rockchip combo phy using an Innosilicon IP Shawn Lin
2020-01-14 23:43 ` Rob Herring
2020-01-16 0:03 ` [PATCH 1/6] dt-bindings: add binding for Rockchip combo phy using an Innosilicon IP【请注意,邮件由linux-rockchip-bounces+shawn.lin=rock-chips.com@lists.infradead.org代发】 Shawn Lin
2020-01-14 7:22 ` [PATCH 2/6] phy/rockchip: inno-combophy: Add initial support Shawn Lin
2020-01-14 7:22 ` Shawn Lin [this message]
2020-01-14 7:22 ` [PATCH 4/6] dt-bindings: rockchip: Add DesignWare based PCIe controller Shawn Lin
2020-01-15 0:05 ` Rob Herring
2020-01-14 7:25 ` [PATCH 5/6] PCI: rockchip: add " Shawn Lin
2020-01-15 17:24 ` Bjorn Helgaas
2020-01-16 0:14 ` Shawn Lin
2020-01-16 21:36 ` Jingoo Han
2020-01-18 16:36 ` Francesco Lavra
2020-01-20 0:55 ` Shawn Lin
2020-01-14 7:25 ` [PATCH 6/6] MAINTAINERS: Update PCIe drivers for Rockchip Shawn Lin
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