From: Akash Asthana <akashast@codeaurora.org>
To: gregkh@linuxfoundation.org, agross@kernel.org,
bjorn.andersson@linaro.org, wsa@the-dreams.de,
broonie@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org
Cc: linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org,
devicetree@vger.kernel.org, swboyd@chromium.org,
mgautam@codeaurora.org, linux-arm-msm@vger.kernel.org,
linux-serial@vger.kernel.org, mka@chromium.org,
dianders@chromium.org, evgreen@chromium.org,
Akash Asthana <akashast@codeaurora.org>
Subject: [PATCH V2 2/8] soc: qcom: geni: Support for ICC voting
Date: Fri, 13 Mar 2020 18:42:08 +0530 [thread overview]
Message-ID: <1584105134-13583-3-git-send-email-akashast@codeaurora.org> (raw)
In-Reply-To: <1584105134-13583-1-git-send-email-akashast@codeaurora.org>
Add necessary macros and structure variables to support ICC BW
voting from individual SE drivers.
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
---
Changes in V2:
- As per Bjorn's comment dropped enums for ICC paths, given the three
paths individual members
include/linux/qcom-geni-se.h | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/include/linux/qcom-geni-se.h b/include/linux/qcom-geni-se.h
index dd46494..eaae16e 100644
--- a/include/linux/qcom-geni-se.h
+++ b/include/linux/qcom-geni-se.h
@@ -6,6 +6,8 @@
#ifndef _LINUX_QCOM_GENI_SE
#define _LINUX_QCOM_GENI_SE
+#include <linux/interconnect.h>
+
/* Transfer mode supported by GENI Serial Engines */
enum geni_se_xfer_mode {
GENI_SE_INVALID,
@@ -33,6 +35,15 @@ struct clk;
* @clk: Handle to the core serial engine clock
* @num_clk_levels: Number of valid clock levels in clk_perf_tbl
* @clk_perf_tbl: Table of clock frequency input to serial engine clock
+ * @icc_path_geni_to_core: ICC path handle for geni to core
+ * @icc_path_cpu_to_geni: ICC path handle for cpu to geni
+ * @icc_path_geni_to_ddr: ICC path handle for geni to ddr
+ * @avg_bw_core: Average bus bandwidth value for QUP core 2x clock
+ * @peak_bw_core: Peak bus bandwidth value for QUP core 2x clock
+ * @avg_bw_cpu: Average bus bandwidth value for CPU
+ * @peak_bw_cpu: Peak bus bandwidth value for CPU
+ * @avg_bw_ddr: Average bus bandwidth value for DDR
+ * @peak_bw_ddr: Peak bus bandwidth value for DDR
*/
struct geni_se {
void __iomem *base;
@@ -41,6 +52,15 @@ struct geni_se {
struct clk *clk;
unsigned int num_clk_levels;
unsigned long *clk_perf_tbl;
+ struct icc_path *icc_path_geni_to_core;
+ struct icc_path *icc_path_cpu_to_geni;
+ struct icc_path *icc_path_geni_to_ddr;
+ unsigned int avg_bw_core;
+ unsigned int peak_bw_core;
+ unsigned int avg_bw_cpu;
+ unsigned int peak_bw_cpu;
+ unsigned int avg_bw_ddr;
+ unsigned int peak_bw_ddr;
};
/* Common SE registers */
@@ -229,6 +249,14 @@ struct geni_se {
#define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT)
#define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK)
+/* Core 2X clock frequency to BCM threshold mapping */
+#define CORE_2X_19_2_MHZ 960
+#define CORE_2X_50_MHZ 2500
+#define CORE_2X_100_MHZ 5000
+#define CORE_2X_150_MHZ 7500
+#define CORE_2X_200_MHZ 10000
+#define CORE_2X_236_MHZ 16383
+
#if IS_ENABLED(CONFIG_QCOM_GENI_SE)
u32 geni_se_get_qup_hw_version(struct geni_se *se);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
next prev parent reply other threads:[~2020-03-13 13:13 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-13 13:12 [PATCH V2 0/8] Add interconnect support to QSPI and QUP drivers Akash Asthana
2020-03-13 13:12 ` [PATCH V2 1/8] interconnect: Add devm_of_icc_get() as exported API for users Akash Asthana
2020-03-13 16:26 ` Matthias Kaehlcke
2020-03-27 23:02 ` Bjorn Andersson
2020-03-13 13:12 ` Akash Asthana [this message]
2020-03-13 16:42 ` [PATCH V2 2/8] soc: qcom: geni: Support for ICC voting Matthias Kaehlcke
2020-03-17 9:58 ` Akash Asthana
2020-03-17 19:06 ` Evan Green
[not found] ` <74851dda-296d-cdc5-2449-b9ec59bbc057@codeaurora.org>
2020-03-20 16:45 ` Evan Green
2020-03-27 5:33 ` Akash Asthana
2020-03-13 13:12 ` [PATCH V2 3/8] soc: qcom-geni-se: Add interconnect support to fix earlycon crash Akash Asthana
2020-03-13 20:44 ` Matthias Kaehlcke
2020-03-17 10:57 ` Akash Asthana
2020-03-17 18:29 ` Matthias Kaehlcke
2020-03-18 8:54 ` Akash Asthana
2020-03-19 19:43 ` Matthias Kaehlcke
2020-03-20 10:22 ` Akash Asthana
2020-03-20 16:30 ` Evan Green
2020-03-27 5:04 ` Akash Asthana
2020-03-27 23:23 ` Bjorn Andersson
2020-03-31 10:55 ` Akash Asthana
2020-03-17 19:08 ` Evan Green
2020-03-17 19:46 ` Doug Anderson
2020-03-18 10:57 ` Akash Asthana
2020-03-18 16:22 ` Evan Green
2020-03-13 13:12 ` [PATCH V2 4/8] tty: serial: qcom_geni_serial: Add interconnect support Akash Asthana
2020-03-13 21:28 ` Matthias Kaehlcke
2020-03-17 11:48 ` Akash Asthana
2020-03-17 19:08 ` Matthias Kaehlcke
2020-03-18 12:23 ` Akash Asthana
2020-03-19 20:42 ` Matthias Kaehlcke
2020-03-20 10:35 ` Akash Asthana
2020-03-13 13:12 ` [PATCH V2 5/8] i2c: i2c-qcom-geni: " Akash Asthana
2020-03-14 0:17 ` Matthias Kaehlcke
2020-03-17 11:51 ` Akash Asthana
2020-03-13 13:12 ` [PATCH V2 6/8] spi: spi-geni-qcom: " Akash Asthana
2020-03-13 13:16 ` Mark Brown
2020-03-17 9:35 ` Akash Asthana
2020-03-17 13:06 ` Mark Brown
2020-03-20 13:52 ` Akash Asthana
2020-03-14 0:41 ` Matthias Kaehlcke
2020-03-17 12:11 ` Akash Asthana
2020-03-13 13:12 ` [PATCH V2 7/8] spi: spi-qcom-qspi: " Akash Asthana
2020-03-14 0:58 ` Matthias Kaehlcke
2020-03-17 12:13 ` Akash Asthana
2020-03-17 19:08 ` Evan Green
2020-03-18 13:48 ` Akash Asthana
2020-03-18 16:30 ` Evan Green
2020-03-20 5:35 ` Akash Asthana
2020-03-13 13:12 ` [PATCH V2 8/8] arm64: dts: sc7180: Add interconnect for QUP and QSPI Akash Asthana
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