* [RFC PATCH 00/13] DMA Engine support for AM33xx
@ 2012-09-20 14:43 Matt Porter
[not found] ` <1348152226-13588-1-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
0 siblings, 1 reply; 52+ messages in thread
From: Matt Porter @ 2012-09-20 14:43 UTC (permalink / raw)
To: Tony Lindgren, Sekhar Nori, Grant Likely, Mark Brown,
Benoit Cousson, Russell King, Vinod Koul, Rob Landley,
Chris Ball
Cc: Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Dan Williams,
Linux SPI Devel List, Linux OMAP List, Linux ARM Kernel List
This series adds DMA Engine support for AM33xx, which uses
an EDMA DMAC. The EDMA DMAC has been previously supported by only
a private API implementation (much like the situation with OMAP
DMA) found on the DaVinci family of SoCs.
There are a mind-boggling number of dependencies for this series:
- Jon Hunter's OF DMA helpers series
https://patchwork.kernel.org/patch/1461061/
https://patchwork.kernel.org/patch/1461051/
- Patch to address OF DMA helpers naming issues:
https://patchwork.kernel.org/patch/1477921/
- EDMA DMA Engine wrapper driver in linux-next
c2dde5f8f2095d7c623ff3565c1462e190272273
- EDMA DMA Engine wrapper driver bug fix:
https://patchwork.kernel.org/patch/1474411/
- A huge number of patches in linux-next for AM33xx boot
(too numerous to list)
The approach taken is similar to how OMAP DMA is being converted to
DMA Engine support. With the functional EDMA private API already
existing in mach-davinci/dma.c, we first move that to an ARM common
area so it can be shared. Adding DT and runtime PM support to the
private EDMA API implementation allows it to run on AM33xx. AM33xx
*only* boots using DT so we leverage Jon's generic DT DMA helpers to
register EDMA DMAC with the of_dma framework and then add support
for calling the dma_request_slave_channel() API to both the mmc
and spi drivers.
What works? Well, with this series we now have MMC and SPI support
on AM33xx. The only caveat for MMC is that the mmc3 controller has
its events on the crossbar and is not usable right now.
This is tested on BeagleBone with a SPI framebuffer driver and SD
card.
After this series, the plan is to convert the last in-tree user
of the private EDMA API (davinci-pcm/mcasp) and then eliminate
the private EDMA API by folding its functionality into
drivers/dma/edma.c.
TODO:
add AM33xx crossbar support to the private EDMA API
(any EDMA events on the crossbar are not supported)
Matt Porter (13):
ARM: davinci: move private EDMA API to arm/common
ARM: edma: remove unused transfer controller handlers
ARM: edma: add DT and runtime PM support for AM335x
dmaengine: edma: enable build for AM335x
dma: Add TI EDMA device tree binding
ARM: omap: add hsmmc am33xx specific init
mmc: omap_hsmmc: dma_request_slave_channel() support for DT platforms
mmc: omap_hsmmc: limit max_segs with the EDMA DMAC
mmc: omap_hsmmc: add generic DMA request support to the DT binding
spi: omap2-mcspi: dma_request_slave_channel() support for DT
platforms
spi: omap2-mcspi: add generic DMA request support to the DT binding
ARM: dts: add am33xx EDMA support
Documentation: add schedule for removing private EDMA API
Documentation/devicetree/bindings/dma/ti-edma.txt | 49 +
.../devicetree/bindings/mmc/ti-omap-hsmmc.txt | 25 +-
Documentation/devicetree/bindings/spi/omap-spi.txt | 27 +-
Documentation/feature-removal-schedule.txt | 10 +
arch/arm/Kconfig | 1 +
arch/arm/boot/dts/am33xx.dtsi | 46 +
arch/arm/common/Kconfig | 3 +
arch/arm/common/Makefile | 1 +
arch/arm/common/edma.c | 1779 ++++++++++++++++++++
arch/arm/include/asm/mach/edma.h | 267 +++
arch/arm/mach-davinci/Makefile | 2 +-
arch/arm/mach-davinci/devices.c | 3 +-
arch/arm/mach-davinci/dm355.c | 2 +-
arch/arm/mach-davinci/dm365.c | 2 +-
arch/arm/mach-davinci/dm644x.c | 2 +-
arch/arm/mach-davinci/dm646x.c | 2 +-
arch/arm/mach-davinci/dma.c | 1588 -----------------
arch/arm/mach-davinci/include/mach/asp.h | 2 +-
arch/arm/mach-davinci/include/mach/da8xx.h | 3 +-
arch/arm/mach-davinci/include/mach/edma.h | 267 ---
arch/arm/mach-davinci/include/mach/spi.h | 2 +-
arch/arm/mach-omap2/hsmmc.c | 7 +-
arch/arm/plat-omap/Kconfig | 1 +
drivers/dma/Kconfig | 2 +-
drivers/dma/edma.c | 2 +-
drivers/mmc/host/omap_hsmmc.c | 26 +-
drivers/spi/spi-omap2-mcspi.c | 68 +-
27 files changed, 2296 insertions(+), 1893 deletions(-)
create mode 100644 Documentation/devicetree/bindings/dma/ti-edma.txt
create mode 100644 arch/arm/common/edma.c
create mode 100644 arch/arm/include/asm/mach/edma.h
delete mode 100644 arch/arm/mach-davinci/dma.c
delete mode 100644 arch/arm/mach-davinci/include/mach/edma.h
--
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^ permalink raw reply [flat|nested] 52+ messages in thread
* [RFC PATCH 01/13] ARM: davinci: move private EDMA API to arm/common
[not found] ` <1348152226-13588-1-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
@ 2012-09-20 14:43 ` Matt Porter
[not found] ` <1348152226-13588-2-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
` (2 more replies)
2012-09-20 14:43 ` [RFC PATCH 02/13] ARM: edma: remove unused transfer controller handlers Matt Porter
` (12 subsequent siblings)
13 siblings, 3 replies; 52+ messages in thread
From: Matt Porter @ 2012-09-20 14:43 UTC (permalink / raw)
To: Tony Lindgren, Sekhar Nori, Grant Likely, Mark Brown,
Benoit Cousson, Russell King, Vinod Koul, Rob Landley,
Chris Ball
Cc: Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Dan Williams,
Linux SPI Devel List, Linux OMAP List, Linux ARM Kernel List
Move mach-davinci/dma.c to common/edma.c so it can be used
by OMAP (specifically AM33xx atm) as well. This just moves
the private EDMA API but does not support OMAP.
Signed-off-by: Matt Porter <mporter-l0cyMroinI0@public.gmane.org>
---
arch/arm/Kconfig | 1 +
arch/arm/common/Kconfig | 3 +
arch/arm/common/Makefile | 1 +
arch/arm/common/edma.c | 1588 ++++++++++++++++++++++++++++
arch/arm/include/asm/mach/edma.h | 267 +++++
arch/arm/mach-davinci/Makefile | 2 +-
arch/arm/mach-davinci/devices.c | 3 +-
arch/arm/mach-davinci/dm355.c | 2 +-
arch/arm/mach-davinci/dm365.c | 2 +-
arch/arm/mach-davinci/dm644x.c | 2 +-
arch/arm/mach-davinci/dm646x.c | 2 +-
arch/arm/mach-davinci/dma.c | 1588 ----------------------------
arch/arm/mach-davinci/include/mach/asp.h | 2 +-
arch/arm/mach-davinci/include/mach/da8xx.h | 3 +-
arch/arm/mach-davinci/include/mach/edma.h | 267 -----
arch/arm/mach-davinci/include/mach/spi.h | 2 +-
arch/arm/plat-omap/Kconfig | 1 +
17 files changed, 1872 insertions(+), 1864 deletions(-)
create mode 100644 arch/arm/common/edma.c
create mode 100644 arch/arm/include/asm/mach/edma.h
delete mode 100644 arch/arm/mach-davinci/dma.c
delete mode 100644 arch/arm/mach-davinci/include/mach/edma.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2f88d8d..5272f72 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -971,6 +971,7 @@ config ARCH_DAVINCI
select GENERIC_ALLOCATOR
select GENERIC_IRQ_CHIP
select ARCH_HAS_HOLES_MEMORYMODEL
+ select TI_PRIV_EDMA
help
Support for TI's DaVinci platform.
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 283fa1d..bd87838 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -40,3 +40,6 @@ config SHARP_PARAM
config SHARP_SCOOP
bool
+
+config TI_PRIV_EDMA
+ bool
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index e8a4e58..d09a39b 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -13,3 +13,4 @@ obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
obj-$(CONFIG_SHARP_SCOOP) += scoop.o
obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o
obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o
+obj-$(CONFIG_TI_PRIV_EDMA) += edma.o
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
new file mode 100644
index 0000000..cecc50e
--- /dev/null
+++ b/arch/arm/common/edma.c
@@ -0,0 +1,1588 @@
+/*
+ * EDMA3 support for DaVinci
+ *
+ * Copyright (C) 2006-2009 Texas Instruments.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+
+#include <asm/mach/edma.h>
+
+/* Offsets matching "struct edmacc_param" */
+#define PARM_OPT 0x00
+#define PARM_SRC 0x04
+#define PARM_A_B_CNT 0x08
+#define PARM_DST 0x0c
+#define PARM_SRC_DST_BIDX 0x10
+#define PARM_LINK_BCNTRLD 0x14
+#define PARM_SRC_DST_CIDX 0x18
+#define PARM_CCNT 0x1c
+
+#define PARM_SIZE 0x20
+
+/* Offsets for EDMA CC global channel registers and their shadows */
+#define SH_ER 0x00 /* 64 bits */
+#define SH_ECR 0x08 /* 64 bits */
+#define SH_ESR 0x10 /* 64 bits */
+#define SH_CER 0x18 /* 64 bits */
+#define SH_EER 0x20 /* 64 bits */
+#define SH_EECR 0x28 /* 64 bits */
+#define SH_EESR 0x30 /* 64 bits */
+#define SH_SER 0x38 /* 64 bits */
+#define SH_SECR 0x40 /* 64 bits */
+#define SH_IER 0x50 /* 64 bits */
+#define SH_IECR 0x58 /* 64 bits */
+#define SH_IESR 0x60 /* 64 bits */
+#define SH_IPR 0x68 /* 64 bits */
+#define SH_ICR 0x70 /* 64 bits */
+#define SH_IEVAL 0x78
+#define SH_QER 0x80
+#define SH_QEER 0x84
+#define SH_QEECR 0x88
+#define SH_QEESR 0x8c
+#define SH_QSER 0x90
+#define SH_QSECR 0x94
+#define SH_SIZE 0x200
+
+/* Offsets for EDMA CC global registers */
+#define EDMA_REV 0x0000
+#define EDMA_CCCFG 0x0004
+#define EDMA_QCHMAP 0x0200 /* 8 registers */
+#define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
+#define EDMA_QDMAQNUM 0x0260
+#define EDMA_QUETCMAP 0x0280
+#define EDMA_QUEPRI 0x0284
+#define EDMA_EMR 0x0300 /* 64 bits */
+#define EDMA_EMCR 0x0308 /* 64 bits */
+#define EDMA_QEMR 0x0310
+#define EDMA_QEMCR 0x0314
+#define EDMA_CCERR 0x0318
+#define EDMA_CCERRCLR 0x031c
+#define EDMA_EEVAL 0x0320
+#define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
+#define EDMA_QRAE 0x0380 /* 4 registers */
+#define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
+#define EDMA_QSTAT 0x0600 /* 2 registers */
+#define EDMA_QWMTHRA 0x0620
+#define EDMA_QWMTHRB 0x0624
+#define EDMA_CCSTAT 0x0640
+
+#define EDMA_M 0x1000 /* global channel registers */
+#define EDMA_ECR 0x1008
+#define EDMA_ECRH 0x100C
+#define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */
+#define EDMA_PARM 0x4000 /* 128 param entries */
+
+#define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
+
+#define EDMA_DCHMAP 0x0100 /* 64 registers */
+#define CHMAP_EXIST BIT(24)
+
+#define EDMA_MAX_DMACH 64
+#define EDMA_MAX_PARAMENTRY 512
+
+/*****************************************************************************/
+
+static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
+
+static inline unsigned int edma_read(unsigned ctlr, int offset)
+{
+ return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
+}
+
+static inline void edma_write(unsigned ctlr, int offset, int val)
+{
+ __raw_writel(val, edmacc_regs_base[ctlr] + offset);
+}
+static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
+ unsigned or)
+{
+ unsigned val = edma_read(ctlr, offset);
+ val &= and;
+ val |= or;
+ edma_write(ctlr, offset, val);
+}
+static inline void edma_and(unsigned ctlr, int offset, unsigned and)
+{
+ unsigned val = edma_read(ctlr, offset);
+ val &= and;
+ edma_write(ctlr, offset, val);
+}
+static inline void edma_or(unsigned ctlr, int offset, unsigned or)
+{
+ unsigned val = edma_read(ctlr, offset);
+ val |= or;
+ edma_write(ctlr, offset, val);
+}
+static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
+{
+ return edma_read(ctlr, offset + (i << 2));
+}
+static inline void edma_write_array(unsigned ctlr, int offset, int i,
+ unsigned val)
+{
+ edma_write(ctlr, offset + (i << 2), val);
+}
+static inline void edma_modify_array(unsigned ctlr, int offset, int i,
+ unsigned and, unsigned or)
+{
+ edma_modify(ctlr, offset + (i << 2), and, or);
+}
+static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
+{
+ edma_or(ctlr, offset + (i << 2), or);
+}
+static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
+ unsigned or)
+{
+ edma_or(ctlr, offset + ((i*2 + j) << 2), or);
+}
+static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
+ unsigned val)
+{
+ edma_write(ctlr, offset + ((i*2 + j) << 2), val);
+}
+static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
+{
+ return edma_read(ctlr, EDMA_SHADOW0 + offset);
+}
+static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
+ int i)
+{
+ return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
+}
+static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
+{
+ edma_write(ctlr, EDMA_SHADOW0 + offset, val);
+}
+static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
+ unsigned val)
+{
+ edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
+}
+static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
+ int param_no)
+{
+ return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
+}
+static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
+ unsigned val)
+{
+ edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
+}
+static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
+ unsigned and, unsigned or)
+{
+ edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
+}
+static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
+ unsigned and)
+{
+ edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
+}
+static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
+ unsigned or)
+{
+ edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
+}
+
+static inline void set_bits(int offset, int len, unsigned long *p)
+{
+ for (; len > 0; len--)
+ set_bit(offset + (len - 1), p);
+}
+
+static inline void clear_bits(int offset, int len, unsigned long *p)
+{
+ for (; len > 0; len--)
+ clear_bit(offset + (len - 1), p);
+}
+
+/*****************************************************************************/
+
+/* actual number of DMA channels and slots on this silicon */
+struct edma {
+ /* how many dma resources of each type */
+ unsigned num_channels;
+ unsigned num_region;
+ unsigned num_slots;
+ unsigned num_tc;
+ unsigned num_cc;
+ enum dma_event_q default_queue;
+
+ /* list of channels with no even trigger; terminated by "-1" */
+ const s8 *noevent;
+
+ /* The edma_inuse bit for each PaRAM slot is clear unless the
+ * channel is in use ... by ARM or DSP, for QDMA, or whatever.
+ */
+ DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
+
+ /* The edma_unused bit for each channel is clear unless
+ * it is not being used on this platform. It uses a bit
+ * of SOC-specific initialization code.
+ */
+ DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
+
+ unsigned irq_res_start;
+ unsigned irq_res_end;
+
+ struct dma_interrupt_data {
+ void (*callback)(unsigned channel, unsigned short ch_status,
+ void *data);
+ void *data;
+ } intr_data[EDMA_MAX_DMACH];
+};
+
+static struct edma *edma_cc[EDMA_MAX_CC];
+static int arch_num_cc;
+
+/* dummy param set used to (re)initialize parameter RAM slots */
+static const struct edmacc_param dummy_paramset = {
+ .link_bcntrld = 0xffff,
+ .ccnt = 1,
+};
+
+/*****************************************************************************/
+
+static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
+ enum dma_event_q queue_no)
+{
+ int bit = (ch_no & 0x7) * 4;
+
+ /* default to low priority queue */
+ if (queue_no == EVENTQ_DEFAULT)
+ queue_no = edma_cc[ctlr]->default_queue;
+
+ queue_no &= 7;
+ edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
+ ~(0x7 << bit), queue_no << bit);
+}
+
+static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no)
+{
+ int bit = queue_no * 4;
+ edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
+}
+
+static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
+ int priority)
+{
+ int bit = queue_no * 4;
+ edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
+ ((priority & 0x7) << bit));
+}
+
+/**
+ * map_dmach_param - Maps channel number to param entry number
+ *
+ * This maps the dma channel number to param entry numberter. In
+ * other words using the DMA channel mapping registers a param entry
+ * can be mapped to any channel
+ *
+ * Callers are responsible for ensuring the channel mapping logic is
+ * included in that particular EDMA variant (Eg : dm646x)
+ *
+ */
+static void __init map_dmach_param(unsigned ctlr)
+{
+ int i;
+ for (i = 0; i < EDMA_MAX_DMACH; i++)
+ edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
+}
+
+static inline void
+setup_dma_interrupt(unsigned lch,
+ void (*callback)(unsigned channel, u16 ch_status, void *data),
+ void *data)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(lch);
+ lch = EDMA_CHAN_SLOT(lch);
+
+ if (!callback)
+ edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
+ BIT(lch & 0x1f));
+
+ edma_cc[ctlr]->intr_data[lch].callback = callback;
+ edma_cc[ctlr]->intr_data[lch].data = data;
+
+ if (callback) {
+ edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
+ BIT(lch & 0x1f));
+ edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
+ BIT(lch & 0x1f));
+ }
+}
+
+static int irq2ctlr(int irq)
+{
+ if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
+ return 0;
+ else if (irq >= edma_cc[1]->irq_res_start &&
+ irq <= edma_cc[1]->irq_res_end)
+ return 1;
+
+ return -1;
+}
+
+/******************************************************************************
+ *
+ * DMA interrupt handler
+ *
+ *****************************************************************************/
+static irqreturn_t dma_irq_handler(int irq, void *data)
+{
+ int ctlr;
+ u32 sh_ier;
+ u32 sh_ipr;
+ u32 bank;
+
+ ctlr = irq2ctlr(irq);
+ if (ctlr < 0)
+ return IRQ_NONE;
+
+ dev_dbg(data, "dma_irq_handler\n");
+
+ sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0);
+ if (!sh_ipr) {
+ sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1);
+ if (!sh_ipr)
+ return IRQ_NONE;
+ sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1);
+ bank = 1;
+ } else {
+ sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0);
+ bank = 0;
+ }
+
+ do {
+ u32 slot;
+ u32 channel;
+
+ dev_dbg(data, "IPR%d %08x\n", bank, sh_ipr);
+
+ slot = __ffs(sh_ipr);
+ sh_ipr &= ~(BIT(slot));
+
+ if (sh_ier & BIT(slot)) {
+ channel = (bank << 5) | slot;
+ /* Clear the corresponding IPR bits */
+ edma_shadow0_write_array(ctlr, SH_ICR, bank,
+ BIT(slot));
+ if (edma_cc[ctlr]->intr_data[channel].callback)
+ edma_cc[ctlr]->intr_data[channel].callback(
+ channel, DMA_COMPLETE,
+ edma_cc[ctlr]->intr_data[channel].data);
+ }
+ } while (sh_ipr);
+
+ edma_shadow0_write(ctlr, SH_IEVAL, 1);
+ return IRQ_HANDLED;
+}
+
+/******************************************************************************
+ *
+ * DMA error interrupt handler
+ *
+ *****************************************************************************/
+static irqreturn_t dma_ccerr_handler(int irq, void *data)
+{
+ int i;
+ int ctlr;
+ unsigned int cnt = 0;
+
+ ctlr = irq2ctlr(irq);
+ if (ctlr < 0)
+ return IRQ_NONE;
+
+ dev_dbg(data, "dma_ccerr_handler\n");
+
+ if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
+ (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
+ (edma_read(ctlr, EDMA_QEMR) == 0) &&
+ (edma_read(ctlr, EDMA_CCERR) == 0))
+ return IRQ_NONE;
+
+ while (1) {
+ int j = -1;
+ if (edma_read_array(ctlr, EDMA_EMR, 0))
+ j = 0;
+ else if (edma_read_array(ctlr, EDMA_EMR, 1))
+ j = 1;
+ if (j >= 0) {
+ dev_dbg(data, "EMR%d %08x\n", j,
+ edma_read_array(ctlr, EDMA_EMR, j));
+ for (i = 0; i < 32; i++) {
+ int k = (j << 5) + i;
+ if (edma_read_array(ctlr, EDMA_EMR, j) &
+ BIT(i)) {
+ /* Clear the corresponding EMR bits */
+ edma_write_array(ctlr, EDMA_EMCR, j,
+ BIT(i));
+ /* Clear any SER */
+ edma_shadow0_write_array(ctlr, SH_SECR,
+ j, BIT(i));
+ if (edma_cc[ctlr]->intr_data[k].
+ callback) {
+ edma_cc[ctlr]->intr_data[k].
+ callback(k,
+ DMA_CC_ERROR,
+ edma_cc[ctlr]->intr_data
+ [k].data);
+ }
+ }
+ }
+ } else if (edma_read(ctlr, EDMA_QEMR)) {
+ dev_dbg(data, "QEMR %02x\n",
+ edma_read(ctlr, EDMA_QEMR));
+ for (i = 0; i < 8; i++) {
+ if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
+ /* Clear the corresponding IPR bits */
+ edma_write(ctlr, EDMA_QEMCR, BIT(i));
+ edma_shadow0_write(ctlr, SH_QSECR,
+ BIT(i));
+
+ /* NOTE: not reported!! */
+ }
+ }
+ } else if (edma_read(ctlr, EDMA_CCERR)) {
+ dev_dbg(data, "CCERR %08x\n",
+ edma_read(ctlr, EDMA_CCERR));
+ /* FIXME: CCERR.BIT(16) ignored! much better
+ * to just write CCERRCLR with CCERR value...
+ */
+ for (i = 0; i < 8; i++) {
+ if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
+ /* Clear the corresponding IPR bits */
+ edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
+
+ /* NOTE: not reported!! */
+ }
+ }
+ }
+ if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
+ (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
+ (edma_read(ctlr, EDMA_QEMR) == 0) &&
+ (edma_read(ctlr, EDMA_CCERR) == 0))
+ break;
+ cnt++;
+ if (cnt > 10)
+ break;
+ }
+ edma_write(ctlr, EDMA_EEVAL, 1);
+ return IRQ_HANDLED;
+}
+
+/******************************************************************************
+ *
+ * Transfer controller error interrupt handlers
+ *
+ *****************************************************************************/
+
+#define tc_errs_handled false /* disabled as long as they're NOPs */
+
+static irqreturn_t dma_tc0err_handler(int irq, void *data)
+{
+ dev_dbg(data, "dma_tc0err_handler\n");
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t dma_tc1err_handler(int irq, void *data)
+{
+ dev_dbg(data, "dma_tc1err_handler\n");
+ return IRQ_HANDLED;
+}
+
+static int reserve_contiguous_slots(int ctlr, unsigned int id,
+ unsigned int num_slots,
+ unsigned int start_slot)
+{
+ int i, j;
+ unsigned int count = num_slots;
+ int stop_slot = start_slot;
+ DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
+
+ for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
+ j = EDMA_CHAN_SLOT(i);
+ if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
+ /* Record our current beginning slot */
+ if (count == num_slots)
+ stop_slot = i;
+
+ count--;
+ set_bit(j, tmp_inuse);
+
+ if (count == 0)
+ break;
+ } else {
+ clear_bit(j, tmp_inuse);
+
+ if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
+ stop_slot = i;
+ break;
+ } else {
+ count = num_slots;
+ }
+ }
+ }
+
+ /*
+ * We have to clear any bits that we set
+ * if we run out parameter RAM slots, i.e we do find a set
+ * of contiguous parameter RAM slots but do not find the exact number
+ * requested as we may reach the total number of parameter RAM slots
+ */
+ if (i == edma_cc[ctlr]->num_slots)
+ stop_slot = i;
+
+ j = start_slot;
+ for_each_set_bit_from(j, tmp_inuse, stop_slot)
+ clear_bit(j, edma_cc[ctlr]->edma_inuse);
+
+ if (count)
+ return -EBUSY;
+
+ for (j = i - num_slots + 1; j <= i; ++j)
+ memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),
+ &dummy_paramset, PARM_SIZE);
+
+ return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
+}
+
+static int prepare_unused_channel_list(struct device *dev, void *data)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ int i, ctlr;
+
+ for (i = 0; i < pdev->num_resources; i++) {
+ if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
+ (int)pdev->resource[i].start >= 0) {
+ ctlr = EDMA_CTLR(pdev->resource[i].start);
+ clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
+ edma_cc[ctlr]->edma_unused);
+ }
+ }
+
+ return 0;
+}
+
+/*-----------------------------------------------------------------------*/
+
+static bool unused_chan_list_done;
+
+/* Resource alloc/free: dma channels, parameter RAM slots */
+
+/**
+ * edma_alloc_channel - allocate DMA channel and paired parameter RAM
+ * @channel: specific channel to allocate; negative for "any unmapped channel"
+ * @callback: optional; to be issued on DMA completion or errors
+ * @data: passed to callback
+ * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
+ * Controller (TC) executes requests using this channel. Use
+ * EVENTQ_DEFAULT unless you really need a high priority queue.
+ *
+ * This allocates a DMA channel and its associated parameter RAM slot.
+ * The parameter RAM is initialized to hold a dummy transfer.
+ *
+ * Normal use is to pass a specific channel number as @channel, to make
+ * use of hardware events mapped to that channel. When the channel will
+ * be used only for software triggering or event chaining, channels not
+ * mapped to hardware events (or mapped to unused events) are preferable.
+ *
+ * DMA transfers start from a channel using edma_start(), or by
+ * chaining. When the transfer described in that channel's parameter RAM
+ * slot completes, that slot's data may be reloaded through a link.
+ *
+ * DMA errors are only reported to the @callback associated with the
+ * channel driving that transfer, but transfer completion callbacks can
+ * be sent to another channel under control of the TCC field in
+ * the option word of the transfer's parameter RAM set. Drivers must not
+ * use DMA transfer completion callbacks for channels they did not allocate.
+ * (The same applies to TCC codes used in transfer chaining.)
+ *
+ * Returns the number of the channel, else negative errno.
+ */
+int edma_alloc_channel(int channel,
+ void (*callback)(unsigned channel, u16 ch_status, void *data),
+ void *data,
+ enum dma_event_q eventq_no)
+{
+ unsigned i, done = 0, ctlr = 0;
+ int ret = 0;
+
+ if (!unused_chan_list_done) {
+ /*
+ * Scan all the platform devices to find out the EDMA channels
+ * used and clear them in the unused list, making the rest
+ * available for ARM usage.
+ */
+ ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
+ prepare_unused_channel_list);
+ if (ret < 0)
+ return ret;
+
+ unused_chan_list_done = true;
+ }
+
+ if (channel >= 0) {
+ ctlr = EDMA_CTLR(channel);
+ channel = EDMA_CHAN_SLOT(channel);
+ }
+
+ if (channel < 0) {
+ for (i = 0; i < arch_num_cc; i++) {
+ channel = 0;
+ for (;;) {
+ channel = find_next_bit(edma_cc[i]->edma_unused,
+ edma_cc[i]->num_channels,
+ channel);
+ if (channel == edma_cc[i]->num_channels)
+ break;
+ if (!test_and_set_bit(channel,
+ edma_cc[i]->edma_inuse)) {
+ done = 1;
+ ctlr = i;
+ break;
+ }
+ channel++;
+ }
+ if (done)
+ break;
+ }
+ if (!done)
+ return -ENOMEM;
+ } else if (channel >= edma_cc[ctlr]->num_channels) {
+ return -EINVAL;
+ } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
+ return -EBUSY;
+ }
+
+ /* ensure access through shadow region 0 */
+ edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
+
+ /* ensure no events are pending */
+ edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
+ memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
+ &dummy_paramset, PARM_SIZE);
+
+ if (callback)
+ setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
+ callback, data);
+
+ map_dmach_queue(ctlr, channel, eventq_no);
+
+ return EDMA_CTLR_CHAN(ctlr, channel);
+}
+EXPORT_SYMBOL(edma_alloc_channel);
+
+
+/**
+ * edma_free_channel - deallocate DMA channel
+ * @channel: dma channel returned from edma_alloc_channel()
+ *
+ * This deallocates the DMA channel and associated parameter RAM slot
+ * allocated by edma_alloc_channel().
+ *
+ * Callers are responsible for ensuring the channel is inactive, and
+ * will not be reactivated by linking, chaining, or software calls to
+ * edma_start().
+ */
+void edma_free_channel(unsigned channel)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(channel);
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel >= edma_cc[ctlr]->num_channels)
+ return;
+
+ setup_dma_interrupt(channel, NULL, NULL);
+ /* REVISIT should probably take out of shadow region 0 */
+
+ memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
+ &dummy_paramset, PARM_SIZE);
+ clear_bit(channel, edma_cc[ctlr]->edma_inuse);
+}
+EXPORT_SYMBOL(edma_free_channel);
+
+/**
+ * edma_alloc_slot - allocate DMA parameter RAM
+ * @slot: specific slot to allocate; negative for "any unused slot"
+ *
+ * This allocates a parameter RAM slot, initializing it to hold a
+ * dummy transfer. Slots allocated using this routine have not been
+ * mapped to a hardware DMA channel, and will normally be used by
+ * linking to them from a slot associated with a DMA channel.
+ *
+ * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
+ * slots may be allocated on behalf of DSP firmware.
+ *
+ * Returns the number of the slot, else negative errno.
+ */
+int edma_alloc_slot(unsigned ctlr, int slot)
+{
+ if (slot >= 0)
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot < 0) {
+ slot = edma_cc[ctlr]->num_channels;
+ for (;;) {
+ slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
+ edma_cc[ctlr]->num_slots, slot);
+ if (slot == edma_cc[ctlr]->num_slots)
+ return -ENOMEM;
+ if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
+ break;
+ }
+ } else if (slot < edma_cc[ctlr]->num_channels ||
+ slot >= edma_cc[ctlr]->num_slots) {
+ return -EINVAL;
+ } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
+ return -EBUSY;
+ }
+
+ memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
+ &dummy_paramset, PARM_SIZE);
+
+ return EDMA_CTLR_CHAN(ctlr, slot);
+}
+EXPORT_SYMBOL(edma_alloc_slot);
+
+/**
+ * edma_free_slot - deallocate DMA parameter RAM
+ * @slot: parameter RAM slot returned from edma_alloc_slot()
+ *
+ * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
+ * Callers are responsible for ensuring the slot is inactive, and will
+ * not be activated.
+ */
+void edma_free_slot(unsigned slot)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot < edma_cc[ctlr]->num_channels ||
+ slot >= edma_cc[ctlr]->num_slots)
+ return;
+
+ memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
+ &dummy_paramset, PARM_SIZE);
+ clear_bit(slot, edma_cc[ctlr]->edma_inuse);
+}
+EXPORT_SYMBOL(edma_free_slot);
+
+
+/**
+ * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
+ * The API will return the starting point of a set of
+ * contiguous parameter RAM slots that have been requested
+ *
+ * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
+ * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
+ * @count: number of contiguous Paramter RAM slots
+ * @slot - the start value of Parameter RAM slot that should be passed if id
+ * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
+ *
+ * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
+ * contiguous Parameter RAM slots from parameter RAM 64 in the case of
+ * DaVinci SOCs and 32 in the case of DA8xx SOCs.
+ *
+ * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
+ * set of contiguous parameter RAM slots from the "slot" that is passed as an
+ * argument to the API.
+ *
+ * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
+ * starts looking for a set of contiguous parameter RAMs from the "slot"
+ * that is passed as an argument to the API. On failure the API will try to
+ * find a set of contiguous Parameter RAM slots from the remaining Parameter
+ * RAM slots
+ */
+int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
+{
+ /*
+ * The start slot requested should be greater than
+ * the number of channels and lesser than the total number
+ * of slots
+ */
+ if ((id != EDMA_CONT_PARAMS_ANY) &&
+ (slot < edma_cc[ctlr]->num_channels ||
+ slot >= edma_cc[ctlr]->num_slots))
+ return -EINVAL;
+
+ /*
+ * The number of parameter RAM slots requested cannot be less than 1
+ * and cannot be more than the number of slots minus the number of
+ * channels
+ */
+ if (count < 1 || count >
+ (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
+ return -EINVAL;
+
+ switch (id) {
+ case EDMA_CONT_PARAMS_ANY:
+ return reserve_contiguous_slots(ctlr, id, count,
+ edma_cc[ctlr]->num_channels);
+ case EDMA_CONT_PARAMS_FIXED_EXACT:
+ case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
+ return reserve_contiguous_slots(ctlr, id, count, slot);
+ default:
+ return -EINVAL;
+ }
+
+}
+EXPORT_SYMBOL(edma_alloc_cont_slots);
+
+/**
+ * edma_free_cont_slots - deallocate DMA parameter RAM slots
+ * @slot: first parameter RAM of a set of parameter RAM slots to be freed
+ * @count: the number of contiguous parameter RAM slots to be freed
+ *
+ * This deallocates the parameter RAM slots allocated by
+ * edma_alloc_cont_slots.
+ * Callers/applications need to keep track of sets of contiguous
+ * parameter RAM slots that have been allocated using the edma_alloc_cont_slots
+ * API.
+ * Callers are responsible for ensuring the slots are inactive, and will
+ * not be activated.
+ */
+int edma_free_cont_slots(unsigned slot, int count)
+{
+ unsigned ctlr, slot_to_free;
+ int i;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot < edma_cc[ctlr]->num_channels ||
+ slot >= edma_cc[ctlr]->num_slots ||
+ count < 1)
+ return -EINVAL;
+
+ for (i = slot; i < slot + count; ++i) {
+ ctlr = EDMA_CTLR(i);
+ slot_to_free = EDMA_CHAN_SLOT(i);
+
+ memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
+ &dummy_paramset, PARM_SIZE);
+ clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(edma_free_cont_slots);
+
+/*-----------------------------------------------------------------------*/
+
+/* Parameter RAM operations (i) -- read/write partial slots */
+
+/**
+ * edma_set_src - set initial DMA source address in parameter RAM slot
+ * @slot: parameter RAM slot being configured
+ * @src_port: physical address of source (memory, controller FIFO, etc)
+ * @addressMode: INCR, except in very rare cases
+ * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
+ * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
+ *
+ * Note that the source address is modified during the DMA transfer
+ * according to edma_set_src_index().
+ */
+void edma_set_src(unsigned slot, dma_addr_t src_port,
+ enum address_mode mode, enum fifo_width width)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot < edma_cc[ctlr]->num_slots) {
+ unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
+
+ if (mode) {
+ /* set SAM and program FWID */
+ i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
+ } else {
+ /* clear SAM */
+ i &= ~SAM;
+ }
+ edma_parm_write(ctlr, PARM_OPT, slot, i);
+
+ /* set the source port address
+ in source register of param structure */
+ edma_parm_write(ctlr, PARM_SRC, slot, src_port);
+ }
+}
+EXPORT_SYMBOL(edma_set_src);
+
+/**
+ * edma_set_dest - set initial DMA destination address in parameter RAM slot
+ * @slot: parameter RAM slot being configured
+ * @dest_port: physical address of destination (memory, controller FIFO, etc)
+ * @addressMode: INCR, except in very rare cases
+ * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
+ * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
+ *
+ * Note that the destination address is modified during the DMA transfer
+ * according to edma_set_dest_index().
+ */
+void edma_set_dest(unsigned slot, dma_addr_t dest_port,
+ enum address_mode mode, enum fifo_width width)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot < edma_cc[ctlr]->num_slots) {
+ unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
+
+ if (mode) {
+ /* set DAM and program FWID */
+ i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
+ } else {
+ /* clear DAM */
+ i &= ~DAM;
+ }
+ edma_parm_write(ctlr, PARM_OPT, slot, i);
+ /* set the destination port address
+ in dest register of param structure */
+ edma_parm_write(ctlr, PARM_DST, slot, dest_port);
+ }
+}
+EXPORT_SYMBOL(edma_set_dest);
+
+/**
+ * edma_get_position - returns the current transfer points
+ * @slot: parameter RAM slot being examined
+ * @src: pointer to source port position
+ * @dst: pointer to destination port position
+ *
+ * Returns current source and destination addresses for a particular
+ * parameter RAM slot. Its channel should not be active when this is called.
+ */
+void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst)
+{
+ struct edmacc_param temp;
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp);
+ if (src != NULL)
+ *src = temp.src;
+ if (dst != NULL)
+ *dst = temp.dst;
+}
+EXPORT_SYMBOL(edma_get_position);
+
+/**
+ * edma_set_src_index - configure DMA source address indexing
+ * @slot: parameter RAM slot being configured
+ * @src_bidx: byte offset between source arrays in a frame
+ * @src_cidx: byte offset between source frames in a block
+ *
+ * Offsets are specified to support either contiguous or discontiguous
+ * memory transfers, or repeated access to a hardware register, as needed.
+ * When accessing hardware registers, both offsets are normally zero.
+ */
+void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot < edma_cc[ctlr]->num_slots) {
+ edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
+ 0xffff0000, src_bidx);
+ edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
+ 0xffff0000, src_cidx);
+ }
+}
+EXPORT_SYMBOL(edma_set_src_index);
+
+/**
+ * edma_set_dest_index - configure DMA destination address indexing
+ * @slot: parameter RAM slot being configured
+ * @dest_bidx: byte offset between destination arrays in a frame
+ * @dest_cidx: byte offset between destination frames in a block
+ *
+ * Offsets are specified to support either contiguous or discontiguous
+ * memory transfers, or repeated access to a hardware register, as needed.
+ * When accessing hardware registers, both offsets are normally zero.
+ */
+void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot < edma_cc[ctlr]->num_slots) {
+ edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
+ 0x0000ffff, dest_bidx << 16);
+ edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
+ 0x0000ffff, dest_cidx << 16);
+ }
+}
+EXPORT_SYMBOL(edma_set_dest_index);
+
+/**
+ * edma_set_transfer_params - configure DMA transfer parameters
+ * @slot: parameter RAM slot being configured
+ * @acnt: how many bytes per array (at least one)
+ * @bcnt: how many arrays per frame (at least one)
+ * @ccnt: how many frames per block (at least one)
+ * @bcnt_rld: used only for A-Synchronized transfers; this specifies
+ * the value to reload into bcnt when it decrements to zero
+ * @sync_mode: ASYNC or ABSYNC
+ *
+ * See the EDMA3 documentation to understand how to configure and link
+ * transfers using the fields in PaRAM slots. If you are not doing it
+ * all at once with edma_write_slot(), you will use this routine
+ * plus two calls each for source and destination, setting the initial
+ * address and saying how to index that address.
+ *
+ * An example of an A-Synchronized transfer is a serial link using a
+ * single word shift register. In that case, @acnt would be equal to
+ * that word size; the serial controller issues a DMA synchronization
+ * event to transfer each word, and memory access by the DMA transfer
+ * controller will be word-at-a-time.
+ *
+ * An example of an AB-Synchronized transfer is a device using a FIFO.
+ * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
+ * The controller with the FIFO issues DMA synchronization events when
+ * the FIFO threshold is reached, and the DMA transfer controller will
+ * transfer one frame to (or from) the FIFO. It will probably use
+ * efficient burst modes to access memory.
+ */
+void edma_set_transfer_params(unsigned slot,
+ u16 acnt, u16 bcnt, u16 ccnt,
+ u16 bcnt_rld, enum sync_dimension sync_mode)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot < edma_cc[ctlr]->num_slots) {
+ edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
+ 0x0000ffff, bcnt_rld << 16);
+ if (sync_mode == ASYNC)
+ edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
+ else
+ edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
+ /* Set the acount, bcount, ccount registers */
+ edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
+ edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
+ }
+}
+EXPORT_SYMBOL(edma_set_transfer_params);
+
+/**
+ * edma_link - link one parameter RAM slot to another
+ * @from: parameter RAM slot originating the link
+ * @to: parameter RAM slot which is the link target
+ *
+ * The originating slot should not be part of any active DMA transfer.
+ */
+void edma_link(unsigned from, unsigned to)
+{
+ unsigned ctlr_from, ctlr_to;
+
+ ctlr_from = EDMA_CTLR(from);
+ from = EDMA_CHAN_SLOT(from);
+ ctlr_to = EDMA_CTLR(to);
+ to = EDMA_CHAN_SLOT(to);
+
+ if (from >= edma_cc[ctlr_from]->num_slots)
+ return;
+ if (to >= edma_cc[ctlr_to]->num_slots)
+ return;
+ edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
+ PARM_OFFSET(to));
+}
+EXPORT_SYMBOL(edma_link);
+
+/**
+ * edma_unlink - cut link from one parameter RAM slot
+ * @from: parameter RAM slot originating the link
+ *
+ * The originating slot should not be part of any active DMA transfer.
+ * Its link is set to 0xffff.
+ */
+void edma_unlink(unsigned from)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(from);
+ from = EDMA_CHAN_SLOT(from);
+
+ if (from >= edma_cc[ctlr]->num_slots)
+ return;
+ edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
+}
+EXPORT_SYMBOL(edma_unlink);
+
+/*-----------------------------------------------------------------------*/
+
+/* Parameter RAM operations (ii) -- read/write whole parameter sets */
+
+/**
+ * edma_write_slot - write parameter RAM data for slot
+ * @slot: number of parameter RAM slot being modified
+ * @param: data to be written into parameter RAM slot
+ *
+ * Use this to assign all parameters of a transfer at once. This
+ * allows more efficient setup of transfers than issuing multiple
+ * calls to set up those parameters in small pieces, and provides
+ * complete control over all transfer options.
+ */
+void edma_write_slot(unsigned slot, const struct edmacc_param *param)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot >= edma_cc[ctlr]->num_slots)
+ return;
+ memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
+ PARM_SIZE);
+}
+EXPORT_SYMBOL(edma_write_slot);
+
+/**
+ * edma_read_slot - read parameter RAM data from slot
+ * @slot: number of parameter RAM slot being copied
+ * @param: where to store copy of parameter RAM data
+ *
+ * Use this to read data from a parameter RAM slot, perhaps to
+ * save them as a template for later reuse.
+ */
+void edma_read_slot(unsigned slot, struct edmacc_param *param)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(slot);
+ slot = EDMA_CHAN_SLOT(slot);
+
+ if (slot >= edma_cc[ctlr]->num_slots)
+ return;
+ memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
+ PARM_SIZE);
+}
+EXPORT_SYMBOL(edma_read_slot);
+
+/*-----------------------------------------------------------------------*/
+
+/* Various EDMA channel control operations */
+
+/**
+ * edma_pause - pause dma on a channel
+ * @channel: on which edma_start() has been called
+ *
+ * This temporarily disables EDMA hardware events on the specified channel,
+ * preventing them from triggering new transfers on its behalf
+ */
+void edma_pause(unsigned channel)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(channel);
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel < edma_cc[ctlr]->num_channels) {
+ unsigned int mask = BIT(channel & 0x1f);
+
+ edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
+ }
+}
+EXPORT_SYMBOL(edma_pause);
+
+/**
+ * edma_resume - resumes dma on a paused channel
+ * @channel: on which edma_pause() has been called
+ *
+ * This re-enables EDMA hardware events on the specified channel.
+ */
+void edma_resume(unsigned channel)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(channel);
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel < edma_cc[ctlr]->num_channels) {
+ unsigned int mask = BIT(channel & 0x1f);
+
+ edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
+ }
+}
+EXPORT_SYMBOL(edma_resume);
+
+/**
+ * edma_start - start dma on a channel
+ * @channel: channel being activated
+ *
+ * Channels with event associations will be triggered by their hardware
+ * events, and channels without such associations will be triggered by
+ * software. (At this writing there is no interface for using software
+ * triggers except with channels that don't support hardware triggers.)
+ *
+ * Returns zero on success, else negative errno.
+ */
+int edma_start(unsigned channel)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(channel);
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel < edma_cc[ctlr]->num_channels) {
+ int j = channel >> 5;
+ unsigned int mask = BIT(channel & 0x1f);
+
+ /* EDMA channels without event association */
+ if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
+ pr_debug("EDMA: ESR%d %08x\n", j,
+ edma_shadow0_read_array(ctlr, SH_ESR, j));
+ edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
+ return 0;
+ }
+
+ /* EDMA channel with event association */
+ pr_debug("EDMA: ER%d %08x\n", j,
+ edma_shadow0_read_array(ctlr, SH_ER, j));
+ /* Clear any pending event or error */
+ edma_write_array(ctlr, EDMA_ECR, j, mask);
+ edma_write_array(ctlr, EDMA_EMCR, j, mask);
+ /* Clear any SER */
+ edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
+ edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
+ pr_debug("EDMA: EER%d %08x\n", j,
+ edma_shadow0_read_array(ctlr, SH_EER, j));
+ return 0;
+ }
+
+ return -EINVAL;
+}
+EXPORT_SYMBOL(edma_start);
+
+/**
+ * edma_stop - stops dma on the channel passed
+ * @channel: channel being deactivated
+ *
+ * When @lch is a channel, any active transfer is paused and
+ * all pending hardware events are cleared. The current transfer
+ * may not be resumed, and the channel's Parameter RAM should be
+ * reinitialized before being reused.
+ */
+void edma_stop(unsigned channel)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(channel);
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel < edma_cc[ctlr]->num_channels) {
+ int j = channel >> 5;
+ unsigned int mask = BIT(channel & 0x1f);
+
+ edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
+ edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
+ edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
+ edma_write_array(ctlr, EDMA_EMCR, j, mask);
+
+ pr_debug("EDMA: EER%d %08x\n", j,
+ edma_shadow0_read_array(ctlr, SH_EER, j));
+
+ /* REVISIT: consider guarding against inappropriate event
+ * chaining by overwriting with dummy_paramset.
+ */
+ }
+}
+EXPORT_SYMBOL(edma_stop);
+
+/******************************************************************************
+ *
+ * It cleans ParamEntry qand bring back EDMA to initial state if media has
+ * been removed before EDMA has finished.It is usedful for removable media.
+ * Arguments:
+ * ch_no - channel no
+ *
+ * Return: zero on success, or corresponding error no on failure
+ *
+ * FIXME this should not be needed ... edma_stop() should suffice.
+ *
+ *****************************************************************************/
+
+void edma_clean_channel(unsigned channel)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(channel);
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel < edma_cc[ctlr]->num_channels) {
+ int j = (channel >> 5);
+ unsigned int mask = BIT(channel & 0x1f);
+
+ pr_debug("EDMA: EMR%d %08x\n", j,
+ edma_read_array(ctlr, EDMA_EMR, j));
+ edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
+ /* Clear the corresponding EMR bits */
+ edma_write_array(ctlr, EDMA_EMCR, j, mask);
+ /* Clear any SER */
+ edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
+ edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
+ }
+}
+EXPORT_SYMBOL(edma_clean_channel);
+
+/*
+ * edma_clear_event - clear an outstanding event on the DMA channel
+ * Arguments:
+ * channel - channel number
+ */
+void edma_clear_event(unsigned channel)
+{
+ unsigned ctlr;
+
+ ctlr = EDMA_CTLR(channel);
+ channel = EDMA_CHAN_SLOT(channel);
+
+ if (channel >= edma_cc[ctlr]->num_channels)
+ return;
+ if (channel < 32)
+ edma_write(ctlr, EDMA_ECR, BIT(channel));
+ else
+ edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
+}
+EXPORT_SYMBOL(edma_clear_event);
+
+/*-----------------------------------------------------------------------*/
+
+static int __init edma_probe(struct platform_device *pdev)
+{
+ struct edma_soc_info **info = pdev->dev.platform_data;
+ const s8 (*queue_priority_mapping)[2];
+ const s8 (*queue_tc_mapping)[2];
+ int i, j, off, ln, found = 0;
+ int status = -1;
+ const s16 (*rsv_chans)[2];
+ const s16 (*rsv_slots)[2];
+ int irq[EDMA_MAX_CC] = {0, 0};
+ int err_irq[EDMA_MAX_CC] = {0, 0};
+ struct resource *r[EDMA_MAX_CC] = {NULL};
+ resource_size_t len[EDMA_MAX_CC];
+ char res_name[10];
+ char irq_name[10];
+
+ if (!info)
+ return -ENODEV;
+
+ for (j = 0; j < EDMA_MAX_CC; j++) {
+ sprintf(res_name, "edma_cc%d", j);
+ r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ res_name);
+ if (!r[j] || !info[j]) {
+ if (found)
+ break;
+ else
+ return -ENODEV;
+ } else {
+ found = 1;
+ }
+
+ len[j] = resource_size(r[j]);
+
+ r[j] = request_mem_region(r[j]->start, len[j],
+ dev_name(&pdev->dev));
+ if (!r[j]) {
+ status = -EBUSY;
+ goto fail1;
+ }
+
+ edmacc_regs_base[j] = ioremap(r[j]->start, len[j]);
+ if (!edmacc_regs_base[j]) {
+ status = -EBUSY;
+ goto fail1;
+ }
+
+ edma_cc[j] = kzalloc(sizeof(struct edma), GFP_KERNEL);
+ if (!edma_cc[j]) {
+ status = -ENOMEM;
+ goto fail1;
+ }
+
+ edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel,
+ EDMA_MAX_DMACH);
+ edma_cc[j]->num_slots = min_t(unsigned, info[j]->n_slot,
+ EDMA_MAX_PARAMENTRY);
+ edma_cc[j]->num_cc = min_t(unsigned, info[j]->n_cc,
+ EDMA_MAX_CC);
+
+ edma_cc[j]->default_queue = info[j]->default_queue;
+
+ dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
+ edmacc_regs_base[j]);
+
+ for (i = 0; i < edma_cc[j]->num_slots; i++)
+ memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
+ &dummy_paramset, PARM_SIZE);
+
+ /* Mark all channels as unused */
+ memset(edma_cc[j]->edma_unused, 0xff,
+ sizeof(edma_cc[j]->edma_unused));
+
+ if (info[j]->rsv) {
+
+ /* Clear the reserved channels in unused list */
+ rsv_chans = info[j]->rsv->rsv_chans;
+ if (rsv_chans) {
+ for (i = 0; rsv_chans[i][0] != -1; i++) {
+ off = rsv_chans[i][0];
+ ln = rsv_chans[i][1];
+ clear_bits(off, ln,
+ edma_cc[j]->edma_unused);
+ }
+ }
+
+ /* Set the reserved slots in inuse list */
+ rsv_slots = info[j]->rsv->rsv_slots;
+ if (rsv_slots) {
+ for (i = 0; rsv_slots[i][0] != -1; i++) {
+ off = rsv_slots[i][0];
+ ln = rsv_slots[i][1];
+ set_bits(off, ln,
+ edma_cc[j]->edma_inuse);
+ }
+ }
+ }
+
+ sprintf(irq_name, "edma%d", j);
+ irq[j] = platform_get_irq_byname(pdev, irq_name);
+ edma_cc[j]->irq_res_start = irq[j];
+ status = request_irq(irq[j], dma_irq_handler, 0, "edma",
+ &pdev->dev);
+ if (status < 0) {
+ dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
+ irq[j], status);
+ goto fail;
+ }
+
+ sprintf(irq_name, "edma%d_err", j);
+ err_irq[j] = platform_get_irq_byname(pdev, irq_name);
+ edma_cc[j]->irq_res_end = err_irq[j];
+ status = request_irq(err_irq[j], dma_ccerr_handler, 0,
+ "edma_error", &pdev->dev);
+ if (status < 0) {
+ dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
+ err_irq[j], status);
+ goto fail;
+ }
+
+ for (i = 0; i < edma_cc[j]->num_channels; i++)
+ map_dmach_queue(j, i, info[j]->default_queue);
+
+ queue_tc_mapping = info[j]->queue_tc_mapping;
+ queue_priority_mapping = info[j]->queue_priority_mapping;
+
+ /* Event queue to TC mapping */
+ for (i = 0; queue_tc_mapping[i][0] != -1; i++)
+ map_queue_tc(j, queue_tc_mapping[i][0],
+ queue_tc_mapping[i][1]);
+
+ /* Event queue priority mapping */
+ for (i = 0; queue_priority_mapping[i][0] != -1; i++)
+ assign_priority_to_queue(j,
+ queue_priority_mapping[i][0],
+ queue_priority_mapping[i][1]);
+
+ /* Map the channel to param entry if channel mapping logic
+ * exist
+ */
+ if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
+ map_dmach_param(j);
+
+ for (i = 0; i < info[j]->n_region; i++) {
+ edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
+ edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
+ edma_write_array(j, EDMA_QRAE, i, 0x0);
+ }
+ arch_num_cc++;
+ }
+
+ if (tc_errs_handled) {
+ status = request_irq(IRQ_TCERRINT0, dma_tc0err_handler, 0,
+ "edma_tc0", &pdev->dev);
+ if (status < 0) {
+ dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
+ IRQ_TCERRINT0, status);
+ return status;
+ }
+ status = request_irq(IRQ_TCERRINT, dma_tc1err_handler, 0,
+ "edma_tc1", &pdev->dev);
+ if (status < 0) {
+ dev_dbg(&pdev->dev, "request_irq %d --> %d\n",
+ IRQ_TCERRINT, status);
+ return status;
+ }
+ }
+
+ return 0;
+
+fail:
+ for (i = 0; i < EDMA_MAX_CC; i++) {
+ if (err_irq[i])
+ free_irq(err_irq[i], &pdev->dev);
+ if (irq[i])
+ free_irq(irq[i], &pdev->dev);
+ }
+fail1:
+ for (i = 0; i < EDMA_MAX_CC; i++) {
+ if (r[i])
+ release_mem_region(r[i]->start, len[i]);
+ if (edmacc_regs_base[i])
+ iounmap(edmacc_regs_base[i]);
+ kfree(edma_cc[i]);
+ }
+ return status;
+}
+
+
+static struct platform_driver edma_driver = {
+ .driver.name = "edma",
+};
+
+static int __init edma_init(void)
+{
+ return platform_driver_probe(&edma_driver, edma_probe);
+}
+arch_initcall(edma_init);
+
diff --git a/arch/arm/include/asm/mach/edma.h b/arch/arm/include/asm/mach/edma.h
new file mode 100644
index 0000000..7e84c90
--- /dev/null
+++ b/arch/arm/include/asm/mach/edma.h
@@ -0,0 +1,267 @@
+/*
+ * TI DAVINCI dma definitions
+ *
+ * Copyright (C) 2006-2009 Texas Instruments.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+/*
+ * This EDMA3 programming framework exposes two basic kinds of resource:
+ *
+ * Channel Triggers transfers, usually from a hardware event but
+ * also manually or by "chaining" from DMA completions.
+ * Each channel is coupled to a Parameter RAM (PaRAM) slot.
+ *
+ * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
+ * "set"), source and destination addresses, a link to a
+ * next PaRAM slot (if any), options for the transfer, and
+ * instructions for updating those addresses. There are
+ * more than twice as many slots as event channels.
+ *
+ * Each PaRAM set describes a sequence of transfers, either for one large
+ * buffer or for several discontiguous smaller buffers. An EDMA transfer
+ * is driven only from a channel, which performs the transfers specified
+ * in its PaRAM slot until there are no more transfers. When that last
+ * transfer completes, the "link" field may be used to reload the channel's
+ * PaRAM slot with a new transfer descriptor.
+ *
+ * The EDMA Channel Controller (CC) maps requests from channels into physical
+ * Transfer Controller (TC) requests when the channel triggers (by hardware
+ * or software events, or by chaining). The two physical DMA channels provided
+ * by the TCs are thus shared by many logical channels.
+ *
+ * DaVinci hardware also has a "QDMA" mechanism which is not currently
+ * supported through this interface. (DSP firmware uses it though.)
+ */
+
+#ifndef EDMA_H_
+#define EDMA_H_
+
+/* PaRAM slots are laid out like this */
+struct edmacc_param {
+ unsigned int opt;
+ unsigned int src;
+ unsigned int a_b_cnt;
+ unsigned int dst;
+ unsigned int src_dst_bidx;
+ unsigned int link_bcntrld;
+ unsigned int src_dst_cidx;
+ unsigned int ccnt;
+};
+
+#define CCINT0_INTERRUPT 16
+#define CCERRINT_INTERRUPT 17
+#define TCERRINT0_INTERRUPT 18
+#define TCERRINT1_INTERRUPT 19
+
+/* fields in edmacc_param.opt */
+#define SAM BIT(0)
+#define DAM BIT(1)
+#define SYNCDIM BIT(2)
+#define STATIC BIT(3)
+#define EDMA_FWID (0x07 << 8)
+#define TCCMODE BIT(11)
+#define EDMA_TCC(t) ((t) << 12)
+#define TCINTEN BIT(20)
+#define ITCINTEN BIT(21)
+#define TCCHEN BIT(22)
+#define ITCCHEN BIT(23)
+
+#define TRWORD (0x7<<2)
+#define PAENTRY (0x1ff<<5)
+
+/* Drivers should avoid using these symbolic names for dm644x
+ * channels, and use platform_device IORESOURCE_DMA resources
+ * instead. (Other DaVinci chips have different peripherals
+ * and thus have different DMA channel mappings.)
+ */
+#define DAVINCI_DMA_MCBSP_TX 2
+#define DAVINCI_DMA_MCBSP_RX 3
+#define DAVINCI_DMA_VPSS_HIST 4
+#define DAVINCI_DMA_VPSS_H3A 5
+#define DAVINCI_DMA_VPSS_PRVU 6
+#define DAVINCI_DMA_VPSS_RSZ 7
+#define DAVINCI_DMA_IMCOP_IMXINT 8
+#define DAVINCI_DMA_IMCOP_VLCDINT 9
+#define DAVINCI_DMA_IMCO_PASQINT 10
+#define DAVINCI_DMA_IMCOP_DSQINT 11
+#define DAVINCI_DMA_SPI_SPIX 16
+#define DAVINCI_DMA_SPI_SPIR 17
+#define DAVINCI_DMA_UART0_URXEVT0 18
+#define DAVINCI_DMA_UART0_UTXEVT0 19
+#define DAVINCI_DMA_UART1_URXEVT1 20
+#define DAVINCI_DMA_UART1_UTXEVT1 21
+#define DAVINCI_DMA_UART2_URXEVT2 22
+#define DAVINCI_DMA_UART2_UTXEVT2 23
+#define DAVINCI_DMA_MEMSTK_MSEVT 24
+#define DAVINCI_DMA_MMCRXEVT 26
+#define DAVINCI_DMA_MMCTXEVT 27
+#define DAVINCI_DMA_I2C_ICREVT 28
+#define DAVINCI_DMA_I2C_ICXEVT 29
+#define DAVINCI_DMA_GPIO_GPINT0 32
+#define DAVINCI_DMA_GPIO_GPINT1 33
+#define DAVINCI_DMA_GPIO_GPINT2 34
+#define DAVINCI_DMA_GPIO_GPINT3 35
+#define DAVINCI_DMA_GPIO_GPINT4 36
+#define DAVINCI_DMA_GPIO_GPINT5 37
+#define DAVINCI_DMA_GPIO_GPINT6 38
+#define DAVINCI_DMA_GPIO_GPINT7 39
+#define DAVINCI_DMA_GPIO_GPBNKINT0 40
+#define DAVINCI_DMA_GPIO_GPBNKINT1 41
+#define DAVINCI_DMA_GPIO_GPBNKINT2 42
+#define DAVINCI_DMA_GPIO_GPBNKINT3 43
+#define DAVINCI_DMA_GPIO_GPBNKINT4 44
+#define DAVINCI_DMA_TIMER0_TINT0 48
+#define DAVINCI_DMA_TIMER1_TINT1 49
+#define DAVINCI_DMA_TIMER2_TINT2 50
+#define DAVINCI_DMA_TIMER3_TINT3 51
+#define DAVINCI_DMA_PWM0 52
+#define DAVINCI_DMA_PWM1 53
+#define DAVINCI_DMA_PWM2 54
+
+/* DA830 specific EDMA3 information */
+#define EDMA_DA830_NUM_DMACH 32
+#define EDMA_DA830_NUM_TCC 32
+#define EDMA_DA830_NUM_PARAMENTRY 128
+#define EDMA_DA830_NUM_EVQUE 2
+#define EDMA_DA830_NUM_TC 2
+#define EDMA_DA830_CHMAP_EXIST 0
+#define EDMA_DA830_NUM_REGIONS 4
+#define DA830_DMACH2EVENT_MAP0 0x000FC03Fu
+#define DA830_DMACH2EVENT_MAP1 0x00000000u
+#define DA830_EDMA_ARM_OWN 0x30FFCCFFu
+
+/*ch_status paramater of callback function possible values*/
+#define DMA_COMPLETE 1
+#define DMA_CC_ERROR 2
+#define DMA_TC1_ERROR 3
+#define DMA_TC2_ERROR 4
+
+enum address_mode {
+ INCR = 0,
+ FIFO = 1
+};
+
+enum fifo_width {
+ W8BIT = 0,
+ W16BIT = 1,
+ W32BIT = 2,
+ W64BIT = 3,
+ W128BIT = 4,
+ W256BIT = 5
+};
+
+enum dma_event_q {
+ EVENTQ_0 = 0,
+ EVENTQ_1 = 1,
+ EVENTQ_2 = 2,
+ EVENTQ_3 = 3,
+ EVENTQ_DEFAULT = -1
+};
+
+enum sync_dimension {
+ ASYNC = 0,
+ ABSYNC = 1
+};
+
+#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
+#define EDMA_CTLR(i) ((i) >> 16)
+#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
+
+#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
+#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
+#define EDMA_CONT_PARAMS_ANY 1001
+#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
+#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
+
+#define EDMA_MAX_CC 2
+
+/* alloc/free DMA channels and their dedicated parameter RAM slots */
+int edma_alloc_channel(int channel,
+ void (*callback)(unsigned channel, u16 ch_status, void *data),
+ void *data, enum dma_event_q);
+void edma_free_channel(unsigned channel);
+
+/* alloc/free parameter RAM slots */
+int edma_alloc_slot(unsigned ctlr, int slot);
+void edma_free_slot(unsigned slot);
+
+/* alloc/free a set of contiguous parameter RAM slots */
+int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
+int edma_free_cont_slots(unsigned slot, int count);
+
+/* calls that operate on part of a parameter RAM slot */
+void edma_set_src(unsigned slot, dma_addr_t src_port,
+ enum address_mode mode, enum fifo_width);
+void edma_set_dest(unsigned slot, dma_addr_t dest_port,
+ enum address_mode mode, enum fifo_width);
+void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst);
+void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
+void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
+void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
+ u16 bcnt_rld, enum sync_dimension sync_mode);
+void edma_link(unsigned from, unsigned to);
+void edma_unlink(unsigned from);
+
+/* calls that operate on an entire parameter RAM slot */
+void edma_write_slot(unsigned slot, const struct edmacc_param *params);
+void edma_read_slot(unsigned slot, struct edmacc_param *params);
+
+/* channel control operations */
+int edma_start(unsigned channel);
+void edma_stop(unsigned channel);
+void edma_clean_channel(unsigned channel);
+void edma_clear_event(unsigned channel);
+void edma_pause(unsigned channel);
+void edma_resume(unsigned channel);
+
+struct edma_rsv_info {
+
+ const s16 (*rsv_chans)[2];
+ const s16 (*rsv_slots)[2];
+};
+
+/* platform_data for EDMA driver */
+struct edma_soc_info {
+
+ /* how many dma resources of each type */
+ unsigned n_channel;
+ unsigned n_region;
+ unsigned n_slot;
+ unsigned n_tc;
+ unsigned n_cc;
+ /*
+ * Default queue is expected to be a low-priority queue.
+ * This way, long transfers on the default queue started
+ * by the codec engine will not cause audio defects.
+ */
+ enum dma_event_q default_queue;
+
+ /* Resource reservation for other cores */
+ struct edma_rsv_info *rsv;
+
+ const s8 (*queue_tc_mapping)[2];
+ const s8 (*queue_priority_mapping)[2];
+};
+
+#endif
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 2227eff..97c639e 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -5,7 +5,7 @@
# Common objects
obj-y := time.o clock.o serial.o psc.o \
- dma.o usb.o common.o sram.o aemif.o
+ usb.o common.o sram.o aemif.o
obj-$(CONFIG_DAVINCI_MUX) += mux.o
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index d2f96662..3407c20 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -14,12 +14,13 @@
#include <linux/dma-mapping.h>
#include <linux/io.h>
+#include <asm/mach/edma.h>
+
#include <mach/hardware.h>
#include <mach/i2c.h>
#include <mach/irqs.h>
#include <mach/cputype.h>
#include <mach/mux.h>
-#include <mach/edma.h>
#include <mach/mmc.h>
#include <mach/time.h>
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 678cd99..c7a432b 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -16,10 +16,10 @@
#include <linux/spi/spi.h>
+#include <asm/mach/edma.h>
#include <asm/mach/map.h>
#include <mach/cputype.h>
-#include <mach/edma.h>
#include <mach/psc.h>
#include <mach/mux.h>
#include <mach/irqs.h>
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index a50d49de..8e22ee8 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -19,10 +19,10 @@
#include <linux/dma-mapping.h>
#include <linux/spi/spi.h>
+#include <asm/mach/edma.h>
#include <asm/mach/map.h>
#include <mach/cputype.h>
-#include <mach/edma.h>
#include <mach/psc.h>
#include <mach/mux.h>
#include <mach/irqs.h>
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index c8b8666..562e51f 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -13,10 +13,10 @@
#include <linux/serial_8250.h>
#include <linux/platform_device.h>
+#include <asm/mach/edma.h>
#include <asm/mach/map.h>
#include <mach/cputype.h>
-#include <mach/edma.h>
#include <mach/irqs.h>
#include <mach/psc.h>
#include <mach/mux.h>
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 9eb87c1..2fa4b5b 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -14,10 +14,10 @@
#include <linux/serial_8250.h>
#include <linux/platform_device.h>
+#include <asm/mach/edma.h>
#include <asm/mach/map.h>
#include <mach/cputype.h>
-#include <mach/edma.h>
#include <mach/irqs.h>
#include <mach/psc.h>
#include <mach/mux.h>
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
deleted file mode 100644
index a685e97..0000000
--- a/arch/arm/mach-davinci/dma.c
+++ /dev/null
@@ -1,1588 +0,0 @@
-/*
- * EDMA3 support for DaVinci
- *
- * Copyright (C) 2006-2009 Texas Instruments.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-
-#include <mach/edma.h>
-
-/* Offsets matching "struct edmacc_param" */
-#define PARM_OPT 0x00
-#define PARM_SRC 0x04
-#define PARM_A_B_CNT 0x08
-#define PARM_DST 0x0c
-#define PARM_SRC_DST_BIDX 0x10
-#define PARM_LINK_BCNTRLD 0x14
-#define PARM_SRC_DST_CIDX 0x18
-#define PARM_CCNT 0x1c
-
-#define PARM_SIZE 0x20
-
-/* Offsets for EDMA CC global channel registers and their shadows */
-#define SH_ER 0x00 /* 64 bits */
-#define SH_ECR 0x08 /* 64 bits */
-#define SH_ESR 0x10 /* 64 bits */
-#define SH_CER 0x18 /* 64 bits */
-#define SH_EER 0x20 /* 64 bits */
-#define SH_EECR 0x28 /* 64 bits */
-#define SH_EESR 0x30 /* 64 bits */
-#define SH_SER 0x38 /* 64 bits */
-#define SH_SECR 0x40 /* 64 bits */
-#define SH_IER 0x50 /* 64 bits */
-#define SH_IECR 0x58 /* 64 bits */
-#define SH_IESR 0x60 /* 64 bits */
-#define SH_IPR 0x68 /* 64 bits */
-#define SH_ICR 0x70 /* 64 bits */
-#define SH_IEVAL 0x78
-#define SH_QER 0x80
-#define SH_QEER 0x84
-#define SH_QEECR 0x88
-#define SH_QEESR 0x8c
-#define SH_QSER 0x90
-#define SH_QSECR 0x94
-#define SH_SIZE 0x200
-
-/* Offsets for EDMA CC global registers */
-#define EDMA_REV 0x0000
-#define EDMA_CCCFG 0x0004
-#define EDMA_QCHMAP 0x0200 /* 8 registers */
-#define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
-#define EDMA_QDMAQNUM 0x0260
-#define EDMA_QUETCMAP 0x0280
-#define EDMA_QUEPRI 0x0284
-#define EDMA_EMR 0x0300 /* 64 bits */
-#define EDMA_EMCR 0x0308 /* 64 bits */
-#define EDMA_QEMR 0x0310
-#define EDMA_QEMCR 0x0314
-#define EDMA_CCERR 0x0318
-#define EDMA_CCERRCLR 0x031c
-#define EDMA_EEVAL 0x0320
-#define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
-#define EDMA_QRAE 0x0380 /* 4 registers */
-#define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
-#define EDMA_QSTAT 0x0600 /* 2 registers */
-#define EDMA_QWMTHRA 0x0620
-#define EDMA_QWMTHRB 0x0624
-#define EDMA_CCSTAT 0x0640
-
-#define EDMA_M 0x1000 /* global channel registers */
-#define EDMA_ECR 0x1008
-#define EDMA_ECRH 0x100C
-#define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */
-#define EDMA_PARM 0x4000 /* 128 param entries */
-
-#define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
-
-#define EDMA_DCHMAP 0x0100 /* 64 registers */
-#define CHMAP_EXIST BIT(24)
-
-#define EDMA_MAX_DMACH 64
-#define EDMA_MAX_PARAMENTRY 512
-
-/*****************************************************************************/
-
-static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
-
-static inline unsigned int edma_read(unsigned ctlr, int offset)
-{
- return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
-}
-
-static inline void edma_write(unsigned ctlr, int offset, int val)
-{
- __raw_writel(val, edmacc_regs_base[ctlr] + offset);
-}
-static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
- unsigned or)
-{
- unsigned val = edma_read(ctlr, offset);
- val &= and;
- val |= or;
- edma_write(ctlr, offset, val);
-}
-static inline void edma_and(unsigned ctlr, int offset, unsigned and)
-{
- unsigned val = edma_read(ctlr, offset);
- val &= and;
- edma_write(ctlr, offset, val);
-}
-static inline void edma_or(unsigned ctlr, int offset, unsigned or)
-{
- unsigned val = edma_read(ctlr, offset);
- val |= or;
- edma_write(ctlr, offset, val);
-}
-static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
-{
- return edma_read(ctlr, offset + (i << 2));
-}
-static inline void edma_write_array(unsigned ctlr, int offset, int i,
- unsigned val)
-{
- edma_write(ctlr, offset + (i << 2), val);
-}
-static inline void edma_modify_array(unsigned ctlr, int offset, int i,
- unsigned and, unsigned or)
-{
- edma_modify(ctlr, offset + (i << 2), and, or);
-}
-static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
-{
- edma_or(ctlr, offset + (i << 2), or);
-}
-static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
- unsigned or)
-{
- edma_or(ctlr, offset + ((i*2 + j) << 2), or);
-}
-static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
- unsigned val)
-{
- edma_write(ctlr, offset + ((i*2 + j) << 2), val);
-}
-static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
-{
- return edma_read(ctlr, EDMA_SHADOW0 + offset);
-}
-static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
- int i)
-{
- return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
-}
-static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
-{
- edma_write(ctlr, EDMA_SHADOW0 + offset, val);
-}
-static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
- unsigned val)
-{
- edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
-}
-static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
- int param_no)
-{
- return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
-}
-static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
- unsigned val)
-{
- edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
-}
-static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
- unsigned and, unsigned or)
-{
- edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
-}
-static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
- unsigned and)
-{
- edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
-}
-static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
- unsigned or)
-{
- edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
-}
-
-static inline void set_bits(int offset, int len, unsigned long *p)
-{
- for (; len > 0; len--)
- set_bit(offset + (len - 1), p);
-}
-
-static inline void clear_bits(int offset, int len, unsigned long *p)
-{
- for (; len > 0; len--)
- clear_bit(offset + (len - 1), p);
-}
-
-/*****************************************************************************/
-
-/* actual number of DMA channels and slots on this silicon */
-struct edma {
- /* how many dma resources of each type */
- unsigned num_channels;
- unsigned num_region;
- unsigned num_slots;
- unsigned num_tc;
- unsigned num_cc;
- enum dma_event_q default_queue;
-
- /* list of channels with no even trigger; terminated by "-1" */
- const s8 *noevent;
-
- /* The edma_inuse bit for each PaRAM slot is clear unless the
- * channel is in use ... by ARM or DSP, for QDMA, or whatever.
- */
- DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
-
- /* The edma_unused bit for each channel is clear unless
- * it is not being used on this platform. It uses a bit
- * of SOC-specific initialization code.
- */
- DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
-
- unsigned irq_res_start;
- unsigned irq_res_end;
-
- struct dma_interrupt_data {
- void (*callback)(unsigned channel, unsigned short ch_status,
- void *data);
- void *data;
- } intr_data[EDMA_MAX_DMACH];
-};
-
-static struct edma *edma_cc[EDMA_MAX_CC];
-static int arch_num_cc;
-
-/* dummy param set used to (re)initialize parameter RAM slots */
-static const struct edmacc_param dummy_paramset = {
- .link_bcntrld = 0xffff,
- .ccnt = 1,
-};
-
-/*****************************************************************************/
-
-static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
- enum dma_event_q queue_no)
-{
- int bit = (ch_no & 0x7) * 4;
-
- /* default to low priority queue */
- if (queue_no == EVENTQ_DEFAULT)
- queue_no = edma_cc[ctlr]->default_queue;
-
- queue_no &= 7;
- edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
- ~(0x7 << bit), queue_no << bit);
-}
-
-static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no)
-{
- int bit = queue_no * 4;
- edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
-}
-
-static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
- int priority)
-{
- int bit = queue_no * 4;
- edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
- ((priority & 0x7) << bit));
-}
-
-/**
- * map_dmach_param - Maps channel number to param entry number
- *
- * This maps the dma channel number to param entry numberter. In
- * other words using the DMA channel mapping registers a param entry
- * can be mapped to any channel
- *
- * Callers are responsible for ensuring the channel mapping logic is
- * included in that particular EDMA variant (Eg : dm646x)
- *
- */
-static void __init map_dmach_param(unsigned ctlr)
-{
- int i;
- for (i = 0; i < EDMA_MAX_DMACH; i++)
- edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
-}
-
-static inline void
-setup_dma_interrupt(unsigned lch,
- void (*callback)(unsigned channel, u16 ch_status, void *data),
- void *data)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(lch);
- lch = EDMA_CHAN_SLOT(lch);
-
- if (!callback)
- edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
- BIT(lch & 0x1f));
-
- edma_cc[ctlr]->intr_data[lch].callback = callback;
- edma_cc[ctlr]->intr_data[lch].data = data;
-
- if (callback) {
- edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
- BIT(lch & 0x1f));
- edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
- BIT(lch & 0x1f));
- }
-}
-
-static int irq2ctlr(int irq)
-{
- if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
- return 0;
- else if (irq >= edma_cc[1]->irq_res_start &&
- irq <= edma_cc[1]->irq_res_end)
- return 1;
-
- return -1;
-}
-
-/******************************************************************************
- *
- * DMA interrupt handler
- *
- *****************************************************************************/
-static irqreturn_t dma_irq_handler(int irq, void *data)
-{
- int ctlr;
- u32 sh_ier;
- u32 sh_ipr;
- u32 bank;
-
- ctlr = irq2ctlr(irq);
- if (ctlr < 0)
- return IRQ_NONE;
-
- dev_dbg(data, "dma_irq_handler\n");
-
- sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0);
- if (!sh_ipr) {
- sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1);
- if (!sh_ipr)
- return IRQ_NONE;
- sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1);
- bank = 1;
- } else {
- sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0);
- bank = 0;
- }
-
- do {
- u32 slot;
- u32 channel;
-
- dev_dbg(data, "IPR%d %08x\n", bank, sh_ipr);
-
- slot = __ffs(sh_ipr);
- sh_ipr &= ~(BIT(slot));
-
- if (sh_ier & BIT(slot)) {
- channel = (bank << 5) | slot;
- /* Clear the corresponding IPR bits */
- edma_shadow0_write_array(ctlr, SH_ICR, bank,
- BIT(slot));
- if (edma_cc[ctlr]->intr_data[channel].callback)
- edma_cc[ctlr]->intr_data[channel].callback(
- channel, DMA_COMPLETE,
- edma_cc[ctlr]->intr_data[channel].data);
- }
- } while (sh_ipr);
-
- edma_shadow0_write(ctlr, SH_IEVAL, 1);
- return IRQ_HANDLED;
-}
-
-/******************************************************************************
- *
- * DMA error interrupt handler
- *
- *****************************************************************************/
-static irqreturn_t dma_ccerr_handler(int irq, void *data)
-{
- int i;
- int ctlr;
- unsigned int cnt = 0;
-
- ctlr = irq2ctlr(irq);
- if (ctlr < 0)
- return IRQ_NONE;
-
- dev_dbg(data, "dma_ccerr_handler\n");
-
- if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
- (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
- (edma_read(ctlr, EDMA_QEMR) == 0) &&
- (edma_read(ctlr, EDMA_CCERR) == 0))
- return IRQ_NONE;
-
- while (1) {
- int j = -1;
- if (edma_read_array(ctlr, EDMA_EMR, 0))
- j = 0;
- else if (edma_read_array(ctlr, EDMA_EMR, 1))
- j = 1;
- if (j >= 0) {
- dev_dbg(data, "EMR%d %08x\n", j,
- edma_read_array(ctlr, EDMA_EMR, j));
- for (i = 0; i < 32; i++) {
- int k = (j << 5) + i;
- if (edma_read_array(ctlr, EDMA_EMR, j) &
- BIT(i)) {
- /* Clear the corresponding EMR bits */
- edma_write_array(ctlr, EDMA_EMCR, j,
- BIT(i));
- /* Clear any SER */
- edma_shadow0_write_array(ctlr, SH_SECR,
- j, BIT(i));
- if (edma_cc[ctlr]->intr_data[k].
- callback) {
- edma_cc[ctlr]->intr_data[k].
- callback(k,
- DMA_CC_ERROR,
- edma_cc[ctlr]->intr_data
- [k].data);
- }
- }
- }
- } else if (edma_read(ctlr, EDMA_QEMR)) {
- dev_dbg(data, "QEMR %02x\n",
- edma_read(ctlr, EDMA_QEMR));
- for (i = 0; i < 8; i++) {
- if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
- /* Clear the corresponding IPR bits */
- edma_write(ctlr, EDMA_QEMCR, BIT(i));
- edma_shadow0_write(ctlr, SH_QSECR,
- BIT(i));
-
- /* NOTE: not reported!! */
- }
- }
- } else if (edma_read(ctlr, EDMA_CCERR)) {
- dev_dbg(data, "CCERR %08x\n",
- edma_read(ctlr, EDMA_CCERR));
- /* FIXME: CCERR.BIT(16) ignored! much better
- * to just write CCERRCLR with CCERR value...
- */
- for (i = 0; i < 8; i++) {
- if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
- /* Clear the corresponding IPR bits */
- edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
-
- /* NOTE: not reported!! */
- }
- }
- }
- if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
- (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
- (edma_read(ctlr, EDMA_QEMR) == 0) &&
- (edma_read(ctlr, EDMA_CCERR) == 0))
- break;
- cnt++;
- if (cnt > 10)
- break;
- }
- edma_write(ctlr, EDMA_EEVAL, 1);
- return IRQ_HANDLED;
-}
-
-/******************************************************************************
- *
- * Transfer controller error interrupt handlers
- *
- *****************************************************************************/
-
-#define tc_errs_handled false /* disabled as long as they're NOPs */
-
-static irqreturn_t dma_tc0err_handler(int irq, void *data)
-{
- dev_dbg(data, "dma_tc0err_handler\n");
- return IRQ_HANDLED;
-}
-
-static irqreturn_t dma_tc1err_handler(int irq, void *data)
-{
- dev_dbg(data, "dma_tc1err_handler\n");
- return IRQ_HANDLED;
-}
-
-static int reserve_contiguous_slots(int ctlr, unsigned int id,
- unsigned int num_slots,
- unsigned int start_slot)
-{
- int i, j;
- unsigned int count = num_slots;
- int stop_slot = start_slot;
- DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
-
- for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
- j = EDMA_CHAN_SLOT(i);
- if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
- /* Record our current beginning slot */
- if (count == num_slots)
- stop_slot = i;
-
- count--;
- set_bit(j, tmp_inuse);
-
- if (count == 0)
- break;
- } else {
- clear_bit(j, tmp_inuse);
-
- if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
- stop_slot = i;
- break;
- } else {
- count = num_slots;
- }
- }
- }
-
- /*
- * We have to clear any bits that we set
- * if we run out parameter RAM slots, i.e we do find a set
- * of contiguous parameter RAM slots but do not find the exact number
- * requested as we may reach the total number of parameter RAM slots
- */
- if (i == edma_cc[ctlr]->num_slots)
- stop_slot = i;
-
- j = start_slot;
- for_each_set_bit_from(j, tmp_inuse, stop_slot)
- clear_bit(j, edma_cc[ctlr]->edma_inuse);
-
- if (count)
- return -EBUSY;
-
- for (j = i - num_slots + 1; j <= i; ++j)
- memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),
- &dummy_paramset, PARM_SIZE);
-
- return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
-}
-
-static int prepare_unused_channel_list(struct device *dev, void *data)
-{
- struct platform_device *pdev = to_platform_device(dev);
- int i, ctlr;
-
- for (i = 0; i < pdev->num_resources; i++) {
- if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
- (int)pdev->resource[i].start >= 0) {
- ctlr = EDMA_CTLR(pdev->resource[i].start);
- clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
- edma_cc[ctlr]->edma_unused);
- }
- }
-
- return 0;
-}
-
-/*-----------------------------------------------------------------------*/
-
-static bool unused_chan_list_done;
-
-/* Resource alloc/free: dma channels, parameter RAM slots */
-
-/**
- * edma_alloc_channel - allocate DMA channel and paired parameter RAM
- * @channel: specific channel to allocate; negative for "any unmapped channel"
- * @callback: optional; to be issued on DMA completion or errors
- * @data: passed to callback
- * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
- * Controller (TC) executes requests using this channel. Use
- * EVENTQ_DEFAULT unless you really need a high priority queue.
- *
- * This allocates a DMA channel and its associated parameter RAM slot.
- * The parameter RAM is initialized to hold a dummy transfer.
- *
- * Normal use is to pass a specific channel number as @channel, to make
- * use of hardware events mapped to that channel. When the channel will
- * be used only for software triggering or event chaining, channels not
- * mapped to hardware events (or mapped to unused events) are preferable.
- *
- * DMA transfers start from a channel using edma_start(), or by
- * chaining. When the transfer described in that channel's parameter RAM
- * slot completes, that slot's data may be reloaded through a link.
- *
- * DMA errors are only reported to the @callback associated with the
- * channel driving that transfer, but transfer completion callbacks can
- * be sent to another channel under control of the TCC field in
- * the option word of the transfer's parameter RAM set. Drivers must not
- * use DMA transfer completion callbacks for channels they did not allocate.
- * (The same applies to TCC codes used in transfer chaining.)
- *
- * Returns the number of the channel, else negative errno.
- */
-int edma_alloc_channel(int channel,
- void (*callback)(unsigned channel, u16 ch_status, void *data),
- void *data,
- enum dma_event_q eventq_no)
-{
- unsigned i, done = 0, ctlr = 0;
- int ret = 0;
-
- if (!unused_chan_list_done) {
- /*
- * Scan all the platform devices to find out the EDMA channels
- * used and clear them in the unused list, making the rest
- * available for ARM usage.
- */
- ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
- prepare_unused_channel_list);
- if (ret < 0)
- return ret;
-
- unused_chan_list_done = true;
- }
-
- if (channel >= 0) {
- ctlr = EDMA_CTLR(channel);
- channel = EDMA_CHAN_SLOT(channel);
- }
-
- if (channel < 0) {
- for (i = 0; i < arch_num_cc; i++) {
- channel = 0;
- for (;;) {
- channel = find_next_bit(edma_cc[i]->edma_unused,
- edma_cc[i]->num_channels,
- channel);
- if (channel == edma_cc[i]->num_channels)
- break;
- if (!test_and_set_bit(channel,
- edma_cc[i]->edma_inuse)) {
- done = 1;
- ctlr = i;
- break;
- }
- channel++;
- }
- if (done)
- break;
- }
- if (!done)
- return -ENOMEM;
- } else if (channel >= edma_cc[ctlr]->num_channels) {
- return -EINVAL;
- } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
- return -EBUSY;
- }
-
- /* ensure access through shadow region 0 */
- edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
-
- /* ensure no events are pending */
- edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
- memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
- &dummy_paramset, PARM_SIZE);
-
- if (callback)
- setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
- callback, data);
-
- map_dmach_queue(ctlr, channel, eventq_no);
-
- return EDMA_CTLR_CHAN(ctlr, channel);
-}
-EXPORT_SYMBOL(edma_alloc_channel);
-
-
-/**
- * edma_free_channel - deallocate DMA channel
- * @channel: dma channel returned from edma_alloc_channel()
- *
- * This deallocates the DMA channel and associated parameter RAM slot
- * allocated by edma_alloc_channel().
- *
- * Callers are responsible for ensuring the channel is inactive, and
- * will not be reactivated by linking, chaining, or software calls to
- * edma_start().
- */
-void edma_free_channel(unsigned channel)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
- channel = EDMA_CHAN_SLOT(channel);
-
- if (channel >= edma_cc[ctlr]->num_channels)
- return;
-
- setup_dma_interrupt(channel, NULL, NULL);
- /* REVISIT should probably take out of shadow region 0 */
-
- memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
- &dummy_paramset, PARM_SIZE);
- clear_bit(channel, edma_cc[ctlr]->edma_inuse);
-}
-EXPORT_SYMBOL(edma_free_channel);
-
-/**
- * edma_alloc_slot - allocate DMA parameter RAM
- * @slot: specific slot to allocate; negative for "any unused slot"
- *
- * This allocates a parameter RAM slot, initializing it to hold a
- * dummy transfer. Slots allocated using this routine have not been
- * mapped to a hardware DMA channel, and will normally be used by
- * linking to them from a slot associated with a DMA channel.
- *
- * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
- * slots may be allocated on behalf of DSP firmware.
- *
- * Returns the number of the slot, else negative errno.
- */
-int edma_alloc_slot(unsigned ctlr, int slot)
-{
- if (slot >= 0)
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < 0) {
- slot = edma_cc[ctlr]->num_channels;
- for (;;) {
- slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
- edma_cc[ctlr]->num_slots, slot);
- if (slot == edma_cc[ctlr]->num_slots)
- return -ENOMEM;
- if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
- break;
- }
- } else if (slot < edma_cc[ctlr]->num_channels ||
- slot >= edma_cc[ctlr]->num_slots) {
- return -EINVAL;
- } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
- return -EBUSY;
- }
-
- memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
- &dummy_paramset, PARM_SIZE);
-
- return EDMA_CTLR_CHAN(ctlr, slot);
-}
-EXPORT_SYMBOL(edma_alloc_slot);
-
-/**
- * edma_free_slot - deallocate DMA parameter RAM
- * @slot: parameter RAM slot returned from edma_alloc_slot()
- *
- * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
- * Callers are responsible for ensuring the slot is inactive, and will
- * not be activated.
- */
-void edma_free_slot(unsigned slot)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_channels ||
- slot >= edma_cc[ctlr]->num_slots)
- return;
-
- memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
- &dummy_paramset, PARM_SIZE);
- clear_bit(slot, edma_cc[ctlr]->edma_inuse);
-}
-EXPORT_SYMBOL(edma_free_slot);
-
-
-/**
- * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
- * The API will return the starting point of a set of
- * contiguous parameter RAM slots that have been requested
- *
- * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
- * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
- * @count: number of contiguous Paramter RAM slots
- * @slot - the start value of Parameter RAM slot that should be passed if id
- * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
- *
- * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
- * contiguous Parameter RAM slots from parameter RAM 64 in the case of
- * DaVinci SOCs and 32 in the case of DA8xx SOCs.
- *
- * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
- * set of contiguous parameter RAM slots from the "slot" that is passed as an
- * argument to the API.
- *
- * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
- * starts looking for a set of contiguous parameter RAMs from the "slot"
- * that is passed as an argument to the API. On failure the API will try to
- * find a set of contiguous Parameter RAM slots from the remaining Parameter
- * RAM slots
- */
-int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
-{
- /*
- * The start slot requested should be greater than
- * the number of channels and lesser than the total number
- * of slots
- */
- if ((id != EDMA_CONT_PARAMS_ANY) &&
- (slot < edma_cc[ctlr]->num_channels ||
- slot >= edma_cc[ctlr]->num_slots))
- return -EINVAL;
-
- /*
- * The number of parameter RAM slots requested cannot be less than 1
- * and cannot be more than the number of slots minus the number of
- * channels
- */
- if (count < 1 || count >
- (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
- return -EINVAL;
-
- switch (id) {
- case EDMA_CONT_PARAMS_ANY:
- return reserve_contiguous_slots(ctlr, id, count,
- edma_cc[ctlr]->num_channels);
- case EDMA_CONT_PARAMS_FIXED_EXACT:
- case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
- return reserve_contiguous_slots(ctlr, id, count, slot);
- default:
- return -EINVAL;
- }
-
-}
-EXPORT_SYMBOL(edma_alloc_cont_slots);
-
-/**
- * edma_free_cont_slots - deallocate DMA parameter RAM slots
- * @slot: first parameter RAM of a set of parameter RAM slots to be freed
- * @count: the number of contiguous parameter RAM slots to be freed
- *
- * This deallocates the parameter RAM slots allocated by
- * edma_alloc_cont_slots.
- * Callers/applications need to keep track of sets of contiguous
- * parameter RAM slots that have been allocated using the edma_alloc_cont_slots
- * API.
- * Callers are responsible for ensuring the slots are inactive, and will
- * not be activated.
- */
-int edma_free_cont_slots(unsigned slot, int count)
-{
- unsigned ctlr, slot_to_free;
- int i;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_channels ||
- slot >= edma_cc[ctlr]->num_slots ||
- count < 1)
- return -EINVAL;
-
- for (i = slot; i < slot + count; ++i) {
- ctlr = EDMA_CTLR(i);
- slot_to_free = EDMA_CHAN_SLOT(i);
-
- memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
- &dummy_paramset, PARM_SIZE);
- clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
- }
-
- return 0;
-}
-EXPORT_SYMBOL(edma_free_cont_slots);
-
-/*-----------------------------------------------------------------------*/
-
-/* Parameter RAM operations (i) -- read/write partial slots */
-
-/**
- * edma_set_src - set initial DMA source address in parameter RAM slot
- * @slot: parameter RAM slot being configured
- * @src_port: physical address of source (memory, controller FIFO, etc)
- * @addressMode: INCR, except in very rare cases
- * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
- * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
- *
- * Note that the source address is modified during the DMA transfer
- * according to edma_set_src_index().
- */
-void edma_set_src(unsigned slot, dma_addr_t src_port,
- enum address_mode mode, enum fifo_width width)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_slots) {
- unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
-
- if (mode) {
- /* set SAM and program FWID */
- i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
- } else {
- /* clear SAM */
- i &= ~SAM;
- }
- edma_parm_write(ctlr, PARM_OPT, slot, i);
-
- /* set the source port address
- in source register of param structure */
- edma_parm_write(ctlr, PARM_SRC, slot, src_port);
- }
-}
-EXPORT_SYMBOL(edma_set_src);
-
-/**
- * edma_set_dest - set initial DMA destination address in parameter RAM slot
- * @slot: parameter RAM slot being configured
- * @dest_port: physical address of destination (memory, controller FIFO, etc)
- * @addressMode: INCR, except in very rare cases
- * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
- * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
- *
- * Note that the destination address is modified during the DMA transfer
- * according to edma_set_dest_index().
- */
-void edma_set_dest(unsigned slot, dma_addr_t dest_port,
- enum address_mode mode, enum fifo_width width)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_slots) {
- unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
-
- if (mode) {
- /* set DAM and program FWID */
- i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
- } else {
- /* clear DAM */
- i &= ~DAM;
- }
- edma_parm_write(ctlr, PARM_OPT, slot, i);
- /* set the destination port address
- in dest register of param structure */
- edma_parm_write(ctlr, PARM_DST, slot, dest_port);
- }
-}
-EXPORT_SYMBOL(edma_set_dest);
-
-/**
- * edma_get_position - returns the current transfer points
- * @slot: parameter RAM slot being examined
- * @src: pointer to source port position
- * @dst: pointer to destination port position
- *
- * Returns current source and destination addresses for a particular
- * parameter RAM slot. Its channel should not be active when this is called.
- */
-void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst)
-{
- struct edmacc_param temp;
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp);
- if (src != NULL)
- *src = temp.src;
- if (dst != NULL)
- *dst = temp.dst;
-}
-EXPORT_SYMBOL(edma_get_position);
-
-/**
- * edma_set_src_index - configure DMA source address indexing
- * @slot: parameter RAM slot being configured
- * @src_bidx: byte offset between source arrays in a frame
- * @src_cidx: byte offset between source frames in a block
- *
- * Offsets are specified to support either contiguous or discontiguous
- * memory transfers, or repeated access to a hardware register, as needed.
- * When accessing hardware registers, both offsets are normally zero.
- */
-void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_slots) {
- edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
- 0xffff0000, src_bidx);
- edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
- 0xffff0000, src_cidx);
- }
-}
-EXPORT_SYMBOL(edma_set_src_index);
-
-/**
- * edma_set_dest_index - configure DMA destination address indexing
- * @slot: parameter RAM slot being configured
- * @dest_bidx: byte offset between destination arrays in a frame
- * @dest_cidx: byte offset between destination frames in a block
- *
- * Offsets are specified to support either contiguous or discontiguous
- * memory transfers, or repeated access to a hardware register, as needed.
- * When accessing hardware registers, both offsets are normally zero.
- */
-void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_slots) {
- edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
- 0x0000ffff, dest_bidx << 16);
- edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
- 0x0000ffff, dest_cidx << 16);
- }
-}
-EXPORT_SYMBOL(edma_set_dest_index);
-
-/**
- * edma_set_transfer_params - configure DMA transfer parameters
- * @slot: parameter RAM slot being configured
- * @acnt: how many bytes per array (at least one)
- * @bcnt: how many arrays per frame (at least one)
- * @ccnt: how many frames per block (at least one)
- * @bcnt_rld: used only for A-Synchronized transfers; this specifies
- * the value to reload into bcnt when it decrements to zero
- * @sync_mode: ASYNC or ABSYNC
- *
- * See the EDMA3 documentation to understand how to configure and link
- * transfers using the fields in PaRAM slots. If you are not doing it
- * all at once with edma_write_slot(), you will use this routine
- * plus two calls each for source and destination, setting the initial
- * address and saying how to index that address.
- *
- * An example of an A-Synchronized transfer is a serial link using a
- * single word shift register. In that case, @acnt would be equal to
- * that word size; the serial controller issues a DMA synchronization
- * event to transfer each word, and memory access by the DMA transfer
- * controller will be word-at-a-time.
- *
- * An example of an AB-Synchronized transfer is a device using a FIFO.
- * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
- * The controller with the FIFO issues DMA synchronization events when
- * the FIFO threshold is reached, and the DMA transfer controller will
- * transfer one frame to (or from) the FIFO. It will probably use
- * efficient burst modes to access memory.
- */
-void edma_set_transfer_params(unsigned slot,
- u16 acnt, u16 bcnt, u16 ccnt,
- u16 bcnt_rld, enum sync_dimension sync_mode)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_slots) {
- edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
- 0x0000ffff, bcnt_rld << 16);
- if (sync_mode == ASYNC)
- edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
- else
- edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
- /* Set the acount, bcount, ccount registers */
- edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
- edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
- }
-}
-EXPORT_SYMBOL(edma_set_transfer_params);
-
-/**
- * edma_link - link one parameter RAM slot to another
- * @from: parameter RAM slot originating the link
- * @to: parameter RAM slot which is the link target
- *
- * The originating slot should not be part of any active DMA transfer.
- */
-void edma_link(unsigned from, unsigned to)
-{
- unsigned ctlr_from, ctlr_to;
-
- ctlr_from = EDMA_CTLR(from);
- from = EDMA_CHAN_SLOT(from);
- ctlr_to = EDMA_CTLR(to);
- to = EDMA_CHAN_SLOT(to);
-
- if (from >= edma_cc[ctlr_from]->num_slots)
- return;
- if (to >= edma_cc[ctlr_to]->num_slots)
- return;
- edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
- PARM_OFFSET(to));
-}
-EXPORT_SYMBOL(edma_link);
-
-/**
- * edma_unlink - cut link from one parameter RAM slot
- * @from: parameter RAM slot originating the link
- *
- * The originating slot should not be part of any active DMA transfer.
- * Its link is set to 0xffff.
- */
-void edma_unlink(unsigned from)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(from);
- from = EDMA_CHAN_SLOT(from);
-
- if (from >= edma_cc[ctlr]->num_slots)
- return;
- edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
-}
-EXPORT_SYMBOL(edma_unlink);
-
-/*-----------------------------------------------------------------------*/
-
-/* Parameter RAM operations (ii) -- read/write whole parameter sets */
-
-/**
- * edma_write_slot - write parameter RAM data for slot
- * @slot: number of parameter RAM slot being modified
- * @param: data to be written into parameter RAM slot
- *
- * Use this to assign all parameters of a transfer at once. This
- * allows more efficient setup of transfers than issuing multiple
- * calls to set up those parameters in small pieces, and provides
- * complete control over all transfer options.
- */
-void edma_write_slot(unsigned slot, const struct edmacc_param *param)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot >= edma_cc[ctlr]->num_slots)
- return;
- memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
- PARM_SIZE);
-}
-EXPORT_SYMBOL(edma_write_slot);
-
-/**
- * edma_read_slot - read parameter RAM data from slot
- * @slot: number of parameter RAM slot being copied
- * @param: where to store copy of parameter RAM data
- *
- * Use this to read data from a parameter RAM slot, perhaps to
- * save them as a template for later reuse.
- */
-void edma_read_slot(unsigned slot, struct edmacc_param *param)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot >= edma_cc[ctlr]->num_slots)
- return;
- memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
- PARM_SIZE);
-}
-EXPORT_SYMBOL(edma_read_slot);
-
-/*-----------------------------------------------------------------------*/
-
-/* Various EDMA channel control operations */
-
-/**
- * edma_pause - pause dma on a channel
- * @channel: on which edma_start() has been called
- *
- * This temporarily disables EDMA hardware events on the specified channel,
- * preventing them from triggering new transfers on its behalf
- */
-void edma_pause(unsigned channel)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
- channel = EDMA_CHAN_SLOT(channel);
-
- if (channel < edma_cc[ctlr]->num_channels) {
- unsigned int mask = BIT(channel & 0x1f);
-
- edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
- }
-}
-EXPORT_SYMBOL(edma_pause);
-
-/**
- * edma_resume - resumes dma on a paused channel
- * @channel: on which edma_pause() has been called
- *
- * This re-enables EDMA hardware events on the specified channel.
- */
-void edma_resume(unsigned channel)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
- channel = EDMA_CHAN_SLOT(channel);
-
- if (channel < edma_cc[ctlr]->num_channels) {
- unsigned int mask = BIT(channel & 0x1f);
-
- edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
- }
-}
-EXPORT_SYMBOL(edma_resume);
-
-/**
- * edma_start - start dma on a channel
- * @channel: channel being activated
- *
- * Channels with event associations will be triggered by their hardware
- * events, and channels without such associations will be triggered by
- * software. (At this writing there is no interface for using software
- * triggers except with channels that don't support hardware triggers.)
- *
- * Returns zero on success, else negative errno.
- */
-int edma_start(unsigned channel)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
- channel = EDMA_CHAN_SLOT(channel);
-
- if (channel < edma_cc[ctlr]->num_channels) {
- int j = channel >> 5;
- unsigned int mask = BIT(channel & 0x1f);
-
- /* EDMA channels without event association */
- if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
- pr_debug("EDMA: ESR%d %08x\n", j,
- edma_shadow0_read_array(ctlr, SH_ESR, j));
- edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
- return 0;
- }
-
- /* EDMA channel with event association */
- pr_debug("EDMA: ER%d %08x\n", j,
- edma_shadow0_read_array(ctlr, SH_ER, j));
- /* Clear any pending event or error */
- edma_write_array(ctlr, EDMA_ECR, j, mask);
- edma_write_array(ctlr, EDMA_EMCR, j, mask);
- /* Clear any SER */
- edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
- edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
- pr_debug("EDMA: EER%d %08x\n", j,
- edma_shadow0_read_array(ctlr, SH_EER, j));
- return 0;
- }
-
- return -EINVAL;
-}
-EXPORT_SYMBOL(edma_start);
-
-/**
- * edma_stop - stops dma on the channel passed
- * @channel: channel being deactivated
- *
- * When @lch is a channel, any active transfer is paused and
- * all pending hardware events are cleared. The current transfer
- * may not be resumed, and the channel's Parameter RAM should be
- * reinitialized before being reused.
- */
-void edma_stop(unsigned channel)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
- channel = EDMA_CHAN_SLOT(channel);
-
- if (channel < edma_cc[ctlr]->num_channels) {
- int j = channel >> 5;
- unsigned int mask = BIT(channel & 0x1f);
-
- edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
- edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
- edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
- edma_write_array(ctlr, EDMA_EMCR, j, mask);
-
- pr_debug("EDMA: EER%d %08x\n", j,
- edma_shadow0_read_array(ctlr, SH_EER, j));
-
- /* REVISIT: consider guarding against inappropriate event
- * chaining by overwriting with dummy_paramset.
- */
- }
-}
-EXPORT_SYMBOL(edma_stop);
-
-/******************************************************************************
- *
- * It cleans ParamEntry qand bring back EDMA to initial state if media has
- * been removed before EDMA has finished.It is usedful for removable media.
- * Arguments:
- * ch_no - channel no
- *
- * Return: zero on success, or corresponding error no on failure
- *
- * FIXME this should not be needed ... edma_stop() should suffice.
- *
- *****************************************************************************/
-
-void edma_clean_channel(unsigned channel)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
- channel = EDMA_CHAN_SLOT(channel);
-
- if (channel < edma_cc[ctlr]->num_channels) {
- int j = (channel >> 5);
- unsigned int mask = BIT(channel & 0x1f);
-
- pr_debug("EDMA: EMR%d %08x\n", j,
- edma_read_array(ctlr, EDMA_EMR, j));
- edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
- /* Clear the corresponding EMR bits */
- edma_write_array(ctlr, EDMA_EMCR, j, mask);
- /* Clear any SER */
- edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
- edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
- }
-}
-EXPORT_SYMBOL(edma_clean_channel);
-
-/*
- * edma_clear_event - clear an outstanding event on the DMA channel
- * Arguments:
- * channel - channel number
- */
-void edma_clear_event(unsigned channel)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
- channel = EDMA_CHAN_SLOT(channel);
-
- if (channel >= edma_cc[ctlr]->num_channels)
- return;
- if (channel < 32)
- edma_write(ctlr, EDMA_ECR, BIT(channel));
- else
- edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
-}
-EXPORT_SYMBOL(edma_clear_event);
-
-/*-----------------------------------------------------------------------*/
-
-static int __init edma_probe(struct platform_device *pdev)
-{
- struct edma_soc_info **info = pdev->dev.platform_data;
- const s8 (*queue_priority_mapping)[2];
- const s8 (*queue_tc_mapping)[2];
- int i, j, off, ln, found = 0;
- int status = -1;
- const s16 (*rsv_chans)[2];
- const s16 (*rsv_slots)[2];
- int irq[EDMA_MAX_CC] = {0, 0};
- int err_irq[EDMA_MAX_CC] = {0, 0};
- struct resource *r[EDMA_MAX_CC] = {NULL};
- resource_size_t len[EDMA_MAX_CC];
- char res_name[10];
- char irq_name[10];
-
- if (!info)
- return -ENODEV;
-
- for (j = 0; j < EDMA_MAX_CC; j++) {
- sprintf(res_name, "edma_cc%d", j);
- r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- res_name);
- if (!r[j] || !info[j]) {
- if (found)
- break;
- else
- return -ENODEV;
- } else {
- found = 1;
- }
-
- len[j] = resource_size(r[j]);
-
- r[j] = request_mem_region(r[j]->start, len[j],
- dev_name(&pdev->dev));
- if (!r[j]) {
- status = -EBUSY;
- goto fail1;
- }
-
- edmacc_regs_base[j] = ioremap(r[j]->start, len[j]);
- if (!edmacc_regs_base[j]) {
- status = -EBUSY;
- goto fail1;
- }
-
- edma_cc[j] = kzalloc(sizeof(struct edma), GFP_KERNEL);
- if (!edma_cc[j]) {
- status = -ENOMEM;
- goto fail1;
- }
-
- edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel,
- EDMA_MAX_DMACH);
- edma_cc[j]->num_slots = min_t(unsigned, info[j]->n_slot,
- EDMA_MAX_PARAMENTRY);
- edma_cc[j]->num_cc = min_t(unsigned, info[j]->n_cc,
- EDMA_MAX_CC);
-
- edma_cc[j]->default_queue = info[j]->default_queue;
-
- dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
- edmacc_regs_base[j]);
-
- for (i = 0; i < edma_cc[j]->num_slots; i++)
- memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
- &dummy_paramset, PARM_SIZE);
-
- /* Mark all channels as unused */
- memset(edma_cc[j]->edma_unused, 0xff,
- sizeof(edma_cc[j]->edma_unused));
-
- if (info[j]->rsv) {
-
- /* Clear the reserved channels in unused list */
- rsv_chans = info[j]->rsv->rsv_chans;
- if (rsv_chans) {
- for (i = 0; rsv_chans[i][0] != -1; i++) {
- off = rsv_chans[i][0];
- ln = rsv_chans[i][1];
- clear_bits(off, ln,
- edma_cc[j]->edma_unused);
- }
- }
-
- /* Set the reserved slots in inuse list */
- rsv_slots = info[j]->rsv->rsv_slots;
- if (rsv_slots) {
- for (i = 0; rsv_slots[i][0] != -1; i++) {
- off = rsv_slots[i][0];
- ln = rsv_slots[i][1];
- set_bits(off, ln,
- edma_cc[j]->edma_inuse);
- }
- }
- }
-
- sprintf(irq_name, "edma%d", j);
- irq[j] = platform_get_irq_byname(pdev, irq_name);
- edma_cc[j]->irq_res_start = irq[j];
- status = request_irq(irq[j], dma_irq_handler, 0, "edma",
- &pdev->dev);
- if (status < 0) {
- dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
- irq[j], status);
- goto fail;
- }
-
- sprintf(irq_name, "edma%d_err", j);
- err_irq[j] = platform_get_irq_byname(pdev, irq_name);
- edma_cc[j]->irq_res_end = err_irq[j];
- status = request_irq(err_irq[j], dma_ccerr_handler, 0,
- "edma_error", &pdev->dev);
- if (status < 0) {
- dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
- err_irq[j], status);
- goto fail;
- }
-
- for (i = 0; i < edma_cc[j]->num_channels; i++)
- map_dmach_queue(j, i, info[j]->default_queue);
-
- queue_tc_mapping = info[j]->queue_tc_mapping;
- queue_priority_mapping = info[j]->queue_priority_mapping;
-
- /* Event queue to TC mapping */
- for (i = 0; queue_tc_mapping[i][0] != -1; i++)
- map_queue_tc(j, queue_tc_mapping[i][0],
- queue_tc_mapping[i][1]);
-
- /* Event queue priority mapping */
- for (i = 0; queue_priority_mapping[i][0] != -1; i++)
- assign_priority_to_queue(j,
- queue_priority_mapping[i][0],
- queue_priority_mapping[i][1]);
-
- /* Map the channel to param entry if channel mapping logic
- * exist
- */
- if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
- map_dmach_param(j);
-
- for (i = 0; i < info[j]->n_region; i++) {
- edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
- edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
- edma_write_array(j, EDMA_QRAE, i, 0x0);
- }
- arch_num_cc++;
- }
-
- if (tc_errs_handled) {
- status = request_irq(IRQ_TCERRINT0, dma_tc0err_handler, 0,
- "edma_tc0", &pdev->dev);
- if (status < 0) {
- dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
- IRQ_TCERRINT0, status);
- return status;
- }
- status = request_irq(IRQ_TCERRINT, dma_tc1err_handler, 0,
- "edma_tc1", &pdev->dev);
- if (status < 0) {
- dev_dbg(&pdev->dev, "request_irq %d --> %d\n",
- IRQ_TCERRINT, status);
- return status;
- }
- }
-
- return 0;
-
-fail:
- for (i = 0; i < EDMA_MAX_CC; i++) {
- if (err_irq[i])
- free_irq(err_irq[i], &pdev->dev);
- if (irq[i])
- free_irq(irq[i], &pdev->dev);
- }
-fail1:
- for (i = 0; i < EDMA_MAX_CC; i++) {
- if (r[i])
- release_mem_region(r[i]->start, len[i]);
- if (edmacc_regs_base[i])
- iounmap(edmacc_regs_base[i]);
- kfree(edma_cc[i]);
- }
- return status;
-}
-
-
-static struct platform_driver edma_driver = {
- .driver.name = "edma",
-};
-
-static int __init edma_init(void)
-{
- return platform_driver_probe(&edma_driver, edma_probe);
-}
-arch_initcall(edma_init);
-
diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h
index 9aa2409..4fe8453 100644
--- a/arch/arm/mach-davinci/include/mach/asp.h
+++ b/arch/arm/mach-davinci/include/mach/asp.h
@@ -4,8 +4,8 @@
#ifndef __ASM_ARCH_DAVINCI_ASP_H
#define __ASM_ARCH_DAVINCI_ASP_H
+#include <asm/mach/edma.h>
#include <mach/irqs.h>
-#include <mach/edma.h>
/* Bases of dm644x and dm355 register banks */
#define DAVINCI_ASP0_BASE 0x01E02000
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index a2f1f27..6f70587 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -17,8 +17,9 @@
#include <linux/davinci_emac.h>
#include <linux/spi/spi.h>
+#include <asm/mach/edma.h>
+
#include <mach/serial.h>
-#include <mach/edma.h>
#include <mach/i2c.h>
#include <mach/asp.h>
#include <mach/mmc.h>
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
deleted file mode 100644
index 7e84c90..0000000
--- a/arch/arm/mach-davinci/include/mach/edma.h
+++ /dev/null
@@ -1,267 +0,0 @@
-/*
- * TI DAVINCI dma definitions
- *
- * Copyright (C) 2006-2009 Texas Instruments.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-/*
- * This EDMA3 programming framework exposes two basic kinds of resource:
- *
- * Channel Triggers transfers, usually from a hardware event but
- * also manually or by "chaining" from DMA completions.
- * Each channel is coupled to a Parameter RAM (PaRAM) slot.
- *
- * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
- * "set"), source and destination addresses, a link to a
- * next PaRAM slot (if any), options for the transfer, and
- * instructions for updating those addresses. There are
- * more than twice as many slots as event channels.
- *
- * Each PaRAM set describes a sequence of transfers, either for one large
- * buffer or for several discontiguous smaller buffers. An EDMA transfer
- * is driven only from a channel, which performs the transfers specified
- * in its PaRAM slot until there are no more transfers. When that last
- * transfer completes, the "link" field may be used to reload the channel's
- * PaRAM slot with a new transfer descriptor.
- *
- * The EDMA Channel Controller (CC) maps requests from channels into physical
- * Transfer Controller (TC) requests when the channel triggers (by hardware
- * or software events, or by chaining). The two physical DMA channels provided
- * by the TCs are thus shared by many logical channels.
- *
- * DaVinci hardware also has a "QDMA" mechanism which is not currently
- * supported through this interface. (DSP firmware uses it though.)
- */
-
-#ifndef EDMA_H_
-#define EDMA_H_
-
-/* PaRAM slots are laid out like this */
-struct edmacc_param {
- unsigned int opt;
- unsigned int src;
- unsigned int a_b_cnt;
- unsigned int dst;
- unsigned int src_dst_bidx;
- unsigned int link_bcntrld;
- unsigned int src_dst_cidx;
- unsigned int ccnt;
-};
-
-#define CCINT0_INTERRUPT 16
-#define CCERRINT_INTERRUPT 17
-#define TCERRINT0_INTERRUPT 18
-#define TCERRINT1_INTERRUPT 19
-
-/* fields in edmacc_param.opt */
-#define SAM BIT(0)
-#define DAM BIT(1)
-#define SYNCDIM BIT(2)
-#define STATIC BIT(3)
-#define EDMA_FWID (0x07 << 8)
-#define TCCMODE BIT(11)
-#define EDMA_TCC(t) ((t) << 12)
-#define TCINTEN BIT(20)
-#define ITCINTEN BIT(21)
-#define TCCHEN BIT(22)
-#define ITCCHEN BIT(23)
-
-#define TRWORD (0x7<<2)
-#define PAENTRY (0x1ff<<5)
-
-/* Drivers should avoid using these symbolic names for dm644x
- * channels, and use platform_device IORESOURCE_DMA resources
- * instead. (Other DaVinci chips have different peripherals
- * and thus have different DMA channel mappings.)
- */
-#define DAVINCI_DMA_MCBSP_TX 2
-#define DAVINCI_DMA_MCBSP_RX 3
-#define DAVINCI_DMA_VPSS_HIST 4
-#define DAVINCI_DMA_VPSS_H3A 5
-#define DAVINCI_DMA_VPSS_PRVU 6
-#define DAVINCI_DMA_VPSS_RSZ 7
-#define DAVINCI_DMA_IMCOP_IMXINT 8
-#define DAVINCI_DMA_IMCOP_VLCDINT 9
-#define DAVINCI_DMA_IMCO_PASQINT 10
-#define DAVINCI_DMA_IMCOP_DSQINT 11
-#define DAVINCI_DMA_SPI_SPIX 16
-#define DAVINCI_DMA_SPI_SPIR 17
-#define DAVINCI_DMA_UART0_URXEVT0 18
-#define DAVINCI_DMA_UART0_UTXEVT0 19
-#define DAVINCI_DMA_UART1_URXEVT1 20
-#define DAVINCI_DMA_UART1_UTXEVT1 21
-#define DAVINCI_DMA_UART2_URXEVT2 22
-#define DAVINCI_DMA_UART2_UTXEVT2 23
-#define DAVINCI_DMA_MEMSTK_MSEVT 24
-#define DAVINCI_DMA_MMCRXEVT 26
-#define DAVINCI_DMA_MMCTXEVT 27
-#define DAVINCI_DMA_I2C_ICREVT 28
-#define DAVINCI_DMA_I2C_ICXEVT 29
-#define DAVINCI_DMA_GPIO_GPINT0 32
-#define DAVINCI_DMA_GPIO_GPINT1 33
-#define DAVINCI_DMA_GPIO_GPINT2 34
-#define DAVINCI_DMA_GPIO_GPINT3 35
-#define DAVINCI_DMA_GPIO_GPINT4 36
-#define DAVINCI_DMA_GPIO_GPINT5 37
-#define DAVINCI_DMA_GPIO_GPINT6 38
-#define DAVINCI_DMA_GPIO_GPINT7 39
-#define DAVINCI_DMA_GPIO_GPBNKINT0 40
-#define DAVINCI_DMA_GPIO_GPBNKINT1 41
-#define DAVINCI_DMA_GPIO_GPBNKINT2 42
-#define DAVINCI_DMA_GPIO_GPBNKINT3 43
-#define DAVINCI_DMA_GPIO_GPBNKINT4 44
-#define DAVINCI_DMA_TIMER0_TINT0 48
-#define DAVINCI_DMA_TIMER1_TINT1 49
-#define DAVINCI_DMA_TIMER2_TINT2 50
-#define DAVINCI_DMA_TIMER3_TINT3 51
-#define DAVINCI_DMA_PWM0 52
-#define DAVINCI_DMA_PWM1 53
-#define DAVINCI_DMA_PWM2 54
-
-/* DA830 specific EDMA3 information */
-#define EDMA_DA830_NUM_DMACH 32
-#define EDMA_DA830_NUM_TCC 32
-#define EDMA_DA830_NUM_PARAMENTRY 128
-#define EDMA_DA830_NUM_EVQUE 2
-#define EDMA_DA830_NUM_TC 2
-#define EDMA_DA830_CHMAP_EXIST 0
-#define EDMA_DA830_NUM_REGIONS 4
-#define DA830_DMACH2EVENT_MAP0 0x000FC03Fu
-#define DA830_DMACH2EVENT_MAP1 0x00000000u
-#define DA830_EDMA_ARM_OWN 0x30FFCCFFu
-
-/*ch_status paramater of callback function possible values*/
-#define DMA_COMPLETE 1
-#define DMA_CC_ERROR 2
-#define DMA_TC1_ERROR 3
-#define DMA_TC2_ERROR 4
-
-enum address_mode {
- INCR = 0,
- FIFO = 1
-};
-
-enum fifo_width {
- W8BIT = 0,
- W16BIT = 1,
- W32BIT = 2,
- W64BIT = 3,
- W128BIT = 4,
- W256BIT = 5
-};
-
-enum dma_event_q {
- EVENTQ_0 = 0,
- EVENTQ_1 = 1,
- EVENTQ_2 = 2,
- EVENTQ_3 = 3,
- EVENTQ_DEFAULT = -1
-};
-
-enum sync_dimension {
- ASYNC = 0,
- ABSYNC = 1
-};
-
-#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
-#define EDMA_CTLR(i) ((i) >> 16)
-#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
-
-#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
-#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
-#define EDMA_CONT_PARAMS_ANY 1001
-#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
-#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
-
-#define EDMA_MAX_CC 2
-
-/* alloc/free DMA channels and their dedicated parameter RAM slots */
-int edma_alloc_channel(int channel,
- void (*callback)(unsigned channel, u16 ch_status, void *data),
- void *data, enum dma_event_q);
-void edma_free_channel(unsigned channel);
-
-/* alloc/free parameter RAM slots */
-int edma_alloc_slot(unsigned ctlr, int slot);
-void edma_free_slot(unsigned slot);
-
-/* alloc/free a set of contiguous parameter RAM slots */
-int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
-int edma_free_cont_slots(unsigned slot, int count);
-
-/* calls that operate on part of a parameter RAM slot */
-void edma_set_src(unsigned slot, dma_addr_t src_port,
- enum address_mode mode, enum fifo_width);
-void edma_set_dest(unsigned slot, dma_addr_t dest_port,
- enum address_mode mode, enum fifo_width);
-void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst);
-void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
-void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
-void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
- u16 bcnt_rld, enum sync_dimension sync_mode);
-void edma_link(unsigned from, unsigned to);
-void edma_unlink(unsigned from);
-
-/* calls that operate on an entire parameter RAM slot */
-void edma_write_slot(unsigned slot, const struct edmacc_param *params);
-void edma_read_slot(unsigned slot, struct edmacc_param *params);
-
-/* channel control operations */
-int edma_start(unsigned channel);
-void edma_stop(unsigned channel);
-void edma_clean_channel(unsigned channel);
-void edma_clear_event(unsigned channel);
-void edma_pause(unsigned channel);
-void edma_resume(unsigned channel);
-
-struct edma_rsv_info {
-
- const s16 (*rsv_chans)[2];
- const s16 (*rsv_slots)[2];
-};
-
-/* platform_data for EDMA driver */
-struct edma_soc_info {
-
- /* how many dma resources of each type */
- unsigned n_channel;
- unsigned n_region;
- unsigned n_slot;
- unsigned n_tc;
- unsigned n_cc;
- /*
- * Default queue is expected to be a low-priority queue.
- * This way, long transfers on the default queue started
- * by the codec engine will not cause audio defects.
- */
- enum dma_event_q default_queue;
-
- /* Resource reservation for other cores */
- struct edma_rsv_info *rsv;
-
- const s8 (*queue_tc_mapping)[2];
- const s8 (*queue_priority_mapping)[2];
-};
-
-#endif
diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/arch/arm/mach-davinci/include/mach/spi.h
index 7af305b..9f927da 100644
--- a/arch/arm/mach-davinci/include/mach/spi.h
+++ b/arch/arm/mach-davinci/include/mach/spi.h
@@ -19,7 +19,7 @@
#ifndef __ARCH_ARM_DAVINCI_SPI_H
#define __ARCH_ARM_DAVINCI_SPI_H
-#include <mach/edma.h>
+#include <asm/mach/edma.h>
#define SPI_INTERN_CS 0xFF
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index dd36eba..6ee991b 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -28,6 +28,7 @@ config ARCH_OMAP2PLUS
select OMAP_DM_TIMER
select USE_OF
select PROC_DEVICETREE if PROC_FS
+ select TI_PRIV_EDMA
help
"Systems based on OMAP2, OMAP3, OMAP4 or OMAP5"
--
1.7.9.5
------------------------------------------------------------------------------
Everyone hates slow websites. So do we.
Make your web apps faster with AppDynamics
Download AppDynamics Lite for free today:
http://ad.doubleclick.net/clk;258768047;13503038;j?
http://info.appdynamics.com/FreeJavaPerformanceDownload.html
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [RFC PATCH 02/13] ARM: edma: remove unused transfer controller handlers
[not found] ` <1348152226-13588-1-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
2012-09-20 14:43 ` [RFC PATCH 01/13] ARM: davinci: move private EDMA API to arm/common Matt Porter
@ 2012-09-20 14:43 ` Matt Porter
2012-09-20 14:43 ` [RFC PATCH 03/13] ARM: edma: add DT and runtime PM support for AM335x Matt Porter
` (11 subsequent siblings)
13 siblings, 0 replies; 52+ messages in thread
From: Matt Porter @ 2012-09-20 14:43 UTC (permalink / raw)
To: Tony Lindgren, Sekhar Nori, Grant Likely, Mark Brown,
Benoit Cousson, Russell King, Vinod Koul, Rob Landley,
Chris Ball
Cc: Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Dan Williams,
Linux SPI Devel List, Linux OMAP List, Linux ARM Kernel List
Fix build on OMAP, the irqs are undefined on AM33xx.
These error interrupt handlers were hardcoded as disabled
so since they are unused code, simply remove them.
Signed-off-by: Matt Porter <mporter-l0cyMroinI0@public.gmane.org>
---
arch/arm/common/edma.c | 37 -------------------------------------
1 file changed, 37 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index cecc50e..001d268 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -494,26 +494,6 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
return IRQ_HANDLED;
}
-/******************************************************************************
- *
- * Transfer controller error interrupt handlers
- *
- *****************************************************************************/
-
-#define tc_errs_handled false /* disabled as long as they're NOPs */
-
-static irqreturn_t dma_tc0err_handler(int irq, void *data)
-{
- dev_dbg(data, "dma_tc0err_handler\n");
- return IRQ_HANDLED;
-}
-
-static irqreturn_t dma_tc1err_handler(int irq, void *data)
-{
- dev_dbg(data, "dma_tc1err_handler\n");
- return IRQ_HANDLED;
-}
-
static int reserve_contiguous_slots(int ctlr, unsigned int id,
unsigned int num_slots,
unsigned int start_slot)
@@ -1538,23 +1518,6 @@ static int __init edma_probe(struct platform_device *pdev)
arch_num_cc++;
}
- if (tc_errs_handled) {
- status = request_irq(IRQ_TCERRINT0, dma_tc0err_handler, 0,
- "edma_tc0", &pdev->dev);
- if (status < 0) {
- dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
- IRQ_TCERRINT0, status);
- return status;
- }
- status = request_irq(IRQ_TCERRINT, dma_tc1err_handler, 0,
- "edma_tc1", &pdev->dev);
- if (status < 0) {
- dev_dbg(&pdev->dev, "request_irq %d --> %d\n",
- IRQ_TCERRINT, status);
- return status;
- }
- }
-
return 0;
fail:
--
1.7.9.5
------------------------------------------------------------------------------
Everyone hates slow websites. So do we.
Make your web apps faster with AppDynamics
Download AppDynamics Lite for free today:
http://ad.doubleclick.net/clk;258768047;13503038;j?
http://info.appdynamics.com/FreeJavaPerformanceDownload.html
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [RFC PATCH 03/13] ARM: edma: add DT and runtime PM support for AM335x
[not found] ` <1348152226-13588-1-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
2012-09-20 14:43 ` [RFC PATCH 01/13] ARM: davinci: move private EDMA API to arm/common Matt Porter
2012-09-20 14:43 ` [RFC PATCH 02/13] ARM: edma: remove unused transfer controller handlers Matt Porter
@ 2012-09-20 14:43 ` Matt Porter
[not found] ` <1348152226-13588-4-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
2012-09-20 14:43 ` [RFC PATCH 04/13] dmaengine: edma: enable build " Matt Porter
` (10 subsequent siblings)
13 siblings, 1 reply; 52+ messages in thread
From: Matt Porter @ 2012-09-20 14:43 UTC (permalink / raw)
To: Tony Lindgren, Sekhar Nori, Grant Likely, Mark Brown,
Benoit Cousson, Russell King, Vinod Koul, Rob Landley,
Chris Ball
Cc: Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Dan Williams,
Linux SPI Devel List, Linux OMAP List, Linux ARM Kernel List
Adds support for parsing the TI EDMA DT data into the required
EDMA private API platform data.
Calls runtime PM API only in the DT case in order to unidle the
associated hwmods on AM335x.
Signed-off-by: Matt Porter <mporter-l0cyMroinI0@public.gmane.org>
---
arch/arm/common/edma.c | 252 ++++++++++++++++++++++++++++++++++++--
arch/arm/include/asm/mach/edma.h | 8 +-
2 files changed, 244 insertions(+), 16 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 001d268..f337f81 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -24,6 +24,13 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/slab.h>
+#include <linux/edma.h>
+#include <linux/err.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_dma.h>
+#include <linux/of_irq.h>
+#include <linux/pm_runtime.h>
#include <asm/mach/edma.h>
@@ -1366,30 +1373,236 @@ void edma_clear_event(unsigned channel)
EXPORT_SYMBOL(edma_clear_event);
/*-----------------------------------------------------------------------*/
+static int edma_of_read_u32_to_s8_array(const struct device_node *np,
+ const char *propname, s8 *out_values,
+ size_t sz)
+{
+ struct property *prop = of_find_property(np, propname, NULL);
+ const __be32 *val;
+
+ if (!prop)
+ return -EINVAL;
+ if (!prop->value)
+ return -ENODATA;
+ if ((sz * sizeof(u32)) > prop->length)
+ return -EOVERFLOW;
+
+ val = prop->value;
+
+ while (sz--)
+ *out_values++ = (s8)(be32_to_cpup(val++) & 0xff);
+
+ /* Terminate it */
+ *out_values++ = -1;
+ *out_values++ = -1;
+
+ return 0;
+}
+
+static int edma_of_read_u32_to_s16_array(const struct device_node *np,
+ const char *propname, s16 *out_values,
+ size_t sz)
+{
+ struct property *prop = of_find_property(np, propname, NULL);
+ const __be32 *val;
+
+ if (!prop)
+ return -EINVAL;
+ if (!prop->value)
+ return -ENODATA;
+ if ((sz * sizeof(u32)) > prop->length)
+ return -EOVERFLOW;
+
+ val = prop->value;
+
+ while (sz--)
+ *out_values++ = (s16)(be32_to_cpup(val++) & 0xffff);
+
+ /* Terminate it */
+ *out_values++ = -1;
+ *out_values++ = -1;
+
+ return 0;
+}
+
+static int edma_of_parse_dt(struct device *dev,
+ struct device_node *node,
+ struct edma_soc_info *pdata)
+{
+ int ret = 0;
+ u32 value;
+ struct property *prop;
+ size_t sz;
+ struct edma_rsv_info *rsv_info;
+ s16 (*rsv_chans)[2], (*rsv_slots)[2];
+ s8 (*queue_tc_map)[2], (*queue_priority_map)[2];
+
+ ret = of_property_read_u32(node, "dma-channels", &value);
+ if (ret < 0)
+ return ret;
+ pdata->n_channel = value;
+
+ ret = of_property_read_u32(node, "ti,edma-regions", &value);
+ if (ret < 0)
+ return ret;
+ pdata->n_region = value;
+
+ ret = of_property_read_u32(node, "ti,edma-slots", &value);
+ if (ret < 0)
+ return ret;
+ pdata->n_slot = value;
+
+ pdata->n_cc = 1;
+ /* This is unused */
+ pdata->n_tc = 3;
+
+ rsv_info =
+ devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
+ if (!rsv_info)
+ return -ENOMEM;
+ pdata->rsv = rsv_info;
+
+ /* Build the reserved channel/slots arrays */
+ prop = of_find_property(node, "ti,edma-reserved-channels", &sz);
+ if (!prop)
+ return -EINVAL;
+
+ rsv_chans =
+ devm_kzalloc(dev, sz/sizeof(s16) + 2*sizeof(s16), GFP_KERNEL);
+ if (!rsv_chans)
+ return -ENOMEM;
+ pdata->rsv->rsv_chans = rsv_chans;
+
+ ret = edma_of_read_u32_to_s16_array(node, "ti,edma-reserved-channels",
+ (s16 *)rsv_chans, sz/sizeof(u32));
+ if (ret < 0)
+ return ret;
+
+ prop = of_find_property(node, "ti,edma-reserved-slots", &sz);
+ if (!prop)
+ return -EINVAL;
+
+ rsv_slots = devm_kzalloc(dev,
+ sz/sizeof(s16) + 2*sizeof(s16),
+ GFP_KERNEL);
+ if (!rsv_slots)
+ return -ENOMEM;
+ pdata->rsv->rsv_slots = rsv_slots;
+
+ ret = edma_of_read_u32_to_s16_array(node,
+ "ti,edma-reserved-slots",
+ (s16 *)rsv_slots,
+ sz/sizeof(u32));
+ if (ret < 0)
+ return ret;
+
+ prop = of_find_property(node, "ti,edma-queue-tc-map", &sz);
+ if (!prop)
+ return -EINVAL;
+
+ queue_tc_map = devm_kzalloc(dev,
+ sz/sizeof(s8) + 2*sizeof(s8),
+ GFP_KERNEL);
+ if (!rsv_slots)
+ return -ENOMEM;
+ pdata->queue_tc_mapping = queue_tc_map;
+
+ ret = edma_of_read_u32_to_s8_array(node,
+ "ti,edma-queue-tc-map",
+ (s8 *)queue_tc_map,
+ sz/sizeof(u32));
+ if (ret < 0)
+ return ret;
+
+ prop = of_find_property(node, "ti,edma-queue-priority-map", &sz);
+ if (!prop)
+ return -EINVAL;
+
+ queue_priority_map = devm_kzalloc(dev,
+ sz/sizeof(s8) + 2*sizeof(s8),
+ GFP_KERNEL);
+ if (!rsv_slots)
+ return -ENOMEM;
+ pdata->queue_priority_mapping = queue_priority_map;
+
+ ret = edma_of_read_u32_to_s8_array(node,
+ "ti,edma-queue-tc-map",
+ (s8 *)queue_priority_map,
+ sz/sizeof(u32));
+ if (ret < 0)
+ return ret;
+
+ ret = of_property_read_u32(node, "ti,edma-default-queue", &value);
+ if (ret < 0)
+ return ret;
+ pdata->default_queue = value;
+
+ return ret;
+}
+
+static struct of_dma_filter_info edma_filter_info = {
+ .filter_fn = edma_filter_fn,
+};
static int __init edma_probe(struct platform_device *pdev)
{
struct edma_soc_info **info = pdev->dev.platform_data;
- const s8 (*queue_priority_mapping)[2];
- const s8 (*queue_tc_mapping)[2];
+ s8 (*queue_priority_mapping)[2];
+ s8 (*queue_tc_mapping)[2];
int i, j, off, ln, found = 0;
int status = -1;
- const s16 (*rsv_chans)[2];
- const s16 (*rsv_slots)[2];
+ s16 (*rsv_chans)[2];
+ s16 (*rsv_slots)[2];
int irq[EDMA_MAX_CC] = {0, 0};
int err_irq[EDMA_MAX_CC] = {0, 0};
struct resource *r[EDMA_MAX_CC] = {NULL};
+ struct resource res[EDMA_MAX_CC];
resource_size_t len[EDMA_MAX_CC];
char res_name[10];
char irq_name[10];
+ struct device_node *node = pdev->dev.of_node;
+ struct device *dev = &pdev->dev;
+ struct edma_soc_info *pdata;
+
+ if (node) {
+ int ret;
+ pdata = devm_kzalloc(dev,
+ sizeof(struct edma_soc_info),
+ GFP_KERNEL);
+ edma_of_parse_dt(dev, node, pdata);
+ info = &pdata;
+ dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
+ of_dma_controller_register(dev->of_node,
+ of_dma_simple_xlate,
+ &edma_filter_info);
+ pm_runtime_enable(dev);
+ ret = pm_runtime_get_sync(dev);
+ if (IS_ERR_VALUE(ret)) {
+ dev_err(dev, "pm_runtime_get_sync() failed\n");
+ return ret;
+ }
+ }
if (!info)
return -ENODEV;
for (j = 0; j < EDMA_MAX_CC; j++) {
- sprintf(res_name, "edma_cc%d", j);
- r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ if (node) {
+ int err;
+ err = of_address_to_resource(node, 0, &res[j]);
+ if (err) {
+ dev_err(dev,
+ "unable to find 'reg' property\n");
+ return -EIO;
+ }
+ r[j] = &res[j];
+
+ } else {
+ sprintf(res_name, "edma_cc%d", j);
+ r[j] = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM,
res_name);
+ }
if (!r[j] || !info[j]) {
if (found)
break;
@@ -1465,8 +1678,12 @@ static int __init edma_probe(struct platform_device *pdev)
}
}
- sprintf(irq_name, "edma%d", j);
- irq[j] = platform_get_irq_byname(pdev, irq_name);
+ if (node)
+ irq[j] = irq_of_parse_and_map(node, 0);
+ else {
+ sprintf(irq_name, "edma%d", j);
+ irq[j] = platform_get_irq_byname(pdev, irq_name);
+ }
edma_cc[j]->irq_res_start = irq[j];
status = request_irq(irq[j], dma_irq_handler, 0, "edma",
&pdev->dev);
@@ -1476,8 +1693,12 @@ static int __init edma_probe(struct platform_device *pdev)
goto fail;
}
- sprintf(irq_name, "edma%d_err", j);
- err_irq[j] = platform_get_irq_byname(pdev, irq_name);
+ if (node)
+ err_irq[j] = irq_of_parse_and_map(node, 2);
+ else {
+ sprintf(irq_name, "edma%d_err", j);
+ err_irq[j] = platform_get_irq_byname(pdev, irq_name);
+ }
edma_cc[j]->irq_res_end = err_irq[j];
status = request_irq(err_irq[j], dma_ccerr_handler, 0,
"edma_error", &pdev->dev);
@@ -1538,9 +1759,17 @@ fail1:
return status;
}
+static const struct of_device_id edma_of_ids[] = {
+ { .compatible = "ti,edma3", },
+ {}
+};
static struct platform_driver edma_driver = {
- .driver.name = "edma",
+ .driver = {
+ .name = "edma",
+ .of_match_table = edma_of_ids,
+ },
+ .probe = edma_probe,
};
static int __init edma_init(void)
@@ -1548,4 +1777,3 @@ static int __init edma_init(void)
return platform_driver_probe(&edma_driver, edma_probe);
}
arch_initcall(edma_init);
-
diff --git a/arch/arm/include/asm/mach/edma.h b/arch/arm/include/asm/mach/edma.h
index 7e84c90..ce5f6f8 100644
--- a/arch/arm/include/asm/mach/edma.h
+++ b/arch/arm/include/asm/mach/edma.h
@@ -237,8 +237,8 @@ void edma_resume(unsigned channel);
struct edma_rsv_info {
- const s16 (*rsv_chans)[2];
- const s16 (*rsv_slots)[2];
+ s16 (*rsv_chans)[2];
+ s16 (*rsv_slots)[2];
};
/* platform_data for EDMA driver */
@@ -260,8 +260,8 @@ struct edma_soc_info {
/* Resource reservation for other cores */
struct edma_rsv_info *rsv;
- const s8 (*queue_tc_mapping)[2];
- const s8 (*queue_priority_mapping)[2];
+ s8 (*queue_tc_mapping)[2];
+ s8 (*queue_priority_mapping)[2];
};
#endif
--
1.7.9.5
------------------------------------------------------------------------------
Everyone hates slow websites. So do we.
Make your web apps faster with AppDynamics
Download AppDynamics Lite for free today:
http://ad.doubleclick.net/clk;258768047;13503038;j?
http://info.appdynamics.com/FreeJavaPerformanceDownload.html
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [RFC PATCH 04/13] dmaengine: edma: enable build for AM335x
[not found] ` <1348152226-13588-1-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
` (2 preceding siblings ...)
2012-09-20 14:43 ` [RFC PATCH 03/13] ARM: edma: add DT and runtime PM support for AM335x Matt Porter
@ 2012-09-20 14:43 ` Matt Porter
2012-09-20 14:43 ` [RFC PATCH 05/13] dma: Add TI EDMA device tree binding Matt Porter
` (9 subsequent siblings)
13 siblings, 0 replies; 52+ messages in thread
From: Matt Porter @ 2012-09-20 14:43 UTC (permalink / raw)
To: Tony Lindgren, Sekhar Nori, Grant Likely, Mark Brown,
Benoit Cousson, Russell King, Vinod Koul, Rob Landley,
Chris Ball
Cc: Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Dan Williams,
Linux SPI Devel List, Linux OMAP List, Linux ARM Kernel List
Enable config option on OMAP and adjust the
private EDMA API header to match the move
of the private EDMA API out of mach-davinci/
Signed-off-by: Matt Porter <mporter-l0cyMroinI0@public.gmane.org>
---
drivers/dma/Kconfig | 2 +-
drivers/dma/edma.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 0351719..24cd403 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -210,7 +210,7 @@ config SIRF_DMA
config TI_EDMA
tristate "TI EDMA support"
- depends on ARCH_DAVINCI
+ depends on ARCH_DAVINCI || ARCH_OMAP
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
default n
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index fdcf079..9f8f2fa 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -24,7 +24,7 @@
#include <linux/slab.h>
#include <linux/spinlock.h>
-#include <mach/edma.h>
+#include <asm/mach/edma.h>
#include "dmaengine.h"
#include "virt-dma.h"
--
1.7.9.5
------------------------------------------------------------------------------
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^ permalink raw reply related [flat|nested] 52+ messages in thread
* [RFC PATCH 05/13] dma: Add TI EDMA device tree binding
[not found] ` <1348152226-13588-1-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
` (3 preceding siblings ...)
2012-09-20 14:43 ` [RFC PATCH 04/13] dmaengine: edma: enable build " Matt Porter
@ 2012-09-20 14:43 ` Matt Porter
[not found] ` <1348152226-13588-6-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
2012-09-20 14:43 ` [RFC PATCH 06/13] ARM: omap: add hsmmc am33xx specific init Matt Porter
` (8 subsequent siblings)
13 siblings, 1 reply; 52+ messages in thread
From: Matt Porter @ 2012-09-20 14:43 UTC (permalink / raw)
To: Tony Lindgren, Sekhar Nori, Grant Likely, Mark Brown,
Benoit Cousson, Russell King, Vinod Koul, Rob Landley,
Chris Ball
Cc: Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Dan Williams,
Linux SPI Devel List, Linux OMAP List, Linux ARM Kernel List
The binding definition is based on the generic DMA controller
binding.
Signed-off-by: Matt Porter <mporter-l0cyMroinI0@public.gmane.org>
---
Documentation/devicetree/bindings/dma/ti-edma.txt | 49 +++++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/ti-edma.txt
diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt
new file mode 100644
index 0000000..06402eb
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/ti-edma.txt
@@ -0,0 +1,49 @@
+TI EDMA
+
+Required properties:
+- compatible : "ti,edma3"
+- ti,hwmods: Name of the hwmods associated to the EDMA
+- ti,edma-regions: Number of regions
+- ti,edma-slots: Number of slots
+- ti,edma-queue-tc-map: List of transfer control to queue mappings
+- ti,edma-queue-priority-map: List of queue priority mappings
+- ti,edma-default-queue: Default queue value
+
+Optional properties:
+- ti,edma-reserved-channels: List of reserved channel regions
+- ti,edma-reserved-slots: List of reserved slot regions
+
+Example:
+
+edma: edma@49000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x49000000 0x10000>;
+ interrupt-parent = <&intc>;
+ interrupts = <12 13 14>;
+ compatible = "ti,edma3";
+ ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
+ #dma-cells = <1>;
+ dma-channels = <64>;
+ ti,edma-regions = <4>;
+ ti,edma-slots = <256>;
+ ti,edma-reserved-channels = <0 2
+ 14 2
+ 26 6
+ 48 4
+ 56 8>;
+ ti,edma-reserved-slots = <0 2
+ 14 2
+ 26 6
+ 48 4
+ 56 8
+ 64 127>;
+ ti,edma-queue-tc-map = <0 0
+ 1 1
+ 2 2>;
+ ti,edma-queue-priority-map = <0 0
+ 1 1
+ 2 2>;
+ ti,edma-default-queue = <0>;
+};
+
--
1.7.9.5
------------------------------------------------------------------------------
Everyone hates slow websites. So do we.
Make your web apps faster with AppDynamics
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^ permalink raw reply related [flat|nested] 52+ messages in thread
* [RFC PATCH 06/13] ARM: omap: add hsmmc am33xx specific init
[not found] ` <1348152226-13588-1-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
` (4 preceding siblings ...)
2012-09-20 14:43 ` [RFC PATCH 05/13] dma: Add TI EDMA device tree binding Matt Porter
@ 2012-09-20 14:43 ` Matt Porter
2012-09-20 14:43 ` [RFC PATCH 07/13] mmc: omap_hsmmc: dma_request_slave_channel() support for DT platforms Matt Porter
` (7 subsequent siblings)
13 siblings, 0 replies; 52+ messages in thread
From: Matt Porter @ 2012-09-20 14:43 UTC (permalink / raw)
To: Tony Lindgren, Sekhar Nori, Grant Likely, Mark Brown,
Benoit Cousson, Russell King, Vinod Koul, Rob Landley,
Chris Ball
Cc: Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Dan Williams,
Linux SPI Devel List, Linux OMAP List, Linux ARM Kernel List
AM33xx requires special handling in hsmmc initialization
platform glue.
Signed-off-by: Matt Porter <mporter-l0cyMroinI0@public.gmane.org>
---
arch/arm/mach-omap2/hsmmc.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index a9675d8..679fb43 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -364,7 +364,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
else
mmc->slots[0].ocr_mask = c->ocr_mask;
- if (!soc_is_am35xx())
+ if (!soc_is_am35xx() && !soc_is_am33xx())
mmc->slots[0].features |= HSMMC_HAS_PBIAS;
if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
@@ -387,7 +387,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
}
}
- if (soc_is_am35xx())
+ if (soc_is_am35xx() || soc_is_am33xx())
mmc->slots[0].set_power = nop_mmc_set_power;
/* OMAP3630 HSMMC1 supports only 4-bit */
@@ -488,7 +488,8 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
if (res < 0)
goto free_mmc;
- omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
+ if (!soc_is_am33xx())
+ omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
name = "omap_hsmmc";
res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
--
1.7.9.5
------------------------------------------------------------------------------
Everyone hates slow websites. So do we.
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Download AppDynamics Lite for free today:
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^ permalink raw reply related [flat|nested] 52+ messages in thread
* [RFC PATCH 07/13] mmc: omap_hsmmc: dma_request_slave_channel() support for DT platforms
[not found] ` <1348152226-13588-1-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
` (5 preceding siblings ...)
2012-09-20 14:43 ` [RFC PATCH 06/13] ARM: omap: add hsmmc am33xx specific init Matt Porter
@ 2012-09-20 14:43 ` Matt Porter
2012-09-20 22:16 ` Tony Lindgren
2012-09-20 14:43 ` [RFC PATCH 08/13] mmc: omap_hsmmc: limit max_segs with the EDMA DMAC Matt Porter
` (6 subsequent siblings)
13 siblings, 1 reply; 52+ messages in thread
From: Matt Porter @ 2012-09-20 14:43 UTC (permalink / raw)
To: Tony Lindgren, Sekhar Nori, Grant Likely, Mark Brown,
Benoit Cousson, Russell King, Vinod Koul, Rob Landley,
Chris Ball
Cc: Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Dan Williams,
Linux SPI Devel List, Linux OMAP List, Linux ARM Kernel List
For platforms with DT populated, use dma_request_slave_channel()
to acquire the DMA channel. For !DT platforms, we fall back to
explicitly passing the omap_dma_filter_fn() to dma_request_channel().
Once all platforms boot from DT, the dma_request_channel() path can
be dropped.
Signed-off-by: Matt Porter <mporter-l0cyMroinI0@public.gmane.org>
---
drivers/mmc/host/omap_hsmmc.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 3a09f93..c82d0ab 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -1923,14 +1923,26 @@ static int __devinit omap_hsmmc_probe(struct platform_device *pdev)
dma_cap_zero(mask);
dma_cap_set(DMA_SLAVE, mask);
- host->rx_chan = dma_request_channel(mask, omap_dma_filter_fn, &rx_req);
+ if (pdev->dev.of_node)
+ host->rx_chan =
+ dma_request_slave_channel(&pdev->dev, "rx");
+ else
+ host->rx_chan = dma_request_channel(mask,
+ omap_dma_filter_fn,
+ &rx_req);
if (!host->rx_chan) {
dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
ret = -ENXIO;
goto err_irq;
}
- host->tx_chan = dma_request_channel(mask, omap_dma_filter_fn, &tx_req);
+ if (pdev->dev.of_node)
+ host->tx_chan =
+ dma_request_slave_channel(&pdev->dev, "tx");
+ else
+ host->tx_chan = dma_request_channel(mask,
+ omap_dma_filter_fn,
+ &tx_req);
if (!host->tx_chan) {
dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
ret = -ENXIO;
--
1.7.9.5
------------------------------------------------------------------------------
Everyone hates slow websites. So do we.
Make your web apps faster with AppDynamics
Download AppDynamics Lite for free today:
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http://info.appdynamics.com/FreeJavaPerformanceDownload.html
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [RFC PATCH 08/13] mmc: omap_hsmmc: limit max_segs with the EDMA DMAC
[not found] ` <1348152226-13588-1-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
` (6 preceding siblings ...)
2012-09-20 14:43 ` [RFC PATCH 07/13] mmc: omap_hsmmc: dma_request_slave_channel() support for DT platforms Matt Porter
@ 2012-09-20 14:43 ` Matt Porter
2012-09-21 17:15 ` S, Venkatraman
2012-09-20 14:43 ` [RFC PATCH 09/13] mmc: omap_hsmmc: add generic DMA request support to the DT binding Matt Porter
` (5 subsequent siblings)
13 siblings, 1 reply; 52+ messages in thread
From: Matt Porter @ 2012-09-20 14:43 UTC (permalink / raw)
To: Tony Lindgren, Sekhar Nori, Grant Likely, Mark Brown,
Benoit Cousson, Russell King, Vinod Koul, Rob Landley,
Chris Ball
Cc: Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Dan Williams,
Linux SPI Devel List, Linux OMAP List, Linux ARM Kernel List
The EDMA DMAC has a hardware limitation that prevents supporting
scatter gather lists with any number of segments. Since the EDMA
DMA Engine driver sets the maximum segments to 16, we do the
same.
Note: this can be removed once the DMA Engine API supports an
API to query the DMAC's segment limitations.
Signed-off-by: Matt Porter <mporter-l0cyMroinI0@public.gmane.org>
---
drivers/mmc/host/omap_hsmmc.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index c82d0ab..61b54ee 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -1885,6 +1885,16 @@ static int __devinit omap_hsmmc_probe(struct platform_device *pdev)
* as we want. */
mmc->max_segs = 1024;
+ /* Eventually we should get our max_segs limitation for EDMA by
+ * querying the dmaengine API */
+ if (pdev->dev.of_node) {
+ struct device_node *parent = pdev->dev.of_node->parent;
+ struct device_node *node;
+ node = of_find_node_by_name(parent, "edma");
+ if (node)
+ mmc->max_segs = 16;
+ }
+
mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
--
1.7.9.5
------------------------------------------------------------------------------
Everyone hates slow websites. So do we.
Make your web apps faster with AppDynamics
Download AppDynamics Lite for free today:
http://ad.doubleclick.net/clk;258768047;13503038;j?
http://info.appdynamics.com/FreeJavaPerformanceDownload.html
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [RFC PATCH 09/13] mmc: omap_hsmmc: add generic DMA request support to the DT binding
[not found] ` <1348152226-13588-1-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
` (7 preceding siblings ...)
2012-09-20 14:43 ` [RFC PATCH 08/13] mmc: omap_hsmmc: limit max_segs with the EDMA DMAC Matt Porter
@ 2012-09-20 14:43 ` Matt Porter
2012-09-20 14:43 ` [RFC PATCH 10/13] spi: omap2-mcspi: dma_request_slave_channel() support for DT platforms Matt Porter
` (4 subsequent siblings)
13 siblings, 0 replies; 52+ messages in thread
From: Matt Porter @ 2012-09-20 14:43 UTC (permalink / raw)
To: Tony Lindgren, Sekhar Nori, Grant Likely, Mark Brown,
Benoit Cousson, Russell King, Vinod Koul, Rob Landley,
Chris Ball
Cc: Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Dan Williams,
Linux SPI Devel List, Linux OMAP List, Linux ARM Kernel List
The binding definition is based on the generic DMA request binding.
Signed-off-by: Matt Porter <mporter-l0cyMroinI0@public.gmane.org>
---
.../devicetree/bindings/mmc/ti-omap-hsmmc.txt | 25 +++++++++++++++++++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
index be76a23..d1b8932 100644
--- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
+++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
@@ -19,8 +19,28 @@ ti,dual-volt: boolean, supports dual voltage cards
"supply-name" examples are "vmmc", "vmmc_aux" etc
ti,non-removable: non-removable slot (like eMMC)
ti,needs-special-reset: Requires a special softreset sequence
+dmas: DMA controller phandle and DMA request value ordered pair
+One tx and one rx pair is required.
+dma-names: DMA request names. These strings correspond 1:1 with
+the ordered pairs in dmas. The RX request must be "rx" and the
+TX request must be "tx".
+
+Examples:
+
+[hwmod populated DMA resources]
+
+ mmc1: mmc@0x4809c000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x4809c000 0x400>;
+ ti,hwmods = "mmc1";
+ ti,dual-volt;
+ bus-width = <4>;
+ vmmc-supply = <&vmmc>; /* phandle to regulator node */
+ ti,non-removable;
+ };
+
+[generic DMA request binding]
-Example:
mmc1: mmc@0x4809c000 {
compatible = "ti,omap4-hsmmc";
reg = <0x4809c000 0x400>;
@@ -29,4 +49,7 @@ Example:
bus-width = <4>;
vmmc-supply = <&vmmc>; /* phandle to regulator node */
ti,non-removable;
+ dmas = <&edma 24
+ &edma 25>;
+ dma-names = "tx", "rx";
};
--
1.7.9.5
------------------------------------------------------------------------------
Everyone hates slow websites. So do we.
Make your web apps faster with AppDynamics
Download AppDynamics Lite for free today:
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http://info.appdynamics.com/FreeJavaPerformanceDownload.html
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [RFC PATCH 10/13] spi: omap2-mcspi: dma_request_slave_channel() support for DT platforms
[not found] ` <1348152226-13588-1-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
` (8 preceding siblings ...)
2012-09-20 14:43 ` [RFC PATCH 09/13] mmc: omap_hsmmc: add generic DMA request support to the DT binding Matt Porter
@ 2012-09-20 14:43 ` Matt Porter
2012-09-20 22:09 ` Tony Lindgren
2012-09-20 14:43 ` [RFC PATCH 11/13] spi: omap2-mcspi: add generic DMA request support to the DT binding Matt Porter
` (3 subsequent siblings)
13 siblings, 1 reply; 52+ messages in thread
From: Matt Porter @ 2012-09-20 14:43 UTC (permalink / raw)
To: Tony Lindgren, Sekhar Nori, Grant Likely, Mark Brown,
Benoit Cousson, Russell King, Vinod Koul, Rob Landley,
Chris Ball
Cc: Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Dan Williams,
Linux SPI Devel List, Linux OMAP List, Linux ARM Kernel List
For platforms with DT populated, use dma_request_slave_channel()
to acquire the DMA channel. For !DT platforms, we fall back to
explicitly passing the omap_dma_filter_fn() to dma_request_channel().
Once all platforms boot from DT, the dma_request_channel() path can
be dropped.
Signed-off-by: Matt Porter <mporter-l0cyMroinI0@public.gmane.org>
---
drivers/spi/spi-omap2-mcspi.c | 68 +++++++++++++++++++++++++++++------------
1 file changed, 48 insertions(+), 20 deletions(-)
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index 9502566..1cf1072 100644
--- a/drivers/spi/spi-omap2-mcspi.c
+++ b/drivers/spi/spi-omap2-mcspi.c
@@ -104,6 +104,9 @@ struct omap2_mcspi_dma {
struct completion dma_tx_completion;
struct completion dma_rx_completion;
+
+ char dma_rx_ch_name[14];
+ char dma_tx_ch_name[14];
};
/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
@@ -798,14 +801,26 @@ static int omap2_mcspi_request_dma(struct spi_device *spi)
dma_cap_zero(mask);
dma_cap_set(DMA_SLAVE, mask);
sig = mcspi_dma->dma_rx_sync_dev;
- mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
+ if (spi->dev.of_node)
+ mcspi_dma->dma_rx =
+ dma_request_slave_channel(&master->dev,
+ mcspi_dma->dma_rx_ch_name);
+ else
+ mcspi_dma->dma_rx =
+ dma_request_channel(mask, omap_dma_filter_fn, &sig);
if (!mcspi_dma->dma_rx) {
dev_err(&spi->dev, "no RX DMA engine channel for McSPI\n");
return -EAGAIN;
}
sig = mcspi_dma->dma_tx_sync_dev;
- mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
+ if (spi->dev.of_node)
+ mcspi_dma->dma_tx =
+ dma_request_slave_channel(&master->dev,
+ mcspi_dma->dma_tx_ch_name);
+ else
+ mcspi_dma->dma_tx =
+ dma_request_channel(mask, omap_dma_filter_fn, &sig);
if (!mcspi_dma->dma_tx) {
dev_err(&spi->dev, "no TX DMA engine channel for McSPI\n");
dma_release_channel(mcspi_dma->dma_rx);
@@ -1194,29 +1209,42 @@ static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
goto free_master;
for (i = 0; i < master->num_chipselect; i++) {
- char dma_ch_name[14];
+ char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name;
+ char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name;
struct resource *dma_res;
- sprintf(dma_ch_name, "rx%d", i);
- dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
- dma_ch_name);
- if (!dma_res) {
- dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
- status = -ENODEV;
- break;
- }
+ sprintf(dma_rx_ch_name, "rx%d", i);
+ if (!pdev->dev.of_node) {
+ dma_res =
+ platform_get_resource_byname(pdev,
+ IORESOURCE_DMA,
+ dma_rx_ch_name);
+ if (!dma_res) {
+ dev_dbg(&pdev->dev,
+ "cannot get DMA RX channel\n");
+ status = -ENODEV;
+ break;
+ }
- mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
- sprintf(dma_ch_name, "tx%d", i);
- dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
- dma_ch_name);
- if (!dma_res) {
- dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
- status = -ENODEV;
- break;
+ mcspi->dma_channels[i].dma_rx_sync_dev =
+ dma_res->start;
}
+ sprintf(dma_tx_ch_name, "tx%d", i);
+ if (!pdev->dev.of_node) {
+ dma_res =
+ platform_get_resource_byname(pdev,
+ IORESOURCE_DMA,
+ dma_tx_ch_name);
+ if (!dma_res) {
+ dev_dbg(&pdev->dev,
+ "cannot get DMA TX channel\n");
+ status = -ENODEV;
+ break;
+ }
- mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
+ mcspi->dma_channels[i].dma_tx_sync_dev =
+ dma_res->start;
+ }
}
if (status < 0)
--
1.7.9.5
------------------------------------------------------------------------------
Everyone hates slow websites. So do we.
Make your web apps faster with AppDynamics
Download AppDynamics Lite for free today:
http://ad.doubleclick.net/clk;258768047;13503038;j?
http://info.appdynamics.com/FreeJavaPerformanceDownload.html
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [RFC PATCH 11/13] spi: omap2-mcspi: add generic DMA request support to the DT binding
[not found] ` <1348152226-13588-1-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
` (9 preceding siblings ...)
2012-09-20 14:43 ` [RFC PATCH 10/13] spi: omap2-mcspi: dma_request_slave_channel() support for DT platforms Matt Porter
@ 2012-09-20 14:43 ` Matt Porter
2012-09-20 14:43 ` [RFC PATCH 12/13] ARM: dts: add am33xx EDMA support Matt Porter
` (2 subsequent siblings)
13 siblings, 0 replies; 52+ messages in thread
From: Matt Porter @ 2012-09-20 14:43 UTC (permalink / raw)
To: Tony Lindgren, Sekhar Nori, Grant Likely, Mark Brown,
Benoit Cousson, Russell King, Vinod Koul, Rob Landley,
Chris Ball
Cc: Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Dan Williams,
Linux SPI Devel List, Linux OMAP List, Linux ARM Kernel List
The binding definition is based on the generic DMA request binding.
Signed-off-by: Matt Porter <mporter-l0cyMroinI0@public.gmane.org>
---
Documentation/devicetree/bindings/spi/omap-spi.txt | 27 +++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/spi/omap-spi.txt b/Documentation/devicetree/bindings/spi/omap-spi.txt
index 81df374..11aff04 100644
--- a/Documentation/devicetree/bindings/spi/omap-spi.txt
+++ b/Documentation/devicetree/bindings/spi/omap-spi.txt
@@ -7,8 +7,18 @@ Required properties:
- ti,spi-num-cs : Number of chipselect supported by the instance.
- ti,hwmods: Name of the hwmod associated to the McSPI
+Optional properties:
+- dmas: List of DMA controller phandle and DMA request ordered
+ pairs. One tx and one rx pair is required for each chip
+ select.
+- dma-names: List of DMA request names. These strings correspond
+ 1:1 with the ordered pairs in dmas. The string naming is
+ to be "rxN" and "txN" for RX and TX requests,
+ respectively, where N equals the chip select number.
-Example:
+Examples:
+
+[hwmod populated DMA resources]
mcspi1: mcspi@1 {
#address-cells = <1>;
@@ -18,3 +28,18 @@ mcspi1: mcspi@1 {
ti,spi-num-cs = <4>;
};
+[generic DMA request binding]
+
+mcspi1: mcspi@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "ti,omap4-mcspi";
+ ti,hwmods = "mcspi1";
+ ti,spi-num-cs = <2>;
+ dmas = <&edma 42
+ &edma 43
+ &edma 44
+ &edma 45>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
+};
+
--
1.7.9.5
------------------------------------------------------------------------------
Everyone hates slow websites. So do we.
Make your web apps faster with AppDynamics
Download AppDynamics Lite for free today:
http://ad.doubleclick.net/clk;258768047;13503038;j?
http://info.appdynamics.com/FreeJavaPerformanceDownload.html
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [RFC PATCH 12/13] ARM: dts: add am33xx EDMA support
[not found] ` <1348152226-13588-1-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
` (10 preceding siblings ...)
2012-09-20 14:43 ` [RFC PATCH 11/13] spi: omap2-mcspi: add generic DMA request support to the DT binding Matt Porter
@ 2012-09-20 14:43 ` Matt Porter
2012-09-20 14:43 ` [RFC PATCH 13/13] Documentation: add schedule for removing private EDMA API Matt Porter
2012-09-21 8:27 ` [RFC PATCH 00/13] DMA Engine support for AM33xx Hebbar, Gururaja
13 siblings, 0 replies; 52+ messages in thread
From: Matt Porter @ 2012-09-20 14:43 UTC (permalink / raw)
To: Tony Lindgren, Sekhar Nori, Grant Likely, Mark Brown,
Benoit Cousson, Russell King, Vinod Koul, Rob Landley,
Chris Ball
Cc: Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Dan Williams,
Linux SPI Devel List, Linux OMAP List, Linux ARM Kernel List
Adds support for the defined EDMA, generic DMA controller, and
DMA request bindings for mmc and spi.
Signed-off-by: Matt Porter <mporter-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/am33xx.dtsi | 46 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index e8033eb..c14a61d 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -86,6 +86,36 @@
reg = <0x48200000 0x1000>;
};
+ edma: edma@49000000 {
+ compatible = "ti,edma3";
+ ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
+ reg = <0x49000000 0x10000>;
+ interrupt-parent = <&intc>;
+ interrupts = <12 13 14>;
+ #dma-cells = <1>;
+ dma-channels = <64>;
+ ti,edma-regions = <4>;
+ ti,edma-slots = <256>;
+ ti,edma-reserved-channels = <0 2
+ 14 2
+ 26 6
+ 48 4
+ 56 8>;
+ ti,edma-reserved-slots = <0 2
+ 14 2
+ 26 6
+ 48 4
+ 56 8
+ 64 127>;
+ ti,edma-queue-tc-map = <0 0
+ 1 1
+ 2 2>;
+ ti,edma-queue-priority-map = <0 0
+ 1 1
+ 2 2>;
+ ti,edma-default-queue = <0>;
+ };
+
gpio0: gpio@44e07000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio1";
@@ -290,6 +320,9 @@
ti,hwmods = "mmc1";
ti,dual-volt;
ti,needs-special-reset;
+ dmas = <&edma 24
+ &edma 25>;
+ dma-names = "tx", "rx";
};
mmc2: mmc@481D8000 {
@@ -297,6 +330,9 @@
ti,hwmods = "mmc2";
ti,needs-special-reset;
status = "disabled";
+ dmas = <&edma 2
+ &edma 3>;
+ dma-names = "tx", "rx";
};
mmc3: mmc@47810000 {
@@ -339,6 +375,11 @@
reg = <0x48030000 0x400>;
interrupt-parent = <&intc>;
interrupt = <65>;
+ dmas = <&edma 16
+ &edma 17
+ &edma 18
+ &edma 19>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
ti,spi-num-cs = <2>;
ti,hwmods = "spi0";
status = "disabled";
@@ -351,6 +392,11 @@
reg = <0x481a0000 0x400>;
interrupt-parent = <&intc>;
interrupt = <125>;
+ dmas = <&edma 42
+ &edma 43
+ &edma 44
+ &edma 45>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
ti,spi-num-cs = <2>;
ti,hwmods = "spi1";
status = "disabled";
--
1.7.9.5
------------------------------------------------------------------------------
Everyone hates slow websites. So do we.
Make your web apps faster with AppDynamics
Download AppDynamics Lite for free today:
http://ad.doubleclick.net/clk;258768047;13503038;j?
http://info.appdynamics.com/FreeJavaPerformanceDownload.html
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [RFC PATCH 13/13] Documentation: add schedule for removing private EDMA API
[not found] ` <1348152226-13588-1-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
` (11 preceding siblings ...)
2012-09-20 14:43 ` [RFC PATCH 12/13] ARM: dts: add am33xx EDMA support Matt Porter
@ 2012-09-20 14:43 ` Matt Porter
2012-09-20 15:58 ` Mark Brown
2012-09-21 8:27 ` [RFC PATCH 00/13] DMA Engine support for AM33xx Hebbar, Gururaja
13 siblings, 1 reply; 52+ messages in thread
From: Matt Porter @ 2012-09-20 14:43 UTC (permalink / raw)
To: Tony Lindgren, Sekhar Nori, Grant Likely, Mark Brown,
Benoit Cousson, Russell King, Vinod Koul, Rob Landley,
Chris Ball
Cc: Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Dan Williams,
Linux SPI Devel List, Linux OMAP List, Linux ARM Kernel List
The davinci-pcm driver is the last in-kernel user of the private
EDMA API. Once it has been converted to DMA Engine API the
private EDMA API functionality can be folded into the EDMA DMA
Engine driver and removed.
Signed-off-by: Matt Porter <mporter-l0cyMroinI0@public.gmane.org>
---
Documentation/feature-removal-schedule.txt | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/feature-removal-schedule.txt b/Documentation/feature-removal-schedule.txt
index f4d8c71..64109e6 100644
--- a/Documentation/feature-removal-schedule.txt
+++ b/Documentation/feature-removal-schedule.txt
@@ -637,3 +637,13 @@ Who: Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>,
Santosh Shilimkar <santosh.shilimkar-l0cyMroinI0@public.gmane.org>
----------------------------
+
+What: EDMA private DMA implementation
+When: 2013
+Why: We have a DMA engine implementation; all users should be updated
+ to use this rather than persisting with the old APIs. The old APIs
+ block merging the old DMA engine implementation into the DMA
+ engine driver.
+Who: Matt Porter <mporter-l0cyMroinI0@public.gmane.org>
+
+----------------------------
--
1.7.9.5
------------------------------------------------------------------------------
Everyone hates slow websites. So do we.
Make your web apps faster with AppDynamics
Download AppDynamics Lite for free today:
http://ad.doubleclick.net/clk;258768047;13503038;j?
http://info.appdynamics.com/FreeJavaPerformanceDownload.html
^ permalink raw reply related [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 13/13] Documentation: add schedule for removing private EDMA API
2012-09-20 14:43 ` [RFC PATCH 13/13] Documentation: add schedule for removing private EDMA API Matt Porter
@ 2012-09-20 15:58 ` Mark Brown
2012-09-20 16:05 ` Matt Porter
0 siblings, 1 reply; 52+ messages in thread
From: Mark Brown @ 2012-09-20 15:58 UTC (permalink / raw)
To: Matt Porter
Cc: Tony Lindgren, Sekhar Nori, Grant Likely, Benoit Cousson,
Russell King, Vinod Koul, Rob Landley, Chris Ball,
Devicetree Discuss, Linux OMAP List, Linux ARM Kernel List,
Linux DaVinci Kernel List, Linux Kernel Mailing List,
Linux Documentation List, Linux MMC List, Linux SPI Devel List,
Arnd Bergmann, Dan Williams, Rob Herring
On Thu, Sep 20, 2012 at 10:43:46AM -0400, Matt Porter wrote:
> Documentation/feature-removal-schedule.txt | 10 ++++++++++
> 1 file changed, 10 insertions(+)
We decided at kernel summit that we'd stop bothering with this, it's
mostly just bitrot and rarely read. I guess the ASoC driver update
isn't ready yet?
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 13/13] Documentation: add schedule for removing private EDMA API
2012-09-20 15:58 ` Mark Brown
@ 2012-09-20 16:05 ` Matt Porter
0 siblings, 0 replies; 52+ messages in thread
From: Matt Porter @ 2012-09-20 16:05 UTC (permalink / raw)
To: Mark Brown
Cc: Linux DaVinci Kernel List, Linux OMAP List, Russell King,
Benoit Cousson, Arnd Bergmann, Linux Documentation List,
Tony Lindgren, Linux MMC List, Devicetree Discuss,
Linux Kernel Mailing List, Rob Herring, Grant Likely, Vinod Koul,
Rob Landley, Dan Williams, Linux SPI Devel List, Chris Ball,
Linux ARM Kernel List
On Thu, Sep 20, 2012 at 04:58:58PM +0100, Mark Brown wrote:
> On Thu, Sep 20, 2012 at 10:43:46AM -0400, Matt Porter wrote:
>
> > Documentation/feature-removal-schedule.txt | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
>
> We decided at kernel summit that we'd stop bothering with this, it's
> mostly just bitrot and rarely read. I guess the ASoC driver update
> isn't ready yet?
Ok, I'll drop this from the series.
No, I'm just getting real time now to work on the davinci-pcm dma engine
conversion and cyclic dma support for edma. That driver is somewhat of a
mess as it has some older platforms dependent on SRAM-based ping-pong
buffering and that all need to be sorted during this. It is the only
remaining blocker though for getting rid of the private API.
-Matt
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 10/13] spi: omap2-mcspi: dma_request_slave_channel() support for DT platforms
2012-09-20 14:43 ` [RFC PATCH 10/13] spi: omap2-mcspi: dma_request_slave_channel() support for DT platforms Matt Porter
@ 2012-09-20 22:09 ` Tony Lindgren
2012-09-21 8:16 ` Arnd Bergmann
0 siblings, 1 reply; 52+ messages in thread
From: Tony Lindgren @ 2012-09-20 22:09 UTC (permalink / raw)
To: Matt Porter
Cc: Sekhar Nori, Grant Likely, Mark Brown, Benoit Cousson,
Russell King, Vinod Koul, Rob Landley, Chris Ball,
Devicetree Discuss, Linux OMAP List, Linux ARM Kernel List,
Linux DaVinci Kernel List, Linux Kernel Mailing List,
Linux Documentation List, Linux MMC List, Linux SPI Devel List,
Arnd Bergmann, Dan Williams, Rob Herring
* Matt Porter <mporter@ti.com> [120920 07:43]:
> For platforms with DT populated, use dma_request_slave_channel()
> to acquire the DMA channel. For !DT platforms, we fall back to
> explicitly passing the omap_dma_filter_fn() to dma_request_channel().
> Once all platforms boot from DT, the dma_request_channel() path can
> be dropped.
>
> Signed-off-by: Matt Porter <mporter@ti.com>
> ---
> drivers/spi/spi-omap2-mcspi.c | 68 +++++++++++++++++++++++++++++------------
> 1 file changed, 48 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
> index 9502566..1cf1072 100644
> --- a/drivers/spi/spi-omap2-mcspi.c
> +++ b/drivers/spi/spi-omap2-mcspi.c
> @@ -104,6 +104,9 @@ struct omap2_mcspi_dma {
>
> struct completion dma_tx_completion;
> struct completion dma_rx_completion;
> +
> + char dma_rx_ch_name[14];
> + char dma_tx_ch_name[14];
> };
>
> /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
> @@ -798,14 +801,26 @@ static int omap2_mcspi_request_dma(struct spi_device *spi)
> dma_cap_zero(mask);
> dma_cap_set(DMA_SLAVE, mask);
> sig = mcspi_dma->dma_rx_sync_dev;
> - mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
> + if (spi->dev.of_node)
> + mcspi_dma->dma_rx =
> + dma_request_slave_channel(&master->dev,
> + mcspi_dma->dma_rx_ch_name);
> + else
> + mcspi_dma->dma_rx =
> + dma_request_channel(mask, omap_dma_filter_fn, &sig);
> if (!mcspi_dma->dma_rx) {
> dev_err(&spi->dev, "no RX DMA engine channel for McSPI\n");
> return -EAGAIN;
> }
>
Hmm this does not look nice.. We should be able to somehow not to care about
the configuration at the mcspi driver level.
Regards,
Tony
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 07/13] mmc: omap_hsmmc: dma_request_slave_channel() support for DT platforms
2012-09-20 14:43 ` [RFC PATCH 07/13] mmc: omap_hsmmc: dma_request_slave_channel() support for DT platforms Matt Porter
@ 2012-09-20 22:16 ` Tony Lindgren
0 siblings, 0 replies; 52+ messages in thread
From: Tony Lindgren @ 2012-09-20 22:16 UTC (permalink / raw)
To: Matt Porter
Cc: Sekhar Nori, Grant Likely, Mark Brown, Benoit Cousson,
Russell King, Vinod Koul, Rob Landley, Chris Ball,
Devicetree Discuss, Linux OMAP List, Linux ARM Kernel List,
Linux DaVinci Kernel List, Linux Kernel Mailing List,
Linux Documentation List, Linux MMC List, Linux SPI Devel List,
Arnd Bergmann, Dan Williams, Rob Herring
* Matt Porter <mporter@ti.com> [120920 07:43]:
> For platforms with DT populated, use dma_request_slave_channel()
> to acquire the DMA channel. For !DT platforms, we fall back to
> explicitly passing the omap_dma_filter_fn() to dma_request_channel().
> Once all platforms boot from DT, the dma_request_channel() path can
> be dropped.
>
> Signed-off-by: Matt Porter <mporter@ti.com>
> ---
> drivers/mmc/host/omap_hsmmc.c | 16 ++++++++++++++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
> index 3a09f93..c82d0ab 100644
> --- a/drivers/mmc/host/omap_hsmmc.c
> +++ b/drivers/mmc/host/omap_hsmmc.c
> @@ -1923,14 +1923,26 @@ static int __devinit omap_hsmmc_probe(struct platform_device *pdev)
> dma_cap_zero(mask);
> dma_cap_set(DMA_SLAVE, mask);
>
> - host->rx_chan = dma_request_channel(mask, omap_dma_filter_fn, &rx_req);
> + if (pdev->dev.of_node)
> + host->rx_chan =
> + dma_request_slave_channel(&pdev->dev, "rx");
> + else
> + host->rx_chan = dma_request_channel(mask,
> + omap_dma_filter_fn,
> + &rx_req);
> if (!host->rx_chan) {
> dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
> ret = -ENXIO;
> goto err_irq;
> }
>
> - host->tx_chan = dma_request_channel(mask, omap_dma_filter_fn, &tx_req);
> + if (pdev->dev.of_node)
> + host->tx_chan =
> + dma_request_slave_channel(&pdev->dev, "tx");
> + else
> + host->tx_chan = dma_request_channel(mask,
> + omap_dma_filter_fn,
> + &tx_req);
> if (!host->tx_chan) {
> dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
> ret = -ENXIO;
>
Here to the omap_hsmmc.c driver should not need to care about which
way to request the dma channels.
Regards,
Tony
^ permalink raw reply [flat|nested] 52+ messages in thread
* RE: [RFC PATCH 01/13] ARM: davinci: move private EDMA API to arm/common
[not found] ` <1348152226-13588-2-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
@ 2012-09-21 7:10 ` Hebbar, Gururaja
2012-09-21 18:24 ` Matt Porter
0 siblings, 1 reply; 52+ messages in thread
From: Hebbar, Gururaja @ 2012-09-21 7:10 UTC (permalink / raw)
To: Porter, Matt, Tony Lindgren, Nori, Sekhar, Grant Likely,
Mark Brown, Cousson, Benoit, Russell King, Vinod Koul,
Rob Landley, Chris Ball
Cc: Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Williams,
Linux SPI Devel List, Linux OMAP List, Dan,
Linux ARM Kernel List
On Thu, Sep 20, 2012 at 20:13:34, Porter, Matt wrote:
> Move mach-davinci/dma.c to common/edma.c so it can be used
> by OMAP (specifically AM33xx atm) as well. This just moves
> the private EDMA API but does not support OMAP.
>
> Signed-off-by: Matt Porter <mporter-l0cyMroinI0@public.gmane.org>
> ---
> arch/arm/Kconfig | 1 +
> arch/arm/common/Kconfig | 3 +
> arch/arm/common/Makefile | 1 +
> arch/arm/common/edma.c | 1588 ++++++++++++++++++++++++++++
> arch/arm/include/asm/mach/edma.h | 267 +++++
> arch/arm/mach-davinci/Makefile | 2 +-
> arch/arm/mach-davinci/devices.c | 3 +-
> arch/arm/mach-davinci/dm355.c | 2 +-
> arch/arm/mach-davinci/dm365.c | 2 +-
> arch/arm/mach-davinci/dm644x.c | 2 +-
> arch/arm/mach-davinci/dm646x.c | 2 +-
> arch/arm/mach-davinci/dma.c | 1588 ----------------------------
Please use –M option, while generating patches via git-format-patch.
This reduces the patch size if files are copied/renamed/moved.
> arch/arm/mach-davinci/include/mach/asp.h | 2 +-
> arch/arm/mach-davinci/include/mach/da8xx.h | 3 +-
> arch/arm/mach-davinci/include/mach/edma.h | 267 -----
> arch/arm/mach-davinci/include/mach/spi.h | 2 +-
> arch/arm/plat-omap/Kconfig | 1 +
> 17 files changed, 1872 insertions(+), 1864 deletions(-)
> create mode 100644 arch/arm/common/edma.c
> create mode 100644 arch/arm/include/asm/mach/edma.h
> delete mode 100644 arch/arm/mach-davinci/dma.c
> delete mode 100644 arch/arm/mach-davinci/include/mach/edma.h
>
...snip...
...snip...
...snip...
>
> --
> 1.7.9.5
>
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
>
Regards,
Gururaja
------------------------------------------------------------------------------
Got visibility?
Most devs has no idea what their production app looks like.
Find out how fast your code is with AppDynamics Lite.
http://ad.doubleclick.net/clk;262219671;13503038;y?
http://info.appdynamics.com/FreeJavaPerformanceDownload.html
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 10/13] spi: omap2-mcspi: dma_request_slave_channel() support for DT platforms
2012-09-20 22:09 ` Tony Lindgren
@ 2012-09-21 8:16 ` Arnd Bergmann
2012-09-21 15:42 ` Tony Lindgren
0 siblings, 1 reply; 52+ messages in thread
From: Arnd Bergmann @ 2012-09-21 8:16 UTC (permalink / raw)
To: Tony Lindgren
Cc: Matt Porter, Sekhar Nori, Grant Likely, Mark Brown,
Benoit Cousson, Russell King, Vinod Koul, Rob Landley,
Chris Ball, Devicetree Discuss, Linux OMAP List,
Linux ARM Kernel List, Linux DaVinci Kernel List,
Linux Kernel Mailing List, Linux Documentation List,
Linux MMC List, Linux SPI Devel List, Dan Williams, Rob Herring
On Thursday 20 September 2012, Tony Lindgren wrote:
> > /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
> > @@ -798,14 +801,26 @@ static int omap2_mcspi_request_dma(struct spi_device *spi)
> > dma_cap_zero(mask);
> > dma_cap_set(DMA_SLAVE, mask);
> > sig = mcspi_dma->dma_rx_sync_dev;
> > - mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
> > + if (spi->dev.of_node)
> > + mcspi_dma->dma_rx =
> > + dma_request_slave_channel(&master->dev,
> > + mcspi_dma->dma_rx_ch_name);
> > + else
> > + mcspi_dma->dma_rx =
> > + dma_request_channel(mask, omap_dma_filter_fn, &sig);
> > if (!mcspi_dma->dma_rx) {
> > dev_err(&spi->dev, "no RX DMA engine channel for McSPI\n");
> > return -EAGAIN;
> > }
> >
>
> Hmm this does not look nice.. We should be able to somehow not to care about
> the configuration at the mcspi driver level.
I agree, but as far as I understand Vinod's plans, we would actually move
all drivers over to dma_request_slave_channel() when we have an interface
to register the lookup tables from platform code.
I think the above is ok for a transitional phase and we can remove the
fallback path when we have converted all platforms using this driver
to either use DT or move to the new style way of passing the channel
configuration.
Arnd
^ permalink raw reply [flat|nested] 52+ messages in thread
* RE: [RFC PATCH 00/13] DMA Engine support for AM33xx
[not found] ` <1348152226-13588-1-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
` (12 preceding siblings ...)
2012-09-20 14:43 ` [RFC PATCH 13/13] Documentation: add schedule for removing private EDMA API Matt Porter
@ 2012-09-21 8:27 ` Hebbar, Gururaja
2012-09-21 18:22 ` Matt Porter
13 siblings, 1 reply; 52+ messages in thread
From: Hebbar, Gururaja @ 2012-09-21 8:27 UTC (permalink / raw)
To: Porter, Matt, Tony Lindgren, Nori, Sekhar, Grant Likely,
Mark Brown, Cousson, Benoit, Russell King, Vinod Koul,
Rob Landley, Chris Ball
Cc: Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Williams,
Linux SPI Devel List, Linux OMAP List, Dan,
Linux ARM Kernel List
On Thu, Sep 20, 2012 at 20:13:33, Porter, Matt wrote:
> This series adds DMA Engine support for AM33xx, which uses
> an EDMA DMAC. The EDMA DMAC has been previously supported by only
> a private API implementation (much like the situation with OMAP
> DMA) found on the DaVinci family of SoCs.
>
> There are a mind-boggling number of dependencies for this series:
>
> - Jon Hunter's OF DMA helpers series
> https://patchwork.kernel.org/patch/1461061/
> https://patchwork.kernel.org/patch/1461051/
> - Patch to address OF DMA helpers naming issues:
> https://patchwork.kernel.org/patch/1477921/
> - EDMA DMA Engine wrapper driver in linux-next
> c2dde5f8f2095d7c623ff3565c1462e190272273
> - EDMA DMA Engine wrapper driver bug fix:
> https://patchwork.kernel.org/patch/1474411/
> - A huge number of patches in linux-next for AM33xx boot
> (too numerous to list)
>
> The approach taken is similar to how OMAP DMA is being converted to
> DMA Engine support. With the functional EDMA private API already
> existing in mach-davinci/dma.c, we first move that to an ARM common
> area so it can be shared. Adding DT and runtime PM support to the
> private EDMA API implementation allows it to run on AM33xx. AM33xx
> *only* boots using DT so we leverage Jon's generic DT DMA helpers to
> register EDMA DMAC with the of_dma framework and then add support
> for calling the dma_request_slave_channel() API to both the mmc
> and spi drivers.
>
> What works? Well, with this series we now have MMC and SPI support
> on AM33xx. The only caveat for MMC is that the mmc3 controller has
> its events on the crossbar and is not usable right now.
>
> This is tested on BeagleBone with a SPI framebuffer driver and SD
> card.
>
> After this series, the plan is to convert the last in-tree user
> of the private EDMA API (davinci-pcm/mcasp) and then eliminate
> the private EDMA API by folding its functionality into
> drivers/dma/edma.c.
>
> TODO:
> add AM33xx crossbar support to the private EDMA API
> (any EDMA events on the crossbar are not supported)
>
Can you please mention the base repo you have taken as starting point.
(repo + extra patches ...).
This will help us to test the code.
This is because I looked at the patch 12/13 and I see that mmc
device-node is modified. But in mainline I don’t see device
node for mmc (yet).
> Matt Porter (13):
> ARM: davinci: move private EDMA API to arm/common
> ARM: edma: remove unused transfer controller handlers
> ARM: edma: add DT and runtime PM support for AM335x
> dmaengine: edma: enable build for AM335x
> dma: Add TI EDMA device tree binding
> ARM: omap: add hsmmc am33xx specific init
> mmc: omap_hsmmc: dma_request_slave_channel() support for DT platforms
> mmc: omap_hsmmc: limit max_segs with the EDMA DMAC
> mmc: omap_hsmmc: add generic DMA request support to the DT binding
> spi: omap2-mcspi: dma_request_slave_channel() support for DT
> platforms
> spi: omap2-mcspi: add generic DMA request support to the DT binding
> ARM: dts: add am33xx EDMA support
> Documentation: add schedule for removing private EDMA API
>
> Documentation/devicetree/bindings/dma/ti-edma.txt | 49 +
> .../devicetree/bindings/mmc/ti-omap-hsmmc.txt | 25 +-
> Documentation/devicetree/bindings/spi/omap-spi.txt | 27 +-
> Documentation/feature-removal-schedule.txt | 10 +
> arch/arm/Kconfig | 1 +
> arch/arm/boot/dts/am33xx.dtsi | 46 +
> arch/arm/common/Kconfig | 3 +
> arch/arm/common/Makefile | 1 +
> arch/arm/common/edma.c | 1779 ++++++++++++++++++++
> arch/arm/include/asm/mach/edma.h | 267 +++
> arch/arm/mach-davinci/Makefile | 2 +-
> arch/arm/mach-davinci/devices.c | 3 +-
> arch/arm/mach-davinci/dm355.c | 2 +-
> arch/arm/mach-davinci/dm365.c | 2 +-
> arch/arm/mach-davinci/dm644x.c | 2 +-
> arch/arm/mach-davinci/dm646x.c | 2 +-
> arch/arm/mach-davinci/dma.c | 1588 -----------------
> arch/arm/mach-davinci/include/mach/asp.h | 2 +-
> arch/arm/mach-davinci/include/mach/da8xx.h | 3 +-
> arch/arm/mach-davinci/include/mach/edma.h | 267 ---
> arch/arm/mach-davinci/include/mach/spi.h | 2 +-
> arch/arm/mach-omap2/hsmmc.c | 7 +-
> arch/arm/plat-omap/Kconfig | 1 +
> drivers/dma/Kconfig | 2 +-
> drivers/dma/edma.c | 2 +-
> drivers/mmc/host/omap_hsmmc.c | 26 +-
> drivers/spi/spi-omap2-mcspi.c | 68 +-
> 27 files changed, 2296 insertions(+), 1893 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/dma/ti-edma.txt
> create mode 100644 arch/arm/common/edma.c
> create mode 100644 arch/arm/include/asm/mach/edma.h
> delete mode 100644 arch/arm/mach-davinci/dma.c
> delete mode 100644 arch/arm/mach-davinci/include/mach/edma.h
>
> --
> 1.7.9.5
>
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
>
Regards,
Gururaja
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^ permalink raw reply [flat|nested] 52+ messages in thread
* RE: [RFC PATCH 05/13] dma: Add TI EDMA device tree binding
[not found] ` <1348152226-13588-6-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
@ 2012-09-21 8:45 ` Hebbar, Gururaja
2012-09-21 18:23 ` Matt Porter
0 siblings, 1 reply; 52+ messages in thread
From: Hebbar, Gururaja @ 2012-09-21 8:45 UTC (permalink / raw)
To: Porter, Matt, Tony Lindgren, Nori, Sekhar, Grant Likely,
Mark Brown, Cousson, Benoit, Russell King, Vinod Koul,
Rob Landley, Chris Ball
Cc: Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Williams,
Linux SPI Devel List, Linux OMAP List, Dan,
Linux ARM Kernel List
On Thu, Sep 20, 2012 at 20:13:38, Porter, Matt wrote:
> The binding definition is based on the generic DMA controller
> binding.
>
> Signed-off-by: Matt Porter <mporter-l0cyMroinI0@public.gmane.org>
> ---
> Documentation/devicetree/bindings/dma/ti-edma.txt | 49 +++++++++++++++++++++
> 1 file changed, 49 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/dma/ti-edma.txt
>
> diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt
> new file mode 100644
> index 0000000..06402eb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/ti-edma.txt
> @@ -0,0 +1,49 @@
> +TI EDMA
> +
> +Required properties:
> +- compatible : "ti,edma3"
> +- ti,hwmods: Name of the hwmods associated to the EDMA
> +- ti,edma-regions: Number of regions
> +- ti,edma-slots: Number of slots
> +- ti,edma-queue-tc-map: List of transfer control to queue mappings
> +- ti,edma-queue-priority-map: List of queue priority mappings
> +- ti,edma-default-queue: Default queue value
> +
> +Optional properties:
> +- ti,edma-reserved-channels: List of reserved channel regions
> +- ti,edma-reserved-slots: List of reserved slot regions
> +
> +Example:
> +
> +edma: edma@49000000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
address-cells & size-cells are only required when current node is a parent
node & it has sibling/child nodes (that too if the child node uses "reg"
property).
> + reg = <0x49000000 0x10000>;
> + interrupt-parent = <&intc>;
> + interrupts = <12 13 14>;
> + compatible = "ti,edma3";
> + ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
> + #dma-cells = <1>;
> + dma-channels = <64>;
> + ti,edma-regions = <4>;
> + ti,edma-slots = <256>;
> + ti,edma-reserved-channels = <0 2
> + 14 2
> + 26 6
> + 48 4
> + 56 8>;
> + ti,edma-reserved-slots = <0 2
> + 14 2
> + 26 6
> + 48 4
> + 56 8
> + 64 127>;
> + ti,edma-queue-tc-map = <0 0
> + 1 1
> + 2 2>;
> + ti,edma-queue-priority-map = <0 0
> + 1 1
> + 2 2>;
> + ti,edma-default-queue = <0>;
> +};
> +
> --
> 1.7.9.5
>
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
>
Regards,
Gururaja
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^ permalink raw reply [flat|nested] 52+ messages in thread
* RE: [RFC PATCH 03/13] ARM: edma: add DT and runtime PM support for AM335x
[not found] ` <1348152226-13588-4-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
@ 2012-09-21 8:53 ` Hebbar, Gururaja
2012-10-09 18:58 ` Matt Porter
0 siblings, 1 reply; 52+ messages in thread
From: Hebbar, Gururaja @ 2012-09-21 8:53 UTC (permalink / raw)
To: Porter, Matt, Tony Lindgren, Nori, Sekhar, Grant Likely,
Mark Brown, Cousson, Benoit, Russell King, Vinod Koul,
Rob Landley, Chris Ball
Cc: Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Williams,
Linux SPI Devel List, Linux OMAP List, Dan,
Linux ARM Kernel List
On Thu, Sep 20, 2012 at 20:13:36, Porter, Matt wrote:
> Adds support for parsing the TI EDMA DT data into the required
> EDMA private API platform data.
>
> Calls runtime PM API only in the DT case in order to unidle the
> associated hwmods on AM335x.
>
> Signed-off-by: Matt Porter <mporter-l0cyMroinI0@public.gmane.org>
> ---
> arch/arm/common/edma.c | 252 ++++++++++++++++++++++++++++++++++++--
> arch/arm/include/asm/mach/edma.h | 8 +-
> 2 files changed, 244 insertions(+), 16 deletions(-)
The binding documentation should be updated along with the driver
change that does introduce the binding. You could just merged patch #4
and #5.
>
> diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
> index 001d268..f337f81 100644
> --- a/arch/arm/common/edma.c
> +++ b/arch/arm/common/edma.c
> @@ -24,6 +24,13 @@
> #include <linux/platform_device.h>
> #include <linux/io.h>
> #include <linux/slab.h>
> +#include <linux/edma.h>
> +#include <linux/err.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/of_dma.h>
> +#include <linux/of_irq.h>
> +#include <linux/pm_runtime.h>
>
> #include <asm/mach/edma.h>
>
> @@ -1366,30 +1373,236 @@ void edma_clear_event(unsigned channel)
> EXPORT_SYMBOL(edma_clear_event);
>
> /*-----------------------------------------------------------------------*/
> +static int edma_of_read_u32_to_s8_array(const struct device_node *np,
> + const char *propname, s8 *out_values,
> + size_t sz)
> +{
> + struct property *prop = of_find_property(np, propname, NULL);
> + const __be32 *val;
> +
> + if (!prop)
> + return -EINVAL;
> + if (!prop->value)
> + return -ENODATA;
> + if ((sz * sizeof(u32)) > prop->length)
> + return -EOVERFLOW;
> +
> + val = prop->value;
> +
> + while (sz--)
> + *out_values++ = (s8)(be32_to_cpup(val++) & 0xff);
> +
> + /* Terminate it */
> + *out_values++ = -1;
> + *out_values++ = -1;
> +
> + return 0;
> +}
> +
> +static int edma_of_read_u32_to_s16_array(const struct device_node *np,
> + const char *propname, s16 *out_values,
> + size_t sz)
> +{
> + struct property *prop = of_find_property(np, propname, NULL);
> + const __be32 *val;
> +
> + if (!prop)
> + return -EINVAL;
> + if (!prop->value)
> + return -ENODATA;
> + if ((sz * sizeof(u32)) > prop->length)
> + return -EOVERFLOW;
> +
> + val = prop->value;
> +
> + while (sz--)
> + *out_values++ = (s16)(be32_to_cpup(val++) & 0xffff);
> +
> + /* Terminate it */
> + *out_values++ = -1;
> + *out_values++ = -1;
> +
> + return 0;
> +}
> +
> +static int edma_of_parse_dt(struct device *dev,
> + struct device_node *node,
> + struct edma_soc_info *pdata)
> +{
> + int ret = 0;
> + u32 value;
> + struct property *prop;
> + size_t sz;
> + struct edma_rsv_info *rsv_info;
> + s16 (*rsv_chans)[2], (*rsv_slots)[2];
> + s8 (*queue_tc_map)[2], (*queue_priority_map)[2];
> +
> + ret = of_property_read_u32(node, "dma-channels", &value);
> + if (ret < 0)
> + return ret;
> + pdata->n_channel = value;
> +
> + ret = of_property_read_u32(node, "ti,edma-regions", &value);
> + if (ret < 0)
> + return ret;
> + pdata->n_region = value;
> +
> + ret = of_property_read_u32(node, "ti,edma-slots", &value);
> + if (ret < 0)
> + return ret;
> + pdata->n_slot = value;
> +
> + pdata->n_cc = 1;
> + /* This is unused */
> + pdata->n_tc = 3;
> +
> + rsv_info =
> + devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
> + if (!rsv_info)
> + return -ENOMEM;
> + pdata->rsv = rsv_info;
> +
> + /* Build the reserved channel/slots arrays */
> + prop = of_find_property(node, "ti,edma-reserved-channels", &sz);
> + if (!prop)
> + return -EINVAL;
> +
> + rsv_chans =
> + devm_kzalloc(dev, sz/sizeof(s16) + 2*sizeof(s16), GFP_KERNEL);
> + if (!rsv_chans)
> + return -ENOMEM;
> + pdata->rsv->rsv_chans = rsv_chans;
> +
> + ret = edma_of_read_u32_to_s16_array(node, "ti,edma-reserved-channels",
> + (s16 *)rsv_chans, sz/sizeof(u32));
> + if (ret < 0)
> + return ret;
> +
> + prop = of_find_property(node, "ti,edma-reserved-slots", &sz);
> + if (!prop)
> + return -EINVAL;
> +
Binding Documentation mentions edma-reserved-[channels/slots] as optional.
But here the code returns as error if they are not found. Kindly reconfirm
>From patch-set 5/13
+Optional properties:
+- ti,edma-reserved-channels: List of reserved channel regions
+- ti,edma-reserved-slots: List of reserved slot regions
> + rsv_slots = devm_kzalloc(dev,
> + sz/sizeof(s16) + 2*sizeof(s16),
> + GFP_KERNEL);
> + if (!rsv_slots)
> + return -ENOMEM;
> + pdata->rsv->rsv_slots = rsv_slots;
> +
> + ret = edma_of_read_u32_to_s16_array(node,
> + "ti,edma-reserved-slots",
> + (s16 *)rsv_slots,
> + sz/sizeof(u32));
> + if (ret < 0)
> + return ret;
> +
> + prop = of_find_property(node, "ti,edma-queue-tc-map", &sz);
> + if (!prop)
> + return -EINVAL;
> +
> + queue_tc_map = devm_kzalloc(dev,
> + sz/sizeof(s8) + 2*sizeof(s8),
> + GFP_KERNEL);
> + if (!rsv_slots)
> + return -ENOMEM;
> + pdata->queue_tc_mapping = queue_tc_map;
> +
> + ret = edma_of_read_u32_to_s8_array(node,
> + "ti,edma-queue-tc-map",
> + (s8 *)queue_tc_map,
> + sz/sizeof(u32));
> + if (ret < 0)
> + return ret;
> +
> + prop = of_find_property(node, "ti,edma-queue-priority-map", &sz);
> + if (!prop)
> + return -EINVAL;
> +
> + queue_priority_map = devm_kzalloc(dev,
> + sz/sizeof(s8) + 2*sizeof(s8),
> + GFP_KERNEL);
> + if (!rsv_slots)
> + return -ENOMEM;
> + pdata->queue_priority_mapping = queue_priority_map;
> +
> + ret = edma_of_read_u32_to_s8_array(node,
> + "ti,edma-queue-tc-map",
> + (s8 *)queue_priority_map,
> + sz/sizeof(u32));
> + if (ret < 0)
> + return ret;
> +
> + ret = of_property_read_u32(node, "ti,edma-default-queue", &value);
> + if (ret < 0)
> + return ret;
> + pdata->default_queue = value;
> +
> + return ret;
> +}
> +
> +static struct of_dma_filter_info edma_filter_info = {
> + .filter_fn = edma_filter_fn,
> +};
>
> static int __init edma_probe(struct platform_device *pdev)
> {
> struct edma_soc_info **info = pdev->dev.platform_data;
> - const s8 (*queue_priority_mapping)[2];
> - const s8 (*queue_tc_mapping)[2];
> + s8 (*queue_priority_mapping)[2];
> + s8 (*queue_tc_mapping)[2];
> int i, j, off, ln, found = 0;
> int status = -1;
> - const s16 (*rsv_chans)[2];
> - const s16 (*rsv_slots)[2];
> + s16 (*rsv_chans)[2];
> + s16 (*rsv_slots)[2];
What is the significance of the number "2" in all above members?
> int irq[EDMA_MAX_CC] = {0, 0};
> int err_irq[EDMA_MAX_CC] = {0, 0};
> struct resource *r[EDMA_MAX_CC] = {NULL};
> + struct resource res[EDMA_MAX_CC];
> resource_size_t len[EDMA_MAX_CC];
> char res_name[10];
> char irq_name[10];
> + struct device_node *node = pdev->dev.of_node;
> + struct device *dev = &pdev->dev;
> + struct edma_soc_info *pdata;
> +
> + if (node) {
> + int ret;
> + pdata = devm_kzalloc(dev,
> + sizeof(struct edma_soc_info),
> + GFP_KERNEL);
> + edma_of_parse_dt(dev, node, pdata);
> + info = &pdata;
> + dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
> + of_dma_controller_register(dev->of_node,
> + of_dma_simple_xlate,
> + &edma_filter_info);
> + pm_runtime_enable(dev);
> + ret = pm_runtime_get_sync(dev);
> + if (IS_ERR_VALUE(ret)) {
> + dev_err(dev, "pm_runtime_get_sync() failed\n");
> + return ret;
> + }
> + }
>
> if (!info)
> return -ENODEV;
>
> for (j = 0; j < EDMA_MAX_CC; j++) {
> - sprintf(res_name, "edma_cc%d", j);
> - r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> + if (node) {
> + int err;
> + err = of_address_to_resource(node, 0, &res[j]);
> + if (err) {
> + dev_err(dev,
> + "unable to find 'reg' property\n");
> + return -EIO;
> + }
> + r[j] = &res[j];
> +
> + } else {
> + sprintf(res_name, "edma_cc%d", j);
> + r[j] = platform_get_resource_byname(pdev,
> + IORESOURCE_MEM,
> res_name);
> + }
> if (!r[j] || !info[j]) {
> if (found)
> break;
> @@ -1465,8 +1678,12 @@ static int __init edma_probe(struct platform_device *pdev)
> }
> }
>
> - sprintf(irq_name, "edma%d", j);
> - irq[j] = platform_get_irq_byname(pdev, irq_name);
> + if (node)
> + irq[j] = irq_of_parse_and_map(node, 0);
> + else {
> + sprintf(irq_name, "edma%d", j);
> + irq[j] = platform_get_irq_byname(pdev, irq_name);
> + }
> edma_cc[j]->irq_res_start = irq[j];
> status = request_irq(irq[j], dma_irq_handler, 0, "edma",
> &pdev->dev);
> @@ -1476,8 +1693,12 @@ static int __init edma_probe(struct platform_device *pdev)
> goto fail;
> }
>
> - sprintf(irq_name, "edma%d_err", j);
> - err_irq[j] = platform_get_irq_byname(pdev, irq_name);
> + if (node)
> + err_irq[j] = irq_of_parse_and_map(node, 2);
> + else {
> + sprintf(irq_name, "edma%d_err", j);
> + err_irq[j] = platform_get_irq_byname(pdev, irq_name);
> + }
> edma_cc[j]->irq_res_end = err_irq[j];
> status = request_irq(err_irq[j], dma_ccerr_handler, 0,
> "edma_error", &pdev->dev);
> @@ -1538,9 +1759,17 @@ fail1:
> return status;
> }
>
> +static const struct of_device_id edma_of_ids[] = {
> + { .compatible = "ti,edma3", },
> + {}
> +};
>
> static struct platform_driver edma_driver = {
> - .driver.name = "edma",
> + .driver = {
> + .name = "edma",
> + .of_match_table = edma_of_ids,
Won't this fail/warn when CONFIG_OF not selected/enabled?
> + },
> + .probe = edma_probe,
> };
>
> static int __init edma_init(void)
> @@ -1548,4 +1777,3 @@ static int __init edma_init(void)
> return platform_driver_probe(&edma_driver, edma_probe);
> }
> arch_initcall(edma_init);
> -
Stray change I believe.
> diff --git a/arch/arm/include/asm/mach/edma.h b/arch/arm/include/asm/mach/edma.h
> index 7e84c90..ce5f6f8 100644
> --- a/arch/arm/include/asm/mach/edma.h
> +++ b/arch/arm/include/asm/mach/edma.h
> @@ -237,8 +237,8 @@ void edma_resume(unsigned channel);
>
> struct edma_rsv_info {
>
> - const s16 (*rsv_chans)[2];
> - const s16 (*rsv_slots)[2];
> + s16 (*rsv_chans)[2];
> + s16 (*rsv_slots)[2];
> };
>
> /* platform_data for EDMA driver */
> @@ -260,8 +260,8 @@ struct edma_soc_info {
> /* Resource reservation for other cores */
> struct edma_rsv_info *rsv;
>
> - const s8 (*queue_tc_mapping)[2];
> - const s8 (*queue_priority_mapping)[2];
> + s8 (*queue_tc_mapping)[2];
> + s8 (*queue_priority_mapping)[2];
> };
>
> #endif
> --
> 1.7.9.5
>
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
>
Regards,
Gururaja
------------------------------------------------------------------------------
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 01/13] ARM: davinci: move private EDMA API to arm/common
2012-09-20 14:43 ` [RFC PATCH 01/13] ARM: davinci: move private EDMA API to arm/common Matt Porter
[not found] ` <1348152226-13588-2-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
@ 2012-09-21 9:29 ` Russell King - ARM Linux
[not found] ` <20120921092923.GA31374-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org>
2012-09-24 2:44 ` Hebbar, Gururaja
2 siblings, 1 reply; 52+ messages in thread
From: Russell King - ARM Linux @ 2012-09-21 9:29 UTC (permalink / raw)
To: Matt Porter
Cc: Tony Lindgren, Sekhar Nori, Grant Likely, Mark Brown,
Benoit Cousson, Vinod Koul, Rob Landley, Chris Ball,
Devicetree Discuss, Linux OMAP List, Linux ARM Kernel List,
Linux DaVinci Kernel List, Linux Kernel Mailing List,
Linux Documentation List, Linux MMC List, Linux SPI Devel List,
Arnd Bergmann, Dan Williams, Rob Herring
On Thu, Sep 20, 2012 at 10:43:34AM -0400, Matt Porter wrote:
> Move mach-davinci/dma.c to common/edma.c so it can be used
> by OMAP (specifically AM33xx atm) as well. This just moves
> the private EDMA API but does not support OMAP.
>
> Signed-off-by: Matt Porter <mporter@ti.com>
> ---
> arch/arm/Kconfig | 1 +
> arch/arm/common/Kconfig | 3 +
> arch/arm/common/Makefile | 1 +
> arch/arm/common/edma.c | 1588 ++++++++++++++++++++++++++++
> arch/arm/include/asm/mach/edma.h | 267 +++++
asm/mach should not be used as a dumping ground for platform header files.
It is there to provide the interfaces between generic ARM architecture
code and platform code. (At least four files that are there at the
moment need to be moved out of there - patch series to follow...)
^ permalink raw reply [flat|nested] 52+ messages in thread
* RE: [RFC PATCH 01/13] ARM: davinci: move private EDMA API to arm/common
[not found] ` <20120921092923.GA31374-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org>
@ 2012-09-21 9:33 ` Hebbar, Gururaja
2012-09-21 9:42 ` Russell King - ARM Linux
0 siblings, 1 reply; 52+ messages in thread
From: Hebbar, Gururaja @ 2012-09-21 9:33 UTC (permalink / raw)
To: Russell King - ARM Linux, Porter, Matt
Cc: Linux DaVinci Kernel List, Chris Ball, Cousson, Benoit,
Arnd Bergmann, Linux Documentation List, Tony Lindgren,
Devicetree Discuss, Mark Brown, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Grant Likely, Vinod Koul,
Rob Landley, Dan Williams, Linux SPI Devel List, Linux OMAP List
On Fri, Sep 21, 2012 at 14:59:23, Russell King - ARM Linux wrote:
> On Thu, Sep 20, 2012 at 10:43:34AM -0400, Matt Porter wrote:
> > Move mach-davinci/dma.c to common/edma.c so it can be used
> > by OMAP (specifically AM33xx atm) as well. This just moves
> > the private EDMA API but does not support OMAP.
> >
> > Signed-off-by: Matt Porter <mporter-l0cyMroinI0@public.gmane.org>
> > ---
> > arch/arm/Kconfig | 1 +
> > arch/arm/common/Kconfig | 3 +
> > arch/arm/common/Makefile | 1 +
> > arch/arm/common/edma.c | 1588 ++++++++++++++++++++++++++++
> > arch/arm/include/asm/mach/edma.h | 267 +++++
>
> asm/mach should not be used as a dumping ground for platform header files.
> It is there to provide the interfaces between generic ARM architecture
> code and platform code. (At least four files that are there at the
> moment need to be moved out of there - patch series to follow...)
Can this be moved to include/linux/platform_data/ ?
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/@public.gmane.org
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
>
Regards,
Gururaja
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 01/13] ARM: davinci: move private EDMA API to arm/common
2012-09-21 9:33 ` Hebbar, Gururaja
@ 2012-09-21 9:42 ` Russell King - ARM Linux
[not found] ` <20120921094205.GC31374-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org>
0 siblings, 1 reply; 52+ messages in thread
From: Russell King - ARM Linux @ 2012-09-21 9:42 UTC (permalink / raw)
To: Hebbar, Gururaja
Cc: Porter, Matt, Linux DaVinci Kernel List, Linux OMAP List,
Cousson, Benoit, Arnd Bergmann, Linux Documentation List,
Tony Lindgren, Linux MMC List, Devicetree Discuss, Mark Brown,
Linux Kernel Mailing List, Rob Herring, Grant Likely, Vinod Koul,
Rob Landley, Dan Williams, Linux SPI Devel List, Chris Ball,
Linux ARM Kernel List
On Fri, Sep 21, 2012 at 09:33:42AM +0000, Hebbar, Gururaja wrote:
> On Fri, Sep 21, 2012 at 14:59:23, Russell King - ARM Linux wrote:
> > On Thu, Sep 20, 2012 at 10:43:34AM -0400, Matt Porter wrote:
> > > Move mach-davinci/dma.c to common/edma.c so it can be used
> > > by OMAP (specifically AM33xx atm) as well. This just moves
> > > the private EDMA API but does not support OMAP.
> > >
> > > Signed-off-by: Matt Porter <mporter@ti.com>
> > > ---
> > > arch/arm/Kconfig | 1 +
> > > arch/arm/common/Kconfig | 3 +
> > > arch/arm/common/Makefile | 1 +
> > > arch/arm/common/edma.c | 1588 ++++++++++++++++++++++++++++
> > > arch/arm/include/asm/mach/edma.h | 267 +++++
> >
> > asm/mach should not be used as a dumping ground for platform header files.
> > It is there to provide the interfaces between generic ARM architecture
> > code and platform code. (At least four files that are there at the
> > moment need to be moved out of there - patch series to follow...)
>
> Can this be moved to include/linux/platform_data/ ?
Here's the pertinant question: "is it platform data?" Looking at the
file, it appears to be internal data structures and register definitions
for the driver itself. Therefore, it isn't platform data, and it
shouldn't be living separately from the driver.
If the driver itself only makes use of the data structures, the data
structures should be defined either within the driver, or a header file
co-located next to the driver itself. The same goes for register
definitions too.
The only structure that I can find which isn't internal to the driver
is struct edma_soc_info, struct edma_rsv_info, and the enum dma_event_q.
Those can go to include/linux/platform_data, but the rest should not.
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 10/13] spi: omap2-mcspi: dma_request_slave_channel() support for DT platforms
2012-09-21 8:16 ` Arnd Bergmann
@ 2012-09-21 15:42 ` Tony Lindgren
[not found] ` <20120921154247.GZ28835-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
0 siblings, 1 reply; 52+ messages in thread
From: Tony Lindgren @ 2012-09-21 15:42 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Matt Porter, Sekhar Nori, Grant Likely, Mark Brown,
Benoit Cousson, Russell King, Vinod Koul, Rob Landley,
Chris Ball, Devicetree Discuss, Linux OMAP List,
Linux ARM Kernel List, Linux DaVinci Kernel List,
Linux Kernel Mailing List, Linux Documentation List,
Linux MMC List, Linux SPI Devel List, Dan Williams, Rob Herring
* Arnd Bergmann <arnd@arndb.de> [120921 02:19]:
> On Thursday 20 September 2012, Tony Lindgren wrote:
> > > /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
> > > @@ -798,14 +801,26 @@ static int omap2_mcspi_request_dma(struct spi_device *spi)
> > > dma_cap_zero(mask);
> > > dma_cap_set(DMA_SLAVE, mask);
> > > sig = mcspi_dma->dma_rx_sync_dev;
> > > - mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
> > > + if (spi->dev.of_node)
> > > + mcspi_dma->dma_rx =
> > > + dma_request_slave_channel(&master->dev,
> > > + mcspi_dma->dma_rx_ch_name);
> > > + else
> > > + mcspi_dma->dma_rx =
> > > + dma_request_channel(mask, omap_dma_filter_fn, &sig);
> > > if (!mcspi_dma->dma_rx) {
> > > dev_err(&spi->dev, "no RX DMA engine channel for McSPI\n");
> > > return -EAGAIN;
> > > }
> > >
> >
> > Hmm this does not look nice.. We should be able to somehow not to care about
> > the configuration at the mcspi driver level.
>
> I agree, but as far as I understand Vinod's plans, we would actually move
> all drivers over to dma_request_slave_channel() when we have an interface
> to register the lookup tables from platform code.
>
> I think the above is ok for a transitional phase and we can remove the
> fallback path when we have converted all platforms using this driver
> to either use DT or move to the new style way of passing the channel
> configuration.
Can't we come up with a version of dma_request_slave_channel that works
both ways for now:
mcspi_dma->dma_rx =
dma_request_slave_channel_compat(mask, omap_dma_filter_fn, &sig,
&master->dev, mcspi_dma->dma_rx_ch_name);
...
Then it's just question of patching away two lines later on rather than
having to add all this if else to all the drivers first, then patching
it away again.
Regards,
Tony
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 08/13] mmc: omap_hsmmc: limit max_segs with the EDMA DMAC
2012-09-20 14:43 ` [RFC PATCH 08/13] mmc: omap_hsmmc: limit max_segs with the EDMA DMAC Matt Porter
@ 2012-09-21 17:15 ` S, Venkatraman
[not found] ` <CANfBPZ81anOy8fWgKM1PgCtB4V2pEp2x1Qi4x1uPsq7QieMN5g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2012-09-21 18:47 ` Russell King - ARM Linux
0 siblings, 2 replies; 52+ messages in thread
From: S, Venkatraman @ 2012-09-21 17:15 UTC (permalink / raw)
To: Matt Porter
Cc: Tony Lindgren, Sekhar Nori, Grant Likely, Mark Brown,
Benoit Cousson, Russell King, Vinod Koul, Rob Landley,
Chris Ball, Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Dan Williams,
Linux SPI Devel List, Linux OMAP List, Linux ARM Kernel List
On Thu, Sep 20, 2012 at 8:13 PM, Matt Porter <mporter@ti.com> wrote:
> The EDMA DMAC has a hardware limitation that prevents supporting
> scatter gather lists with any number of segments. Since the EDMA
> DMA Engine driver sets the maximum segments to 16, we do the
> same.
>
> Note: this can be removed once the DMA Engine API supports an
> API to query the DMAC's segment limitations.
>
I wouldn't want to bind the properties of EDMA to omap_hsmmc as this patch
suggests. Why don't we have a max_segs property, which when explicitly specified
in DT, will override the default ?
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 08/13] mmc: omap_hsmmc: limit max_segs with the EDMA DMAC
[not found] ` <CANfBPZ81anOy8fWgKM1PgCtB4V2pEp2x1Qi4x1uPsq7QieMN5g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2012-09-21 17:17 ` S, Venkatraman
2012-09-21 17:18 ` Felipe Balbi
2012-09-21 18:42 ` Matt Porter
0 siblings, 2 replies; 52+ messages in thread
From: S, Venkatraman @ 2012-09-21 17:17 UTC (permalink / raw)
To: Matt Porter
Cc: Linux DaVinci Kernel List, Linux OMAP List, Russell King,
Benoit Cousson, Arnd Bergmann, Linux Documentation List,
Tony Lindgren, Linux MMC List, Devicetree Discuss, Mark Brown,
Sekhar Nori, Linux Kernel Mailing List, Rob Herring, Vinod Koul,
Rob Landley, Dan Williams, Linux SPI Devel List, Chris Ball,
Linux ARM Kernel List
On Fri, Sep 21, 2012 at 10:45 PM, S, Venkatraman <svenkatr-l0cyMroinI0@public.gmane.org> wrote:
> On Thu, Sep 20, 2012 at 8:13 PM, Matt Porter <mporter-l0cyMroinI0@public.gmane.org> wrote:
>> The EDMA DMAC has a hardware limitation that prevents supporting
>> scatter gather lists with any number of segments. Since the EDMA
>> DMA Engine driver sets the maximum segments to 16, we do the
>> same.
>>
>> Note: this can be removed once the DMA Engine API supports an
>> API to query the DMAC's segment limitations.
>>
>
> I wouldn't want to bind the properties of EDMA to omap_hsmmc as this patch
> suggests. Why don't we have a max_segs property, which when explicitly specified
> in DT, will override the default ?
If you are adventurous, this can be a generic mmc DT binding instead
of restricting it to OMAP.
------------------------------------------------------------------------------
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 08/13] mmc: omap_hsmmc: limit max_segs with the EDMA DMAC
2012-09-21 17:17 ` S, Venkatraman
@ 2012-09-21 17:18 ` Felipe Balbi
[not found] ` <20120921171840.GB10409-S8G//mZuvNWo5Im9Ml3/Zg@public.gmane.org>
2012-09-21 18:54 ` Matt Porter
2012-09-21 18:42 ` Matt Porter
1 sibling, 2 replies; 52+ messages in thread
From: Felipe Balbi @ 2012-09-21 17:18 UTC (permalink / raw)
To: S, Venkatraman
Cc: Matt Porter, Tony Lindgren, Sekhar Nori, Grant Likely,
Mark Brown, Benoit Cousson, Russell King, Vinod Koul,
Rob Landley, Chris Ball, Linux DaVinci Kernel List,
Arnd Bergmann, Linux Documentation List, Devicetree Discuss,
Linux MMC List, Linux Kernel Mailing List, Rob Herring,
Dan Williams, Linux SPI Devel List, Linux OMAP List
[-- Attachment #1: Type: text/plain, Size: 1174 bytes --]
On Fri, Sep 21, 2012 at 10:47:30PM +0530, S, Venkatraman wrote:
> On Fri, Sep 21, 2012 at 10:45 PM, S, Venkatraman <svenkatr@ti.com> wrote:
> > On Thu, Sep 20, 2012 at 8:13 PM, Matt Porter <mporter@ti.com> wrote:
> >> The EDMA DMAC has a hardware limitation that prevents supporting
> >> scatter gather lists with any number of segments. Since the EDMA
> >> DMA Engine driver sets the maximum segments to 16, we do the
> >> same.
> >>
> >> Note: this can be removed once the DMA Engine API supports an
> >> API to query the DMAC's segment limitations.
> >>
> >
> > I wouldn't want to bind the properties of EDMA to omap_hsmmc as this patch
> > suggests. Why don't we have a max_segs property, which when explicitly specified
> > in DT, will override the default ?
>
> If you are adventurous, this can be a generic mmc DT binding instead
> of restricting it to OMAP.
I say if it's a limitation in the DMAC, then DMAC's driver should handle
it, no ? Meaning that in this case you would copy from one multi-segment
sg into a one-segment sg and when transfer is complete, before calling
user's callback, copy data the other way around (?)
--
balbi
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 08/13] mmc: omap_hsmmc: limit max_segs with the EDMA DMAC
[not found] ` <20120921171840.GB10409-S8G//mZuvNWo5Im9Ml3/Zg@public.gmane.org>
@ 2012-09-21 17:33 ` S, Venkatraman
0 siblings, 0 replies; 52+ messages in thread
From: S, Venkatraman @ 2012-09-21 17:33 UTC (permalink / raw)
To: balbi-l0cyMroinI0
Cc: Matt Porter, Linux DaVinci Kernel List, Linux OMAP List,
Russell King, Benoit Cousson, Arnd Bergmann,
Linux Documentation List, Tony Lindgren, Linux MMC List,
Devicetree Discuss, Mark Brown, Sekhar Nori,
Linux Kernel Mailing List, Rob Herring, Vinod Koul, Rob Landley,
Dan Williams, Linux SPI Devel List, Chris Ball,
Linux ARM Kernel List
On Fri, Sep 21, 2012 at 10:48 PM, Felipe Balbi <balbi-l0cyMroinI0@public.gmane.org> wrote:
> On Fri, Sep 21, 2012 at 10:47:30PM +0530, S, Venkatraman wrote:
>> On Fri, Sep 21, 2012 at 10:45 PM, S, Venkatraman <svenkatr-l0cyMroinI0@public.gmane.org> wrote:
>> > On Thu, Sep 20, 2012 at 8:13 PM, Matt Porter <mporter-l0cyMroinI0@public.gmane.org> wrote:
>> >> The EDMA DMAC has a hardware limitation that prevents supporting
>> >> scatter gather lists with any number of segments. Since the EDMA
>> >> DMA Engine driver sets the maximum segments to 16, we do the
>> >> same.
>> >>
>> >> Note: this can be removed once the DMA Engine API supports an
>> >> API to query the DMAC's segment limitations.
>> >>
>> >
>> > I wouldn't want to bind the properties of EDMA to omap_hsmmc as this patch
>> > suggests. Why don't we have a max_segs property, which when explicitly specified
>> > in DT, will override the default ?
>>
>> If you are adventurous, this can be a generic mmc DT binding instead
>> of restricting it to OMAP.
>
> I say if it's a limitation in the DMAC, then DMAC's driver should handle
> it, no ? Meaning that in this case you would copy from one multi-segment
> sg into a one-segment sg and when transfer is complete, before calling
> user's callback, copy data the other way around (?)
>
Right ! So even if the property is defined for MMC, Matt will end up coding the
limitation into every peripheral driver that uses EMAC, which doesn't scale.
Your solution is better.
------------------------------------------------------------------------------
Got visibility?
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 00/13] DMA Engine support for AM33xx
2012-09-21 8:27 ` [RFC PATCH 00/13] DMA Engine support for AM33xx Hebbar, Gururaja
@ 2012-09-21 18:22 ` Matt Porter
2012-09-24 11:26 ` Hebbar, Gururaja
2012-09-26 8:26 ` Hebbar, Gururaja
0 siblings, 2 replies; 52+ messages in thread
From: Matt Porter @ 2012-09-21 18:22 UTC (permalink / raw)
To: Hebbar, Gururaja
Cc: Tony Lindgren, Nori, Sekhar, Grant Likely, Mark Brown, Cousson,
Benoit, Russell King, Vinod Koul, Rob Landley, Chris Ball,
Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Dan Williams,
Linux SPI Devel List, Linux OMAP List, Linux ARM Kernel List
On Fri, Sep 21, 2012 at 08:27:07AM +0000, Hebbar, Gururaja wrote:
> On Thu, Sep 20, 2012 at 20:13:33, Porter, Matt wrote:
> > This series adds DMA Engine support for AM33xx, which uses
> > an EDMA DMAC. The EDMA DMAC has been previously supported by only
> > a private API implementation (much like the situation with OMAP
> > DMA) found on the DaVinci family of SoCs.
> >
> > There are a mind-boggling number of dependencies for this series:
> >
> > - Jon Hunter's OF DMA helpers series
> > https://patchwork.kernel.org/patch/1461061/
> > https://patchwork.kernel.org/patch/1461051/
> > - Patch to address OF DMA helpers naming issues:
> > https://patchwork.kernel.org/patch/1477921/
> > - EDMA DMA Engine wrapper driver in linux-next
> > c2dde5f8f2095d7c623ff3565c1462e190272273
> > - EDMA DMA Engine wrapper driver bug fix:
> > https://patchwork.kernel.org/patch/1474411/
> > - A huge number of patches in linux-next for AM33xx boot
> > (too numerous to list)
> >
> > The approach taken is similar to how OMAP DMA is being converted to
> > DMA Engine support. With the functional EDMA private API already
> > existing in mach-davinci/dma.c, we first move that to an ARM common
> > area so it can be shared. Adding DT and runtime PM support to the
> > private EDMA API implementation allows it to run on AM33xx. AM33xx
> > *only* boots using DT so we leverage Jon's generic DT DMA helpers to
> > register EDMA DMAC with the of_dma framework and then add support
> > for calling the dma_request_slave_channel() API to both the mmc
> > and spi drivers.
> >
> > What works? Well, with this series we now have MMC and SPI support
> > on AM33xx. The only caveat for MMC is that the mmc3 controller has
> > its events on the crossbar and is not usable right now.
> >
> > This is tested on BeagleBone with a SPI framebuffer driver and SD
> > card.
> >
> > After this series, the plan is to convert the last in-tree user
> > of the private EDMA API (davinci-pcm/mcasp) and then eliminate
> > the private EDMA API by folding its functionality into
> > drivers/dma/edma.c.
> >
> > TODO:
> > add AM33xx crossbar support to the private EDMA API
> > (any EDMA events on the crossbar are not supported)
> >
>
>
> Can you please mention the base repo you have taken as starting point.
> (repo + extra patches ...).
It's mainline 3.6-rc6 and you can see the complete set of patches
at https://github.com/ohporter/linux/tree/edma-dmaengine-am33xx-rfc-v1
after commit 5698bd757d55b1bb87edd1a9744ab09c142abfc2
> This will help us to test the code.
>
> This is because I looked at the patch 12/13 and I see that mmc
> device-node is modified. But in mainline I don’t see device
> node for mmc (yet).
Oops. You'll need e62a3333ae450bcdefbe22229d7bc277ae0ef645 and
fe97304557d2c6f7d0aaf1ea028ea48ffca366a9 which I forgot to include
in this series. I'll have them in for v2.
-Matt
> > Matt Porter (13):
> > ARM: davinci: move private EDMA API to arm/common
> > ARM: edma: remove unused transfer controller handlers
> > ARM: edma: add DT and runtime PM support for AM335x
> > dmaengine: edma: enable build for AM335x
> > dma: Add TI EDMA device tree binding
> > ARM: omap: add hsmmc am33xx specific init
> > mmc: omap_hsmmc: dma_request_slave_channel() support for DT platforms
> > mmc: omap_hsmmc: limit max_segs with the EDMA DMAC
> > mmc: omap_hsmmc: add generic DMA request support to the DT binding
> > spi: omap2-mcspi: dma_request_slave_channel() support for DT
> > platforms
> > spi: omap2-mcspi: add generic DMA request support to the DT binding
> > ARM: dts: add am33xx EDMA support
> > Documentation: add schedule for removing private EDMA API
> >
> > Documentation/devicetree/bindings/dma/ti-edma.txt | 49 +
> > .../devicetree/bindings/mmc/ti-omap-hsmmc.txt | 25 +-
> > Documentation/devicetree/bindings/spi/omap-spi.txt | 27 +-
> > Documentation/feature-removal-schedule.txt | 10 +
> > arch/arm/Kconfig | 1 +
> > arch/arm/boot/dts/am33xx.dtsi | 46 +
> > arch/arm/common/Kconfig | 3 +
> > arch/arm/common/Makefile | 1 +
> > arch/arm/common/edma.c | 1779 ++++++++++++++++++++
> > arch/arm/include/asm/mach/edma.h | 267 +++
> > arch/arm/mach-davinci/Makefile | 2 +-
> > arch/arm/mach-davinci/devices.c | 3 +-
> > arch/arm/mach-davinci/dm355.c | 2 +-
> > arch/arm/mach-davinci/dm365.c | 2 +-
> > arch/arm/mach-davinci/dm644x.c | 2 +-
> > arch/arm/mach-davinci/dm646x.c | 2 +-
> > arch/arm/mach-davinci/dma.c | 1588 -----------------
> > arch/arm/mach-davinci/include/mach/asp.h | 2 +-
> > arch/arm/mach-davinci/include/mach/da8xx.h | 3 +-
> > arch/arm/mach-davinci/include/mach/edma.h | 267 ---
> > arch/arm/mach-davinci/include/mach/spi.h | 2 +-
> > arch/arm/mach-omap2/hsmmc.c | 7 +-
> > arch/arm/plat-omap/Kconfig | 1 +
> > drivers/dma/Kconfig | 2 +-
> > drivers/dma/edma.c | 2 +-
> > drivers/mmc/host/omap_hsmmc.c | 26 +-
> > drivers/spi/spi-omap2-mcspi.c | 68 +-
> > 27 files changed, 2296 insertions(+), 1893 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/dma/ti-edma.txt
> > create mode 100644 arch/arm/common/edma.c
> > create mode 100644 arch/arm/include/asm/mach/edma.h
> > delete mode 100644 arch/arm/mach-davinci/dma.c
> > delete mode 100644 arch/arm/mach-davinci/include/mach/edma.h
> >
> > --
> > 1.7.9.5
> >
> > _______________________________________________
> > Davinci-linux-open-source mailing list
> > Davinci-linux-open-source@linux.davincidsp.com
> > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
> >
>
>
> Regards,
> Gururaja
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source@linux.davincidsp.com
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 05/13] dma: Add TI EDMA device tree binding
2012-09-21 8:45 ` Hebbar, Gururaja
@ 2012-09-21 18:23 ` Matt Porter
0 siblings, 0 replies; 52+ messages in thread
From: Matt Porter @ 2012-09-21 18:23 UTC (permalink / raw)
To: Hebbar, Gururaja
Cc: Tony Lindgren, Nori, Sekhar, Grant Likely, Mark Brown, Cousson,
Benoit, Russell King, Vinod Koul, Rob Landley, Chris Ball,
Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Dan Williams,
Linux SPI Devel List, Linux OMAP List, Linux ARM Kernel List
On Fri, Sep 21, 2012 at 08:45:53AM +0000, Hebbar, Gururaja wrote:
> On Thu, Sep 20, 2012 at 20:13:38, Porter, Matt wrote:
> > The binding definition is based on the generic DMA controller
> > binding.
> >
> > Signed-off-by: Matt Porter <mporter@ti.com>
> > ---
> > Documentation/devicetree/bindings/dma/ti-edma.txt | 49 +++++++++++++++++++++
> > 1 file changed, 49 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/dma/ti-edma.txt
> >
> > diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt
> > new file mode 100644
> > index 0000000..06402eb
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dma/ti-edma.txt
> > @@ -0,0 +1,49 @@
> > +TI EDMA
> > +
> > +Required properties:
> > +- compatible : "ti,edma3"
> > +- ti,hwmods: Name of the hwmods associated to the EDMA
> > +- ti,edma-regions: Number of regions
> > +- ti,edma-slots: Number of slots
> > +- ti,edma-queue-tc-map: List of transfer control to queue mappings
> > +- ti,edma-queue-priority-map: List of queue priority mappings
> > +- ti,edma-default-queue: Default queue value
> > +
> > +Optional properties:
> > +- ti,edma-reserved-channels: List of reserved channel regions
> > +- ti,edma-reserved-slots: List of reserved slot regions
> > +
> > +Example:
> > +
> > +edma: edma@49000000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
>
> address-cells & size-cells are only required when current node is a parent
> node & it has sibling/child nodes (that too if the child node uses "reg"
> property).
Ok. will drop that in v2.
>
>
> > + reg = <0x49000000 0x10000>;
> > + interrupt-parent = <&intc>;
> > + interrupts = <12 13 14>;
> > + compatible = "ti,edma3";
> > + ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
> > + #dma-cells = <1>;
> > + dma-channels = <64>;
> > + ti,edma-regions = <4>;
> > + ti,edma-slots = <256>;
> > + ti,edma-reserved-channels = <0 2
> > + 14 2
> > + 26 6
> > + 48 4
> > + 56 8>;
> > + ti,edma-reserved-slots = <0 2
> > + 14 2
> > + 26 6
> > + 48 4
> > + 56 8
> > + 64 127>;
> > + ti,edma-queue-tc-map = <0 0
> > + 1 1
> > + 2 2>;
> > + ti,edma-queue-priority-map = <0 0
> > + 1 1
> > + 2 2>;
> > + ti,edma-default-queue = <0>;
> > +};
> > +
> > --
> > 1.7.9.5
> >
> > _______________________________________________
> > Davinci-linux-open-source mailing list
> > Davinci-linux-open-source@linux.davincidsp.com
> > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
> >
>
>
> Regards,
> Gururaja
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source@linux.davincidsp.com
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 01/13] ARM: davinci: move private EDMA API to arm/common
2012-09-21 7:10 ` Hebbar, Gururaja
@ 2012-09-21 18:24 ` Matt Porter
0 siblings, 0 replies; 52+ messages in thread
From: Matt Porter @ 2012-09-21 18:24 UTC (permalink / raw)
To: Hebbar, Gururaja
Cc: Tony Lindgren, Nori, Sekhar, Grant Likely, Mark Brown, Cousson,
Benoit, Russell King, Vinod Koul, Rob Landley, Chris Ball,
Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Dan Williams,
Linux SPI Devel List, Linux OMAP List, Linux ARM Kernel List
On Fri, Sep 21, 2012 at 07:10:52AM +0000, Hebbar, Gururaja wrote:
> On Thu, Sep 20, 2012 at 20:13:34, Porter, Matt wrote:
> > Move mach-davinci/dma.c to common/edma.c so it can be used
> > by OMAP (specifically AM33xx atm) as well. This just moves
> > the private EDMA API but does not support OMAP.
> >
> > Signed-off-by: Matt Porter <mporter@ti.com>
> > ---
> > arch/arm/Kconfig | 1 +
> > arch/arm/common/Kconfig | 3 +
> > arch/arm/common/Makefile | 1 +
> > arch/arm/common/edma.c | 1588 ++++++++++++++++++++++++++++
> > arch/arm/include/asm/mach/edma.h | 267 +++++
> > arch/arm/mach-davinci/Makefile | 2 +-
> > arch/arm/mach-davinci/devices.c | 3 +-
> > arch/arm/mach-davinci/dm355.c | 2 +-
> > arch/arm/mach-davinci/dm365.c | 2 +-
> > arch/arm/mach-davinci/dm644x.c | 2 +-
> > arch/arm/mach-davinci/dm646x.c | 2 +-
> > arch/arm/mach-davinci/dma.c | 1588 ----------------------------
>
>
> Please use –M option, while generating patches via git-format-patch.
> This reduces the patch size if files are copied/renamed/moved.
Yes, I didn't notice until the arm kernel list caught the >100k post.
Will take care of this in v2.
-Matt
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 01/13] ARM: davinci: move private EDMA API to arm/common
[not found] ` <20120921094205.GC31374-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org>
@ 2012-09-21 18:34 ` Matt Porter
2012-09-21 18:50 ` Russell King - ARM Linux
0 siblings, 1 reply; 52+ messages in thread
From: Matt Porter @ 2012-09-21 18:34 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: Linux DaVinci Kernel List, Linux OMAP List, Cousson, Benoit,
Arnd Bergmann, Linux Documentation List, Tony Lindgren,
Devicetree Discuss, Mark Brown, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Hebbar, Gururaja,
Vinod Koul, Rob Landley, Dan Williams, Linux SPI Devel List,
Chris Ball, Linux ARM Kernel List
On Fri, Sep 21, 2012 at 10:42:05AM +0100, Russell King wrote:
> On Fri, Sep 21, 2012 at 09:33:42AM +0000, Hebbar, Gururaja wrote:
> > On Fri, Sep 21, 2012 at 14:59:23, Russell King - ARM Linux wrote:
> > > On Thu, Sep 20, 2012 at 10:43:34AM -0400, Matt Porter wrote:
> > > > Move mach-davinci/dma.c to common/edma.c so it can be used
> > > > by OMAP (specifically AM33xx atm) as well. This just moves
> > > > the private EDMA API but does not support OMAP.
> > > >
> > > > Signed-off-by: Matt Porter <mporter-l0cyMroinI0@public.gmane.org>
> > > > ---
> > > > arch/arm/Kconfig | 1 +
> > > > arch/arm/common/Kconfig | 3 +
> > > > arch/arm/common/Makefile | 1 +
> > > > arch/arm/common/edma.c | 1588 ++++++++++++++++++++++++++++
> > > > arch/arm/include/asm/mach/edma.h | 267 +++++
> > >
> > > asm/mach should not be used as a dumping ground for platform header files.
> > > It is there to provide the interfaces between generic ARM architecture
> > > code and platform code. (At least four files that are there at the
> > > moment need to be moved out of there - patch series to follow...)
> >
> > Can this be moved to include/linux/platform_data/ ?
>
> Here's the pertinant question: "is it platform data?" Looking at the
> file, it appears to be internal data structures and register definitions
> for the driver itself. Therefore, it isn't platform data, and it
> shouldn't be living separately from the driver.
>
> If the driver itself only makes use of the data structures, the data
> structures should be defined either within the driver, or a header file
> co-located next to the driver itself. The same goes for register
> definitions too.
>
> The only structure that I can find which isn't internal to the driver
> is struct edma_soc_info, struct edma_rsv_info, and the enum dma_event_q.
> Those can go to include/linux/platform_data, but the rest should not.
Ok, but is it ok to keep the actual private EDMA API portion in
arch/arm/include/asm/mach/? It's not a problem to move the internal
portions to a local include and that pdata to the appropriate place.
We still need a place independent of mach-davinci and mach-omap2 to
keep that portion of the include. I suppose it could be put in with
the dmaengine wrapper's include/linux/edma.h but I hate to clutter
that up when the private API will go away later.
-Matt
------------------------------------------------------------------------------
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 10/13] spi: omap2-mcspi: dma_request_slave_channel() support for DT platforms
[not found] ` <20120921154247.GZ28835-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
@ 2012-09-21 18:37 ` Matt Porter
2012-09-27 9:36 ` Vinod Koul
0 siblings, 1 reply; 52+ messages in thread
From: Matt Porter @ 2012-09-21 18:37 UTC (permalink / raw)
To: Tony Lindgren
Cc: Linux DaVinci Kernel List, Chris Ball, Russell King,
Linux Documentation List, Vinod Koul, Devicetree Discuss,
Mark Brown, Linux MMC List, Linux Kernel Mailing List,
Rob Herring, Dan Williams, Linux SPI Devel List, Linux OMAP List,
Linux ARM Kernel List
On Fri, Sep 21, 2012 at 08:42:47AM -0700, Tony Lindgren wrote:
> * Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> [120921 02:19]:
> > On Thursday 20 September 2012, Tony Lindgren wrote:
> > > > /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
> > > > @@ -798,14 +801,26 @@ static int omap2_mcspi_request_dma(struct spi_device *spi)
> > > > dma_cap_zero(mask);
> > > > dma_cap_set(DMA_SLAVE, mask);
> > > > sig = mcspi_dma->dma_rx_sync_dev;
> > > > - mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
> > > > + if (spi->dev.of_node)
> > > > + mcspi_dma->dma_rx =
> > > > + dma_request_slave_channel(&master->dev,
> > > > + mcspi_dma->dma_rx_ch_name);
> > > > + else
> > > > + mcspi_dma->dma_rx =
> > > > + dma_request_channel(mask, omap_dma_filter_fn, &sig);
> > > > if (!mcspi_dma->dma_rx) {
> > > > dev_err(&spi->dev, "no RX DMA engine channel for McSPI\n");
> > > > return -EAGAIN;
> > > > }
> > > >
> > >
> > > Hmm this does not look nice.. We should be able to somehow not to care about
> > > the configuration at the mcspi driver level.
> >
> > I agree, but as far as I understand Vinod's plans, we would actually move
> > all drivers over to dma_request_slave_channel() when we have an interface
> > to register the lookup tables from platform code.
> >
> > I think the above is ok for a transitional phase and we can remove the
> > fallback path when we have converted all platforms using this driver
> > to either use DT or move to the new style way of passing the channel
> > configuration.
>
> Can't we come up with a version of dma_request_slave_channel that works
> both ways for now:
>
> mcspi_dma->dma_rx =
> dma_request_slave_channel_compat(mask, omap_dma_filter_fn, &sig,
> &master->dev, mcspi_dma->dma_rx_ch_name);
> ...
>
> Then it's just question of patching away two lines later on rather than
> having to add all this if else to all the drivers first, then patching
> it away again.
I think that something like that is workable with the implementation
simply checking for of_node to do the right thing.
-Matt
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 08/13] mmc: omap_hsmmc: limit max_segs with the EDMA DMAC
2012-09-21 17:17 ` S, Venkatraman
2012-09-21 17:18 ` Felipe Balbi
@ 2012-09-21 18:42 ` Matt Porter
1 sibling, 0 replies; 52+ messages in thread
From: Matt Porter @ 2012-09-21 18:42 UTC (permalink / raw)
To: S, Venkatraman
Cc: Tony Lindgren, Sekhar Nori, Grant Likely, Mark Brown,
Benoit Cousson, Russell King, Vinod Koul, Rob Landley,
Chris Ball, Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Dan Williams,
Linux SPI Devel List, Linux OMAP List, Linux ARM Kernel List
On Fri, Sep 21, 2012 at 10:47:30PM +0530, S, Venkatraman wrote:
> On Fri, Sep 21, 2012 at 10:45 PM, S, Venkatraman <svenkatr@ti.com> wrote:
> > On Thu, Sep 20, 2012 at 8:13 PM, Matt Porter <mporter@ti.com> wrote:
> >> The EDMA DMAC has a hardware limitation that prevents supporting
> >> scatter gather lists with any number of segments. Since the EDMA
> >> DMA Engine driver sets the maximum segments to 16, we do the
> >> same.
> >>
> >> Note: this can be removed once the DMA Engine API supports an
> >> API to query the DMAC's segment limitations.
> >>
> >
> > I wouldn't want to bind the properties of EDMA to omap_hsmmc as this patch
> > suggests. Why don't we have a max_segs property, which when explicitly specified
> > in DT, will override the default ?
>
> If you are adventurous, this can be a generic mmc DT binding instead
> of restricting it to OMAP.
I think it's bad practice to add something to a binding that is not part
of the hardware definition for the device. In this case, the limitations
comes strictly from the DMAC. As I noted, the proper fix for this is to
have the DMA Engine API extended to allow querying the DMAC SG
capabilities before setting up a DMA transfer. I brought this up
previously in the thread where the actual EDMA dmaengine wrapper driver
was discussed and Vinod indicated that he was open to dmaengine
providing this information.
It makes sense as DMA Engine should tell the slave driver everything it
needs to know to set up a transfer...this is just a missing piece right
now. FWIW, we have this issue in davinci_mmc.c as well...it just was
already hardcoded with a value to satisfy the EDMA DMAC. However, I'd
like to see that go away as well.
-Matt
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 08/13] mmc: omap_hsmmc: limit max_segs with the EDMA DMAC
2012-09-21 17:15 ` S, Venkatraman
[not found] ` <CANfBPZ81anOy8fWgKM1PgCtB4V2pEp2x1Qi4x1uPsq7QieMN5g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2012-09-21 18:47 ` Russell King - ARM Linux
[not found] ` <20120921184721.GD31374-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org>
2012-09-27 9:41 ` Vinod Koul
1 sibling, 2 replies; 52+ messages in thread
From: Russell King - ARM Linux @ 2012-09-21 18:47 UTC (permalink / raw)
To: S, Venkatraman
Cc: Matt Porter, Tony Lindgren, Sekhar Nori, Grant Likely,
Mark Brown, Benoit Cousson, Vinod Koul, Rob Landley, Chris Ball,
Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Dan Williams,
Linux SPI Devel List, Linux OMAP List, Linux ARM Kernel List
On Fri, Sep 21, 2012 at 10:45:29PM +0530, S, Venkatraman wrote:
> On Thu, Sep 20, 2012 at 8:13 PM, Matt Porter <mporter@ti.com> wrote:
> > The EDMA DMAC has a hardware limitation that prevents supporting
> > scatter gather lists with any number of segments. Since the EDMA
> > DMA Engine driver sets the maximum segments to 16, we do the
> > same.
> >
> > Note: this can be removed once the DMA Engine API supports an
> > API to query the DMAC's segment limitations.
> >
>
> I wouldn't want to bind the properties of EDMA to omap_hsmmc as this patch
> suggests. Why don't we have a max_segs property, which when explicitly specified
> in DT, will override the default ?
Why not have a generic way that DMA engine can export these kinds of
properties?
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 01/13] ARM: davinci: move private EDMA API to arm/common
2012-09-21 18:34 ` Matt Porter
@ 2012-09-21 18:50 ` Russell King - ARM Linux
0 siblings, 0 replies; 52+ messages in thread
From: Russell King - ARM Linux @ 2012-09-21 18:50 UTC (permalink / raw)
To: Matt Porter
Cc: Hebbar, Gururaja, Linux DaVinci Kernel List, Chris Ball, Cousson,
Benoit, Arnd Bergmann, Linux Documentation List, Tony Lindgren,
Devicetree Discuss, Mark Brown, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Grant Likely, Vinod Koul,
Rob Landley, Dan Williams, Linux SPI Devel List, Linux OMAP List,
Linux ARM Kernel List
On Fri, Sep 21, 2012 at 02:34:46PM -0400, Matt Porter wrote:
> On Fri, Sep 21, 2012 at 10:42:05AM +0100, Russell King wrote:
> > Here's the pertinant question: "is it platform data?" Looking at the
> > file, it appears to be internal data structures and register definitions
> > for the driver itself. Therefore, it isn't platform data, and it
> > shouldn't be living separately from the driver.
> >
> > If the driver itself only makes use of the data structures, the data
> > structures should be defined either within the driver, or a header file
> > co-located next to the driver itself. The same goes for register
> > definitions too.
> >
> > The only structure that I can find which isn't internal to the driver
> > is struct edma_soc_info, struct edma_rsv_info, and the enum dma_event_q.
> > Those can go to include/linux/platform_data, but the rest should not.
>
> Ok, but is it ok to keep the actual private EDMA API portion in
> arch/arm/include/asm/mach/? It's not a problem to move the internal
> portions to a local include and that pdata to the appropriate place.
Move the platform data parts to include/linux/platform_data.
Move the driver specific parts to be either in the .c file for the
driver, or in a .h file _along_ _side_ the .c file.
Private data for drivers should be kept as close to the driver as
possible, whether that be in the same .c file as the driver itself,
or a header co-located with the .c file.
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 08/13] mmc: omap_hsmmc: limit max_segs with the EDMA DMAC
2012-09-21 17:18 ` Felipe Balbi
[not found] ` <20120921171840.GB10409-S8G//mZuvNWo5Im9Ml3/Zg@public.gmane.org>
@ 2012-09-21 18:54 ` Matt Porter
1 sibling, 0 replies; 52+ messages in thread
From: Matt Porter @ 2012-09-21 18:54 UTC (permalink / raw)
To: Felipe Balbi
Cc: S, Venkatraman, Tony Lindgren, Sekhar Nori, Grant Likely,
Mark Brown, Benoit Cousson, Russell King, Vinod Koul,
Rob Landley, Chris Ball, Linux DaVinci Kernel List,
Arnd Bergmann, Linux Documentation List, Devicetree Discuss,
Linux MMC List, Linux Kernel Mailing List, Rob Herring,
Dan Williams, Linux SPI Devel List, Linux OMAP List
On Fri, Sep 21, 2012 at 08:18:41PM +0300, Felipe Balbi wrote:
> On Fri, Sep 21, 2012 at 10:47:30PM +0530, S, Venkatraman wrote:
> > On Fri, Sep 21, 2012 at 10:45 PM, S, Venkatraman <svenkatr@ti.com> wrote:
> > > On Thu, Sep 20, 2012 at 8:13 PM, Matt Porter <mporter@ti.com> wrote:
> > >> The EDMA DMAC has a hardware limitation that prevents supporting
> > >> scatter gather lists with any number of segments. Since the EDMA
> > >> DMA Engine driver sets the maximum segments to 16, we do the
> > >> same.
> > >>
> > >> Note: this can be removed once the DMA Engine API supports an
> > >> API to query the DMAC's segment limitations.
> > >>
> > >
> > > I wouldn't want to bind the properties of EDMA to omap_hsmmc as this patch
> > > suggests. Why don't we have a max_segs property, which when explicitly specified
> > > in DT, will override the default ?
> >
> > If you are adventurous, this can be a generic mmc DT binding instead
> > of restricting it to OMAP.
>
> I say if it's a limitation in the DMAC, then DMAC's driver should handle
> it, no ? Meaning that in this case you would copy from one multi-segment
> sg into a one-segment sg and when transfer is complete, before calling
> user's callback, copy data the other way around (?)
With this DMAC, we would have to do a CPU-based copy or a series of
smaller DMA-based 16 segment copies with completion interrupts in between.
The reason the EDMA DMA Engine driver sets this limit is that we have
a hardware limitation preventing setting up a large multi-segment
transfer. The limitation is set by how many EDMA PaRaM slots are
available (varies based on how the hwmod is instantiated) but on AM335x
it's 256. You can't use all of those for just one slave device and so
the EDMA dmaengine driver arbitrarily hardcodes (atm) 16 as the max
any one channel can claim. Even if you could use all of them, it's
common for an unrestricted scatter gather transfer to exceed even our
best case hardware limitation.
This is a case where asking the DMA Engine driver to handle any length
SG is going to result in a big peformance hit, since the MMC subsystem
provides this hook for a reason, we just need the proper DMA Engine API
to find out how to set it.
So I guess I'm going to need to write up an API proposal unless Vinod
has already been thinking about this...
-Matt
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 08/13] mmc: omap_hsmmc: limit max_segs with the EDMA DMAC
[not found] ` <20120921184721.GD31374-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org>
@ 2012-09-21 19:03 ` Matt Porter
0 siblings, 0 replies; 52+ messages in thread
From: Matt Porter @ 2012-09-21 19:03 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: Linux DaVinci Kernel List, Linux OMAP List, Benoit Cousson,
Arnd Bergmann, Linux Documentation List, Tony Lindgren,
Devicetree Discuss, Mark Brown, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Vinod Koul, Chris Ball,
Rob Landley, Dan Williams, Linux SPI Devel List, S, Venkatraman,
Linux ARM Kernel List
On Fri, Sep 21, 2012 at 07:47:21PM +0100, Russell King wrote:
> On Fri, Sep 21, 2012 at 10:45:29PM +0530, S, Venkatraman wrote:
> > On Thu, Sep 20, 2012 at 8:13 PM, Matt Porter <mporter-l0cyMroinI0@public.gmane.org> wrote:
> > > The EDMA DMAC has a hardware limitation that prevents supporting
> > > scatter gather lists with any number of segments. Since the EDMA
> > > DMA Engine driver sets the maximum segments to 16, we do the
> > > same.
> > >
> > > Note: this can be removed once the DMA Engine API supports an
> > > API to query the DMAC's segment limitations.
> > >
> >
> > I wouldn't want to bind the properties of EDMA to omap_hsmmc as this patch
> > suggests. Why don't we have a max_segs property, which when explicitly specified
> > in DT, will override the default ?
>
> Why not have a generic way that DMA engine can export these kinds of
> properties?
That's exactly what my note above is suggesting...
Something along the lines of:
struct slave_sg_caps
{
int max_segs; /* <0 is no limit */
}
struct slave_sg_cap *
dmaengine_get_slave_sg_caps(struct dma_chan *chan);
I'm sure there are or will be other characteristics worth providing to
slave drivers.
-Matt
------------------------------------------------------------------------------
Got visibility?
Most devs has no idea what their production app looks like.
Find out how fast your code is with AppDynamics Lite.
http://ad.doubleclick.net/clk;262219671;13503038;y?
http://info.appdynamics.com/FreeJavaPerformanceDownload.html
^ permalink raw reply [flat|nested] 52+ messages in thread
* RE: [RFC PATCH 01/13] ARM: davinci: move private EDMA API to arm/common
2012-09-20 14:43 ` [RFC PATCH 01/13] ARM: davinci: move private EDMA API to arm/common Matt Porter
[not found] ` <1348152226-13588-2-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
2012-09-21 9:29 ` Russell King - ARM Linux
@ 2012-09-24 2:44 ` Hebbar, Gururaja
2 siblings, 0 replies; 52+ messages in thread
From: Hebbar, Gururaja @ 2012-09-24 2:44 UTC (permalink / raw)
To: Porter, Matt, Tony Lindgren, Nori, Sekhar, Grant Likely,
Mark Brown, Cousson, Benoit, Russell King, Vinod Koul,
Rob Landley, Chris Ball
Cc: Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Dan Williams,
Linux SPI Devel List, Linux OMAP List, Linux ARM Kernel List
On Thu, Sep 20, 2012 at 20:13:34, Porter, Matt wrote:
> Move mach-davinci/dma.c to common/edma.c so it can be used
> by OMAP (specifically AM33xx atm) as well. This just moves
> the private EDMA API but does not support OMAP.
>
> Signed-off-by: Matt Porter <mporter@ti.com>
> ---
> arch/arm/Kconfig | 1 +
> arch/arm/common/Kconfig | 3 +
> arch/arm/common/Makefile | 1 +
> arch/arm/common/edma.c | 1588 ++++++++++++++++++++++++++++
> arch/arm/include/asm/mach/edma.h | 267 +++++
> arch/arm/mach-davinci/Makefile | 2 +-
> arch/arm/mach-davinci/devices.c | 3 +-
> arch/arm/mach-davinci/dm355.c | 2 +-
> arch/arm/mach-davinci/dm365.c | 2 +-
> arch/arm/mach-davinci/dm644x.c | 2 +-
> arch/arm/mach-davinci/dm646x.c | 2 +-
> arch/arm/mach-davinci/dma.c | 1588 ----------------------------
> arch/arm/mach-davinci/include/mach/asp.h | 2 +-
This will clash with patch "ASoC/ARM: Davinci: McASP: split asp header
into platform and audio specific" queued in ASoC tree by Mark Brown
tree (Auio - ASoC Tree)
I forgot to mention this last time. Sorry
> arch/arm/mach-davinci/include/mach/da8xx.h | 3 +-
> arch/arm/mach-davinci/include/mach/edma.h | 267 -----
> arch/arm/mach-davinci/include/mach/spi.h | 2 +-
> arch/arm/plat-omap/Kconfig | 1 +
> 17 files changed, 1872 insertions(+), 1864 deletions(-)
> create mode 100644 arch/arm/common/edma.c
> create mode 100644 arch/arm/include/asm/mach/edma.h
> delete mode 100644 arch/arm/mach-davinci/dma.c
> delete mode 100644 arch/arm/mach-davinci/include/mach/edma.h
>
...snip...
...snip...
Regards,
Gururaja
^ permalink raw reply [flat|nested] 52+ messages in thread
* RE: [RFC PATCH 00/13] DMA Engine support for AM33xx
2012-09-21 18:22 ` Matt Porter
@ 2012-09-24 11:26 ` Hebbar, Gururaja
2012-09-24 12:05 ` Matt Porter
2012-09-26 8:26 ` Hebbar, Gururaja
1 sibling, 1 reply; 52+ messages in thread
From: Hebbar, Gururaja @ 2012-09-24 11:26 UTC (permalink / raw)
To: Porter, Matt
Cc: Tony Lindgren, Nori, Sekhar, Grant Likely, Mark Brown, Cousson,
Benoit, Russell King, Vinod Koul, Rob Landley, Chris Ball,
Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Dan Williams,
Linux SPI Devel List, Linux OMAP List, Linux ARM Kernel List
On Fri, Sep 21, 2012 at 23:52:11, Porter, Matt wrote:
> On Fri, Sep 21, 2012 at 08:27:07AM +0000, Hebbar, Gururaja wrote:
> > On Thu, Sep 20, 2012 at 20:13:33, Porter, Matt wrote:
> > > This series adds DMA Engine support for AM33xx, which uses
> > > an EDMA DMAC. The EDMA DMAC has been previously supported by only
> > > a private API implementation (much like the situation with OMAP
> > > DMA) found on the DaVinci family of SoCs.
> > >
> > > There are a mind-boggling number of dependencies for this series:
> > >
> > > - Jon Hunter's OF DMA helpers series
> > > https://patchwork.kernel.org/patch/1461061/
> > > https://patchwork.kernel.org/patch/1461051/
> > > - Patch to address OF DMA helpers naming issues:
> > > https://patchwork.kernel.org/patch/1477921/
> > > - EDMA DMA Engine wrapper driver in linux-next
> > > c2dde5f8f2095d7c623ff3565c1462e190272273
> > > - EDMA DMA Engine wrapper driver bug fix:
> > > https://patchwork.kernel.org/patch/1474411/
> > > - A huge number of patches in linux-next for AM33xx boot
> > > (too numerous to list)
> > >
> > > The approach taken is similar to how OMAP DMA is being converted to
> > > DMA Engine support. With the functional EDMA private API already
> > > existing in mach-davinci/dma.c, we first move that to an ARM common
> > > area so it can be shared. Adding DT and runtime PM support to the
> > > private EDMA API implementation allows it to run on AM33xx. AM33xx
> > > *only* boots using DT so we leverage Jon's generic DT DMA helpers to
> > > register EDMA DMAC with the of_dma framework and then add support
> > > for calling the dma_request_slave_channel() API to both the mmc
> > > and spi drivers.
> > >
> > > What works? Well, with this series we now have MMC and SPI support
> > > on AM33xx. The only caveat for MMC is that the mmc3 controller has
> > > its events on the crossbar and is not usable right now.
> > >
> > > This is tested on BeagleBone with a SPI framebuffer driver and SD
> > > card.
> > >
> > > After this series, the plan is to convert the last in-tree user
> > > of the private EDMA API (davinci-pcm/mcasp) and then eliminate
> > > the private EDMA API by folding its functionality into
> > > drivers/dma/edma.c.
> > >
> > > TODO:
> > > add AM33xx crossbar support to the private EDMA API
> > > (any EDMA events on the crossbar are not supported)
> > >
> >
> >
> > Can you please mention the base repo you have taken as starting point.
> > (repo + extra patches ...).
>
> It's mainline 3.6-rc6 and you can see the complete set of patches
> at https://github.com/ohporter/linux/tree/edma-dmaengine-am33xx-rfc-v1
> after commit 5698bd757d55b1bb87edd1a9744ab09c142abfc2
Thanks for the link. However, I was looking for the mainline kernel repo/branch
That you first used as baseline.
>
> > This will help us to test the code.
> >
> > This is because I looked at the patch 12/13 and I see that mmc
> > device-node is modified. But in mainline I don’t see device
> > node for mmc (yet).
>
> Oops. You'll need e62a3333ae450bcdefbe22229d7bc277ae0ef645 and
> fe97304557d2c6f7d0aaf1ea028ea48ffca366a9 which I forgot to include
> in this series. I'll have them in for v2.
>
> -Matt
>
> > > Matt Porter (13):
> > > ARM: davinci: move private EDMA API to arm/common
> > > ARM: edma: remove unused transfer controller handlers
> > > ARM: edma: add DT and runtime PM support for AM335x
> > > dmaengine: edma: enable build for AM335x
> > > dma: Add TI EDMA device tree binding
> > > ARM: omap: add hsmmc am33xx specific init
> > > mmc: omap_hsmmc: dma_request_slave_channel() support for DT platforms
> > > mmc: omap_hsmmc: limit max_segs with the EDMA DMAC
> > > mmc: omap_hsmmc: add generic DMA request support to the DT binding
> > > spi: omap2-mcspi: dma_request_slave_channel() support for DT
> > > platforms
> > > spi: omap2-mcspi: add generic DMA request support to the DT binding
> > > ARM: dts: add am33xx EDMA support
> > > Documentation: add schedule for removing private EDMA API
> > >
> > > Documentation/devicetree/bindings/dma/ti-edma.txt | 49 +
> > > .../devicetree/bindings/mmc/ti-omap-hsmmc.txt | 25 +-
> > > Documentation/devicetree/bindings/spi/omap-spi.txt | 27 +-
> > > Documentation/feature-removal-schedule.txt | 10 +
> > > arch/arm/Kconfig | 1 +
> > > arch/arm/boot/dts/am33xx.dtsi | 46 +
> > > arch/arm/common/Kconfig | 3 +
> > > arch/arm/common/Makefile | 1 +
> > > arch/arm/common/edma.c | 1779 ++++++++++++++++++++
> > > arch/arm/include/asm/mach/edma.h | 267 +++
> > > arch/arm/mach-davinci/Makefile | 2 +-
> > > arch/arm/mach-davinci/devices.c | 3 +-
> > > arch/arm/mach-davinci/dm355.c | 2 +-
> > > arch/arm/mach-davinci/dm365.c | 2 +-
> > > arch/arm/mach-davinci/dm644x.c | 2 +-
> > > arch/arm/mach-davinci/dm646x.c | 2 +-
> > > arch/arm/mach-davinci/dma.c | 1588 -----------------
> > > arch/arm/mach-davinci/include/mach/asp.h | 2 +-
> > > arch/arm/mach-davinci/include/mach/da8xx.h | 3 +-
> > > arch/arm/mach-davinci/include/mach/edma.h | 267 ---
> > > arch/arm/mach-davinci/include/mach/spi.h | 2 +-
> > > arch/arm/mach-omap2/hsmmc.c | 7 +-
> > > arch/arm/plat-omap/Kconfig | 1 +
> > > drivers/dma/Kconfig | 2 +-
> > > drivers/dma/edma.c | 2 +-
> > > drivers/mmc/host/omap_hsmmc.c | 26 +-
> > > drivers/spi/spi-omap2-mcspi.c | 68 +-
> > > 27 files changed, 2296 insertions(+), 1893 deletions(-)
> > > create mode 100644 Documentation/devicetree/bindings/dma/ti-edma.txt
> > > create mode 100644 arch/arm/common/edma.c
> > > create mode 100644 arch/arm/include/asm/mach/edma.h
> > > delete mode 100644 arch/arm/mach-davinci/dma.c
> > > delete mode 100644 arch/arm/mach-davinci/include/mach/edma.h
> > >
> > > --
> > > 1.7.9.5
> > >
> > > _______________________________________________
> > > Davinci-linux-open-source mailing list
> > > Davinci-linux-open-source@linux.davincidsp.com
> > > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
> > >
> >
> >
> > Regards,
> > Gururaja
> > _______________________________________________
> > Davinci-linux-open-source mailing list
> > Davinci-linux-open-source@linux.davincidsp.com
> > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
>
Regards,
Gururaja
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 00/13] DMA Engine support for AM33xx
2012-09-24 11:26 ` Hebbar, Gururaja
@ 2012-09-24 12:05 ` Matt Porter
0 siblings, 0 replies; 52+ messages in thread
From: Matt Porter @ 2012-09-24 12:05 UTC (permalink / raw)
To: Hebbar, Gururaja
Cc: Linux DaVinci Kernel List, Linux OMAP List, Russell King,
Cousson, Benoit, Arnd Bergmann, Linux Documentation List,
Tony Lindgren, Linux MMC List, Devicetree Discuss, Mark Brown,
Linux Kernel Mailing List, Rob Herring, Grant Likely, Vinod Koul,
Rob Landley, Dan Williams, Linux SPI Devel List, Chris Ball,
Linux ARM Kernel List
On Mon, Sep 24, 2012 at 11:26:55AM +0000, Hebbar, Gururaja wrote:
> On Fri, Sep 21, 2012 at 23:52:11, Porter, Matt wrote:
> > On Fri, Sep 21, 2012 at 08:27:07AM +0000, Hebbar, Gururaja wrote:
> > > On Thu, Sep 20, 2012 at 20:13:33, Porter, Matt wrote:
> > > > This series adds DMA Engine support for AM33xx, which uses
> > > > an EDMA DMAC. The EDMA DMAC has been previously supported by only
> > > > a private API implementation (much like the situation with OMAP
> > > > DMA) found on the DaVinci family of SoCs.
> > > >
> > > > There are a mind-boggling number of dependencies for this series:
> > > >
> > > > - Jon Hunter's OF DMA helpers series
> > > > https://patchwork.kernel.org/patch/1461061/
> > > > https://patchwork.kernel.org/patch/1461051/
> > > > - Patch to address OF DMA helpers naming issues:
> > > > https://patchwork.kernel.org/patch/1477921/
> > > > - EDMA DMA Engine wrapper driver in linux-next
> > > > c2dde5f8f2095d7c623ff3565c1462e190272273
> > > > - EDMA DMA Engine wrapper driver bug fix:
> > > > https://patchwork.kernel.org/patch/1474411/
> > > > - A huge number of patches in linux-next for AM33xx boot
> > > > (too numerous to list)
> > > >
> > > > The approach taken is similar to how OMAP DMA is being converted to
> > > > DMA Engine support. With the functional EDMA private API already
> > > > existing in mach-davinci/dma.c, we first move that to an ARM common
> > > > area so it can be shared. Adding DT and runtime PM support to the
> > > > private EDMA API implementation allows it to run on AM33xx. AM33xx
> > > > *only* boots using DT so we leverage Jon's generic DT DMA helpers to
> > > > register EDMA DMAC with the of_dma framework and then add support
> > > > for calling the dma_request_slave_channel() API to both the mmc
> > > > and spi drivers.
> > > >
> > > > What works? Well, with this series we now have MMC and SPI support
> > > > on AM33xx. The only caveat for MMC is that the mmc3 controller has
> > > > its events on the crossbar and is not usable right now.
> > > >
> > > > This is tested on BeagleBone with a SPI framebuffer driver and SD
> > > > card.
> > > >
> > > > After this series, the plan is to convert the last in-tree user
> > > > of the private EDMA API (davinci-pcm/mcasp) and then eliminate
> > > > the private EDMA API by folding its functionality into
> > > > drivers/dma/edma.c.
> > > >
> > > > TODO:
> > > > add AM33xx crossbar support to the private EDMA API
> > > > (any EDMA events on the crossbar are not supported)
> > > >
> > >
> > >
> > > Can you please mention the base repo you have taken as starting point.
> > > (repo + extra patches ...).
> >
> > It's mainline 3.6-rc6 and you can see the complete set of patches
> > at https://github.com/ohporter/linux/tree/edma-dmaengine-am33xx-rfc-v1
> > after commit 5698bd757d55b1bb87edd1a9744ab09c142abfc2
>
> Thanks for the link. However, I was looking for the mainline kernel repo/branch
> That you first used as baseline.
Linus 3.6-rc6 is the baseline. This inital version was created before any
of the am33xx base support patches got pulled to linux-next. v2 is being
rebased against that to slim down the stack of patches necessary for
testing.
> > > This will help us to test the code.
> > >
> > > This is because I looked at the patch 12/13 and I see that mmc
> > > device-node is modified. But in mainline I don’t see device
> > > node for mmc (yet).
> >
> > Oops. You'll need e62a3333ae450bcdefbe22229d7bc277ae0ef645 and
> > fe97304557d2c6f7d0aaf1ea028ea48ffca366a9 which I forgot to include
> > in this series. I'll have them in for v2.
> >
> > -Matt
> >
> > > > Matt Porter (13):
> > > > ARM: davinci: move private EDMA API to arm/common
> > > > ARM: edma: remove unused transfer controller handlers
> > > > ARM: edma: add DT and runtime PM support for AM335x
> > > > dmaengine: edma: enable build for AM335x
> > > > dma: Add TI EDMA device tree binding
> > > > ARM: omap: add hsmmc am33xx specific init
> > > > mmc: omap_hsmmc: dma_request_slave_channel() support for DT platforms
> > > > mmc: omap_hsmmc: limit max_segs with the EDMA DMAC
> > > > mmc: omap_hsmmc: add generic DMA request support to the DT binding
> > > > spi: omap2-mcspi: dma_request_slave_channel() support for DT
> > > > platforms
> > > > spi: omap2-mcspi: add generic DMA request support to the DT binding
> > > > ARM: dts: add am33xx EDMA support
> > > > Documentation: add schedule for removing private EDMA API
> > > >
> > > > Documentation/devicetree/bindings/dma/ti-edma.txt | 49 +
> > > > .../devicetree/bindings/mmc/ti-omap-hsmmc.txt | 25 +-
> > > > Documentation/devicetree/bindings/spi/omap-spi.txt | 27 +-
> > > > Documentation/feature-removal-schedule.txt | 10 +
> > > > arch/arm/Kconfig | 1 +
> > > > arch/arm/boot/dts/am33xx.dtsi | 46 +
> > > > arch/arm/common/Kconfig | 3 +
> > > > arch/arm/common/Makefile | 1 +
> > > > arch/arm/common/edma.c | 1779 ++++++++++++++++++++
> > > > arch/arm/include/asm/mach/edma.h | 267 +++
> > > > arch/arm/mach-davinci/Makefile | 2 +-
> > > > arch/arm/mach-davinci/devices.c | 3 +-
> > > > arch/arm/mach-davinci/dm355.c | 2 +-
> > > > arch/arm/mach-davinci/dm365.c | 2 +-
> > > > arch/arm/mach-davinci/dm644x.c | 2 +-
> > > > arch/arm/mach-davinci/dm646x.c | 2 +-
> > > > arch/arm/mach-davinci/dma.c | 1588 -----------------
> > > > arch/arm/mach-davinci/include/mach/asp.h | 2 +-
> > > > arch/arm/mach-davinci/include/mach/da8xx.h | 3 +-
> > > > arch/arm/mach-davinci/include/mach/edma.h | 267 ---
> > > > arch/arm/mach-davinci/include/mach/spi.h | 2 +-
> > > > arch/arm/mach-omap2/hsmmc.c | 7 +-
> > > > arch/arm/plat-omap/Kconfig | 1 +
> > > > drivers/dma/Kconfig | 2 +-
> > > > drivers/dma/edma.c | 2 +-
> > > > drivers/mmc/host/omap_hsmmc.c | 26 +-
> > > > drivers/spi/spi-omap2-mcspi.c | 68 +-
> > > > 27 files changed, 2296 insertions(+), 1893 deletions(-)
> > > > create mode 100644 Documentation/devicetree/bindings/dma/ti-edma.txt
> > > > create mode 100644 arch/arm/common/edma.c
> > > > create mode 100644 arch/arm/include/asm/mach/edma.h
> > > > delete mode 100644 arch/arm/mach-davinci/dma.c
> > > > delete mode 100644 arch/arm/mach-davinci/include/mach/edma.h
> > > >
> > > > --
> > > > 1.7.9.5
> > > >
> > > > _______________________________________________
> > > > Davinci-linux-open-source mailing list
> > > > Davinci-linux-open-source@linux.davincidsp.com
> > > > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
> > > >
> > >
> > >
> > > Regards,
> > > Gururaja
> > > _______________________________________________
> > > Davinci-linux-open-source mailing list
> > > Davinci-linux-open-source@linux.davincidsp.com
> > > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
> >
>
>
> Regards,
> Gururaja
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source@linux.davincidsp.com
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
^ permalink raw reply [flat|nested] 52+ messages in thread
* RE: [RFC PATCH 00/13] DMA Engine support for AM33xx
2012-09-21 18:22 ` Matt Porter
2012-09-24 11:26 ` Hebbar, Gururaja
@ 2012-09-26 8:26 ` Hebbar, Gururaja
2012-09-26 13:01 ` Matt Porter
1 sibling, 1 reply; 52+ messages in thread
From: Hebbar, Gururaja @ 2012-09-26 8:26 UTC (permalink / raw)
To: Porter, Matt
Cc: Linux DaVinci Kernel List, Linux OMAP List, Russell King,
Cousson, Benoit, Arnd Bergmann, Linux Documentation List,
Tony Lindgren, Linux MMC List, Devicetree Discuss, Mark Brown,
Nori, Sekhar, Linux Kernel Mailing List, Rob Herring,
Grant Likely, Vinod Koul, Rob Landley, Dan Williams,
Linux SPI Devel List, Chris Ball, Linux ARM Kernel List
On Fri, Sep 21, 2012 at 23:52:11, Porter, Matt wrote:
> On Fri, Sep 21, 2012 at 08:27:07AM +0000, Hebbar, Gururaja wrote:
> > On Thu, Sep 20, 2012 at 20:13:33, Porter, Matt wrote:
> > > This series adds DMA Engine support for AM33xx, which uses
> > > an EDMA DMAC. The EDMA DMAC has been previously supported by only
> > > a private API implementation (much like the situation with OMAP
> > > DMA) found on the DaVinci family of SoCs.
> > >
> > > There are a mind-boggling number of dependencies for this series:
> > >
> > > - Jon Hunter's OF DMA helpers series
> > > https://patchwork.kernel.org/patch/1461061/
> > > https://patchwork.kernel.org/patch/1461051/
> > > - Patch to address OF DMA helpers naming issues:
> > > https://patchwork.kernel.org/patch/1477921/
> > > - EDMA DMA Engine wrapper driver in linux-next
> > > c2dde5f8f2095d7c623ff3565c1462e190272273
> > > - EDMA DMA Engine wrapper driver bug fix:
> > > https://patchwork.kernel.org/patch/1474411/
> > > - A huge number of patches in linux-next for AM33xx boot
> > > (too numerous to list)
> > >
> > > The approach taken is similar to how OMAP DMA is being converted to
> > > DMA Engine support. With the functional EDMA private API already
> > > existing in mach-davinci/dma.c, we first move that to an ARM common
> > > area so it can be shared. Adding DT and runtime PM support to the
> > > private EDMA API implementation allows it to run on AM33xx. AM33xx
> > > *only* boots using DT so we leverage Jon's generic DT DMA helpers to
> > > register EDMA DMAC with the of_dma framework and then add support
> > > for calling the dma_request_slave_channel() API to both the mmc
> > > and spi drivers.
> > >
> > > What works? Well, with this series we now have MMC and SPI support
> > > on AM33xx. The only caveat for MMC is that the mmc3 controller has
> > > its events on the crossbar and is not usable right now.
> > >
> > > This is tested on BeagleBone with a SPI framebuffer driver and SD
> > > card.
> > >
> > > After this series, the plan is to convert the last in-tree user
> > > of the private EDMA API (davinci-pcm/mcasp) and then eliminate
> > > the private EDMA API by folding its functionality into
> > > drivers/dma/edma.c.
> > >
> > > TODO:
> > > add AM33xx crossbar support to the private EDMA API
> > > (any EDMA events on the crossbar are not supported)
> > >
> >
> >
> > Can you please mention the base repo you have taken as starting point.
> > (repo + extra patches ...).
>
> It's mainline 3.6-rc6 and you can see the complete set of patches
> at https://github.com/ohporter/linux/tree/edma-dmaengine-am33xx-rfc-v1
> after commit 5698bd757d55b1bb87edd1a9744ab09c142abfc2
>
> > This will help us to test the code.
> >
> > This is because I looked at the patch 12/13 and I see that mmc
> > device-node is modified. But in mainline I don’t see device
> > node for mmc (yet).
>
> Oops. You'll need e62a3333ae450bcdefbe22229d7bc277ae0ef645 and
> fe97304557d2c6f7d0aaf1ea028ea48ffca366a9 which I forgot to include
> in this series. I'll have them in for v2.
Yesterday I tested edma patches on latest linux-next/master + merge of
linux-omap/for_3.7/dts_part2. Below are my observations
1. baseline = linux-next/master + merge of linux-omap/for_3.7/dts_part2
2. on top of above branch, I applied patches [1-9]/13 of your edma
patches
3. few patches required trivial changes before applying
4. Applied dma of patches as you mentioned
5. add custom patch (ARM: CUSTOM: Build a uImage with dtb already
appended)
From https://github.com/hvaibhav/am335x-linux/commit/
7e72f5ed4b702c9373d19f7626f07ae31a381d53#arch/arm/Makefile
6. Modified 9/13 patch to apply properly on latest am33xx.dtsi.
a. Edma portion as it is
b. mmc portion as below
mmc1: mmc@48060000 {
compatible = "ti,omap3-hsmmc";
ti,hwmods = "mmc1";
ti,dual-volt;
ti,needs-special-reset;
bus-width = <4>;
vmmc-supply = <&vmmc_reg>;
dmas = <&edma 24
&edma 25>;
dma-names = "tx", "rx";
};
c. added mmc pinmux as-well
7. make CROSS_COMPILE=arm-arago-linux-gnueabi- ARCH=arm distclean
make CROSS_COMPILE=arm-arago-linux-gnueabi- ARCH=arm
omap2plus_defconfig
8. enabled TI_EDMA from menuconfig (since it was not enabled for
omap2plus_defconfig
9. make CROSS_COMPILE=arm-arago-linux-gnueabi- ARCH=arm uImage
make CROSS_COMPILE=arm-arago-linux-gnueabi- ARCH=arm
uImage-dtb.am335x-evm
With above changes, edma probe was failing at request_mem_region()
Inside linux-next/arch/arm/common/edma.c --> edma_probe()
I had to modify edma_probe as below
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index f337f81..efe2673 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -1589,11 +1589,11 @@ static int __init edma_probe(struct platform_device *pdev)
for (j = 0; j < EDMA_MAX_CC; j++) {
if (node) {
int err;
- err = of_address_to_resource(node, 0, &res[j]);
+ err = of_address_to_resource(node, j, &res[j]);
if (err) {
dev_err(dev,
"unable to find 'reg' property\n");
- return -EIO;
+ //return -EIO;
}
r[j] = &res[j];
With this I was able to boot on am335x-evm and do a successful MMC
copy-md5sum-compare test.
I believe you are looking into above issue in your v2 version.
>
> -Matt
>
...snip...
...snip...
...snip...
Regards,
Gururaja
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 00/13] DMA Engine support for AM33xx
2012-09-26 8:26 ` Hebbar, Gururaja
@ 2012-09-26 13:01 ` Matt Porter
0 siblings, 0 replies; 52+ messages in thread
From: Matt Porter @ 2012-09-26 13:01 UTC (permalink / raw)
To: Hebbar, Gururaja
Cc: Linux DaVinci Kernel List, Linux OMAP List, Russell King,
Cousson, Benoit, Arnd Bergmann, Linux Documentation List,
Tony Lindgren, Linux MMC List, Devicetree Discuss, Mark Brown,
Linux Kernel Mailing List, Rob Herring, Grant Likely, Vinod Koul,
Rob Landley, Dan Williams, Linux SPI Devel List, Chris Ball,
Linux ARM Kernel List
On Wed, Sep 26, 2012 at 08:26:19AM +0000, Hebbar, Gururaja wrote:
> On Fri, Sep 21, 2012 at 23:52:11, Porter, Matt wrote:
> > On Fri, Sep 21, 2012 at 08:27:07AM +0000, Hebbar, Gururaja wrote:
> > > On Thu, Sep 20, 2012 at 20:13:33, Porter, Matt wrote:
> > > > This series adds DMA Engine support for AM33xx, which uses
> > > > an EDMA DMAC. The EDMA DMAC has been previously supported by only
> > > > a private API implementation (much like the situation with OMAP
> > > > DMA) found on the DaVinci family of SoCs.
> > > >
> > > > There are a mind-boggling number of dependencies for this series:
> > > >
> > > > - Jon Hunter's OF DMA helpers series
> > > > https://patchwork.kernel.org/patch/1461061/
> > > > https://patchwork.kernel.org/patch/1461051/
> > > > - Patch to address OF DMA helpers naming issues:
> > > > https://patchwork.kernel.org/patch/1477921/
> > > > - EDMA DMA Engine wrapper driver in linux-next
> > > > c2dde5f8f2095d7c623ff3565c1462e190272273
> > > > - EDMA DMA Engine wrapper driver bug fix:
> > > > https://patchwork.kernel.org/patch/1474411/
> > > > - A huge number of patches in linux-next for AM33xx boot
> > > > (too numerous to list)
> > > >
> > > > The approach taken is similar to how OMAP DMA is being converted to
> > > > DMA Engine support. With the functional EDMA private API already
> > > > existing in mach-davinci/dma.c, we first move that to an ARM common
> > > > area so it can be shared. Adding DT and runtime PM support to the
> > > > private EDMA API implementation allows it to run on AM33xx. AM33xx
> > > > *only* boots using DT so we leverage Jon's generic DT DMA helpers to
> > > > register EDMA DMAC with the of_dma framework and then add support
> > > > for calling the dma_request_slave_channel() API to both the mmc
> > > > and spi drivers.
> > > >
> > > > What works? Well, with this series we now have MMC and SPI support
> > > > on AM33xx. The only caveat for MMC is that the mmc3 controller has
> > > > its events on the crossbar and is not usable right now.
> > > >
> > > > This is tested on BeagleBone with a SPI framebuffer driver and SD
> > > > card.
> > > >
> > > > After this series, the plan is to convert the last in-tree user
> > > > of the private EDMA API (davinci-pcm/mcasp) and then eliminate
> > > > the private EDMA API by folding its functionality into
> > > > drivers/dma/edma.c.
> > > >
> > > > TODO:
> > > > add AM33xx crossbar support to the private EDMA API
> > > > (any EDMA events on the crossbar are not supported)
> > > >
> > >
> > >
> > > Can you please mention the base repo you have taken as starting point.
> > > (repo + extra patches ...).
> >
> > It's mainline 3.6-rc6 and you can see the complete set of patches
> > at https://github.com/ohporter/linux/tree/edma-dmaengine-am33xx-rfc-v1
> > after commit 5698bd757d55b1bb87edd1a9744ab09c142abfc2
> >
> > > This will help us to test the code.
> > >
> > > This is because I looked at the patch 12/13 and I see that mmc
> > > device-node is modified. But in mainline I don’t see device
> > > node for mmc (yet).
> >
> > Oops. You'll need e62a3333ae450bcdefbe22229d7bc277ae0ef645 and
> > fe97304557d2c6f7d0aaf1ea028ea48ffca366a9 which I forgot to include
> > in this series. I'll have them in for v2.
>
> Yesterday I tested edma patches on latest linux-next/master + merge of
> linux-omap/for_3.7/dts_part2. Below are my observations
>
> 1. baseline = linux-next/master + merge of linux-omap/for_3.7/dts_part2
> 2. on top of above branch, I applied patches [1-9]/13 of your edma
> patches
> 3. few patches required trivial changes before applying
> 4. Applied dma of patches as you mentioned
> 5. add custom patch (ARM: CUSTOM: Build a uImage with dtb already
> appended)
> From https://github.com/hvaibhav/am335x-linux/commit/
> 7e72f5ed4b702c9373d19f7626f07ae31a381d53#arch/arm/Makefile
Alternatively you can run a current u-boot master build for am335x and
the appended dtb is no longer required.
> 6. Modified 9/13 patch to apply properly on latest am33xx.dtsi.
> a. Edma portion as it is
> b. mmc portion as below
> mmc1: mmc@48060000 {
> compatible = "ti,omap3-hsmmc";
> ti,hwmods = "mmc1";
> ti,dual-volt;
> ti,needs-special-reset;
> bus-width = <4>;
> vmmc-supply = <&vmmc_reg>;
> dmas = <&edma 24
> &edma 25>;
> dma-names = "tx", "rx";
> };
> c. added mmc pinmux as-well
>
> 7. make CROSS_COMPILE=arm-arago-linux-gnueabi- ARCH=arm distclean
> make CROSS_COMPILE=arm-arago-linux-gnueabi- ARCH=arm
> omap2plus_defconfig
>
> 8. enabled TI_EDMA from menuconfig (since it was not enabled for
> omap2plus_defconfig
>
> 9. make CROSS_COMPILE=arm-arago-linux-gnueabi- ARCH=arm uImage
> make CROSS_COMPILE=arm-arago-linux-gnueabi- ARCH=arm
> uImage-dtb.am335x-evm
>
> With above changes, edma probe was failing at request_mem_region()
> Inside linux-next/arch/arm/common/edma.c --> edma_probe()
>
> I had to modify edma_probe as below
>
>
> diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
> index f337f81..efe2673 100644
> --- a/arch/arm/common/edma.c
> +++ b/arch/arm/common/edma.c
> @@ -1589,11 +1589,11 @@ static int __init edma_probe(struct platform_device *pdev)
> for (j = 0; j < EDMA_MAX_CC; j++) {
> if (node) {
> int err;
> - err = of_address_to_resource(node, 0, &res[j]);
> + err = of_address_to_resource(node, j, &res[j]);
> if (err) {
> dev_err(dev,
> "unable to find 'reg' property\n");
> - return -EIO;
> + //return -EIO;
> }
> r[j] = &res[j];
Hrm, looks like a dts issue if it can't find the reg resource on your
integration of this. In any case, I'll look at it in v2.
> With this I was able to boot on am335x-evm and do a successful MMC
> copy-md5sum-compare test.
Great! Thanks for testing this.
> I believe you are looking into above issue in your v2 version.
Yes.
-Matt
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 10/13] spi: omap2-mcspi: dma_request_slave_channel() support for DT platforms
2012-09-21 18:37 ` Matt Porter
@ 2012-09-27 9:36 ` Vinod Koul
2012-10-01 16:37 ` Matt Porter
0 siblings, 1 reply; 52+ messages in thread
From: Vinod Koul @ 2012-09-27 9:36 UTC (permalink / raw)
To: Matt Porter
Cc: Tony Lindgren, Arnd Bergmann, Linux DaVinci Kernel List,
Linux OMAP List, Russell King, Benoit Cousson,
Linux Documentation List, Linux MMC List, Devicetree Discuss,
Mark Brown, Linux Kernel Mailing List, Rob Herring, Grant Likely,
Rob Landley, Dan Williams, Linux SPI Devel List, Chris Ball,
Linux ARM Kernel List
On Fri, 2012-09-21 at 14:37 -0400, Matt Porter wrote:
> On Fri, Sep 21, 2012 at 08:42:47AM -0700, Tony Lindgren wrote:
> >
> > Can't we come up with a version of dma_request_slave_channel that works
> > both ways for now:
> >
> > mcspi_dma->dma_rx =
> > dma_request_slave_channel_compat(mask, omap_dma_filter_fn, &sig,
> > &master->dev, mcspi_dma->dma_rx_ch_name);
> > ...
> >
> > Then it's just question of patching away two lines later on rather than
> > having to add all this if else to all the drivers first, then patching
> > it away again.
>
> I think that something like that is workable with the implementation
> simply checking for of_node to do the right thing.
Yes, I think it would be better to have common API but underneath two
implementations in transitional phase.
--
~Vinod
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 08/13] mmc: omap_hsmmc: limit max_segs with the EDMA DMAC
2012-09-21 18:47 ` Russell King - ARM Linux
[not found] ` <20120921184721.GD31374-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org>
@ 2012-09-27 9:41 ` Vinod Koul
2012-10-01 16:39 ` Matt Porter
1 sibling, 1 reply; 52+ messages in thread
From: Vinod Koul @ 2012-09-27 9:41 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: S, Venkatraman, Matt Porter, Linux DaVinci Kernel List,
Linux OMAP List, Benoit Cousson, Arnd Bergmann,
Linux Documentation List, Tony Lindgren, Linux MMC List,
Devicetree Discuss, Mark Brown, Sekhar Nori,
Linux Kernel Mailing List, Rob Herring, Grant Likely,
Rob Landley, Dan Williams, Linux SPI Devel List, Chris Ball,
Linux ARM Kernel List
On Fri, 2012-09-21 at 19:47 +0100, Russell King - ARM Linux wrote:
> On Fri, Sep 21, 2012 at 10:45:29PM +0530, S, Venkatraman wrote:
> > On Thu, Sep 20, 2012 at 8:13 PM, Matt Porter <mporter@ti.com> wrote:
> > > The EDMA DMAC has a hardware limitation that prevents supporting
> > > scatter gather lists with any number of segments. Since the EDMA
> > > DMA Engine driver sets the maximum segments to 16, we do the
> > > same.
> > >
> > > Note: this can be removed once the DMA Engine API supports an
> > > API to query the DMAC's segment limitations.
> > >
> >
> > I wouldn't want to bind the properties of EDMA to omap_hsmmc as this patch
> > suggests. Why don't we have a max_segs property, which when explicitly specified
> > in DT, will override the default ?
>
> Why not have a generic way that DMA engine can export these kinds of
> properties?
We discussed this at KS. I was of opinion that DMA engine should export
controller and channel capabilities as part of the channel it returns.
Some folks had an opinion that they already know how to use controller
so may not be very helpful, but if it is going to help (which I think),
i have a patch for this :)
--
~Vinod
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 10/13] spi: omap2-mcspi: dma_request_slave_channel() support for DT platforms
2012-09-27 9:36 ` Vinod Koul
@ 2012-10-01 16:37 ` Matt Porter
0 siblings, 0 replies; 52+ messages in thread
From: Matt Porter @ 2012-10-01 16:37 UTC (permalink / raw)
To: Vinod Koul
Cc: Linux DaVinci Kernel List, Chris Ball, Russell King,
Benoit Cousson, Arnd Bergmann, Linux Documentation List,
Tony Lindgren, Devicetree Discuss, Mark Brown, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Grant Likely,
Rob Landley, Dan Williams, Linux SPI Devel List, Linux OMAP List,
Linux ARM Kernel List
On Thu, Sep 27, 2012 at 03:06:34PM +0530, Vinod Koul wrote:
> On Fri, 2012-09-21 at 14:37 -0400, Matt Porter wrote:
> > On Fri, Sep 21, 2012 at 08:42:47AM -0700, Tony Lindgren wrote:
> > >
> > > Can't we come up with a version of dma_request_slave_channel that works
> > > both ways for now:
> > >
> > > mcspi_dma->dma_rx =
> > > dma_request_slave_channel_compat(mask, omap_dma_filter_fn, &sig,
> > > &master->dev, mcspi_dma->dma_rx_ch_name);
> > > ...
> > >
> > > Then it's just question of patching away two lines later on rather than
> > > having to add all this if else to all the drivers first, then patching
> > > it away again.
> >
> > I think that something like that is workable with the implementation
> > simply checking for of_node to do the right thing.
> Yes, I think it would be better to have common API but underneath two
> implementations in transitional phase.
Ok, I'll implement something for discussion in the v2 series.
-Matt
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 08/13] mmc: omap_hsmmc: limit max_segs with the EDMA DMAC
2012-09-27 9:41 ` Vinod Koul
@ 2012-10-01 16:39 ` Matt Porter
2012-10-02 12:03 ` Vinod Koul
0 siblings, 1 reply; 52+ messages in thread
From: Matt Porter @ 2012-10-01 16:39 UTC (permalink / raw)
To: Vinod Koul
Cc: Russell King - ARM Linux, S, Venkatraman,
Linux DaVinci Kernel List, Linux OMAP List, Benoit Cousson,
Arnd Bergmann, Linux Documentation List, Tony Lindgren,
Linux MMC List, Devicetree Discuss, Mark Brown, Sekhar Nori,
Linux Kernel Mailing List, Rob Herring, Grant Likely,
Rob Landley, Dan Williams, Linux SPI Devel List, Chris Ball,
Linux ARM Kernel List
On Thu, Sep 27, 2012 at 03:11:08PM +0530, Vinod Koul wrote:
> On Fri, 2012-09-21 at 19:47 +0100, Russell King - ARM Linux wrote:
> > On Fri, Sep 21, 2012 at 10:45:29PM +0530, S, Venkatraman wrote:
> > > On Thu, Sep 20, 2012 at 8:13 PM, Matt Porter <mporter@ti.com> wrote:
> > > > The EDMA DMAC has a hardware limitation that prevents supporting
> > > > scatter gather lists with any number of segments. Since the EDMA
> > > > DMA Engine driver sets the maximum segments to 16, we do the
> > > > same.
> > > >
> > > > Note: this can be removed once the DMA Engine API supports an
> > > > API to query the DMAC's segment limitations.
> > > >
> > >
> > > I wouldn't want to bind the properties of EDMA to omap_hsmmc as this patch
> > > suggests. Why don't we have a max_segs property, which when explicitly specified
> > > in DT, will override the default ?
> >
> > Why not have a generic way that DMA engine can export these kinds of
> > properties?
> We discussed this at KS. I was of opinion that DMA engine should export
> controller and channel capabilities as part of the channel it returns.
>
> Some folks had an opinion that they already know how to use controller
> so may not be very helpful, but if it is going to help (which I think),
> i have a patch for this :)
Anything you can show at this point? ;) I'd be happy to drop the half-hack
for a real API. If not, I'm going to carry that to v2 atm.
-Matt
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 08/13] mmc: omap_hsmmc: limit max_segs with the EDMA DMAC
2012-10-01 16:39 ` Matt Porter
@ 2012-10-02 12:03 ` Vinod Koul
0 siblings, 0 replies; 52+ messages in thread
From: Vinod Koul @ 2012-10-02 12:03 UTC (permalink / raw)
To: Matt Porter
Cc: Linux DaVinci Kernel List, Chris Ball, Russell King - ARM Linux,
Linux Documentation List, Linux MMC List, Devicetree Discuss,
Mark Brown, Sekhar Nori, Linux Kernel Mailing List, Rob Herring,
Dan Williams, Linux SPI Devel List, Linux OMAP List,
Linux ARM Kernel List
On Mon, 2012-10-01 at 12:39 -0400, Matt Porter wrote:
> Anything you can show at this point? ;) I'd be happy to drop the
> half-hack
> for a real API. If not, I'm going to carry that to v2 atm.
This is what I had done sometime back. Feel free to update....
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 9c02a45..94ae006 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -86,11 +86,11 @@ enum dma_transaction_type {
* @DMA_DEV_TO_DEV: Slave mode & From Device to Device
*/
enum dma_transfer_direction {
- DMA_MEM_TO_MEM,
- DMA_MEM_TO_DEV,
- DMA_DEV_TO_MEM,
- DMA_DEV_TO_DEV,
- DMA_TRANS_NONE,
+ DMA_MEM_TO_MEM = 0x01,
+ DMA_MEM_TO_DEV = 0x02,
+ DMA_DEV_TO_MEM = 0x04,
+ DMA_DEV_TO_DEV = 0x08,
+ DMA_TRANS_NONE = 0x10,
};
/**
@@ -371,6 +371,41 @@ struct dma_slave_config {
unsigned int slave_id;
};
+enum dmaengine_apis {
+ DMAENGINE_MEMCPY = 0x0001,
+ DMAENGINE_XOR = 0x0002,
+ DMAENGINE_XOR_VAL = 0x0004,
+ DMAENGINE_PQ = 0x0008,
+ DMAENGINE_PQ_VAL = 0x0010,
+ DMAENGINE_MEMSET = 0x0020,
+ DMAENGINE_SLAVE = 0x0040,
+ DMAENGINE_CYCLIC = 0x0080,
+ DMAENGINE_INTERLEAVED = 0x0100,
+ DMAENGINE_SG = 0x0200,
+};
+
+/* struct dmaengine_chan_caps - expose capability of a channel
+ * Note: each channel can have same or different capabilities
+ *
+ * This primarily classifies capabilities into
+ * a) APIs/ops supported
+ * b) channel physical capabilities
+ *
+ * @ops: or'ed api capability
+ * @widths: channel widths supported
+ * @dirn: channel directions supported
+ * @bursts: bitmask of burst lengths supported
+ * @mux: configurable slave id or hard wired
+ * -1 for hard wired, otherwise valid positive slave id (including zero)
+ */
+struct dmaengine_chan_caps {
+ enum dmaengine_apis ops;
+ enum dma_slave_buswidth widths;
+ enum dma_transfer_direction dirn;
+ unsigned int dma_bursts;
+ int mux;
+};
+
static inline const char *dma_chan_name(struct dma_chan *chan)
{
return dev_name(&chan->dev->device);
@@ -534,6 +569,7 @@ struct dma_tx_state {
* struct with auxiliary transfer status information, otherwise the call
* will just return a simple status code
* @device_issue_pending: push pending transactions to hardware
+ * @device_channel_caps: return the capablities of channel
*/
struct dma_device {
@@ -602,6 +638,9 @@ struct dma_device {
dma_cookie_t cookie,
struct dma_tx_state *txstate);
void (*device_issue_pending)(struct dma_chan *chan);
+
+ struct dmaengine_chan_caps *(*device_channel_caps)(
+ struct dma_chan *chan);
};
static inline int dmaengine_device_control(struct dma_chan *chan,
--
~Vinod
^ permalink raw reply related [flat|nested] 52+ messages in thread
* Re: [RFC PATCH 03/13] ARM: edma: add DT and runtime PM support for AM335x
2012-09-21 8:53 ` Hebbar, Gururaja
@ 2012-10-09 18:58 ` Matt Porter
0 siblings, 0 replies; 52+ messages in thread
From: Matt Porter @ 2012-10-09 18:58 UTC (permalink / raw)
To: Hebbar, Gururaja
Cc: Tony Lindgren, Nori, Sekhar, Grant Likely, Mark Brown, Cousson,
Benoit, Russell King, Vinod Koul, Rob Landley, Chris Ball,
Linux DaVinci Kernel List, Arnd Bergmann,
Linux Documentation List, Devicetree Discuss, Linux MMC List,
Linux Kernel Mailing List, Rob Herring, Dan Williams,
Linux SPI Devel List, Linux OMAP List, Linux ARM Kernel List
On Fri, Sep 21, 2012 at 08:53:06AM +0000, Hebbar, Gururaja wrote:
> On Thu, Sep 20, 2012 at 20:13:36, Porter, Matt wrote:
> > Adds support for parsing the TI EDMA DT data into the required
> > EDMA private API platform data.
> >
> > Calls runtime PM API only in the DT case in order to unidle the
> > associated hwmods on AM335x.
> >
> > Signed-off-by: Matt Porter <mporter@ti.com>
> > ---
> > arch/arm/common/edma.c | 252 ++++++++++++++++++++++++++++++++++++--
> > arch/arm/include/asm/mach/edma.h | 8 +-
> > 2 files changed, 244 insertions(+), 16 deletions(-)
>
> The binding documentation should be updated along with the driver
> change that does introduce the binding. You could just merged patch #4
> and #5.
Hi Gururaja,
Sorry I missed these comments for this long...
I've been asked by maintainers to keep the binding separate in other
drivers. It is documentation that is independent of the driver in
any case...I'll move the binding before this implementation though.
> > diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
> > index 001d268..f337f81 100644
> > --- a/arch/arm/common/edma.c
> > +++ b/arch/arm/common/edma.c
> > @@ -24,6 +24,13 @@
> > #include <linux/platform_device.h>
> > #include <linux/io.h>
> > #include <linux/slab.h>
> > +#include <linux/edma.h>
> > +#include <linux/err.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_dma.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/pm_runtime.h>
> >
> > #include <asm/mach/edma.h>
> >
> > @@ -1366,30 +1373,236 @@ void edma_clear_event(unsigned channel)
> > EXPORT_SYMBOL(edma_clear_event);
> >
> > /*-----------------------------------------------------------------------*/
> > +static int edma_of_read_u32_to_s8_array(const struct device_node *np,
> > + const char *propname, s8 *out_values,
> > + size_t sz)
> > +{
> > + struct property *prop = of_find_property(np, propname, NULL);
> > + const __be32 *val;
> > +
> > + if (!prop)
> > + return -EINVAL;
> > + if (!prop->value)
> > + return -ENODATA;
> > + if ((sz * sizeof(u32)) > prop->length)
> > + return -EOVERFLOW;
> > +
> > + val = prop->value;
> > +
> > + while (sz--)
> > + *out_values++ = (s8)(be32_to_cpup(val++) & 0xff);
> > +
> > + /* Terminate it */
> > + *out_values++ = -1;
> > + *out_values++ = -1;
> > +
> > + return 0;
> > +}
> > +
> > +static int edma_of_read_u32_to_s16_array(const struct device_node *np,
> > + const char *propname, s16 *out_values,
> > + size_t sz)
> > +{
> > + struct property *prop = of_find_property(np, propname, NULL);
> > + const __be32 *val;
> > +
> > + if (!prop)
> > + return -EINVAL;
> > + if (!prop->value)
> > + return -ENODATA;
> > + if ((sz * sizeof(u32)) > prop->length)
> > + return -EOVERFLOW;
> > +
> > + val = prop->value;
> > +
> > + while (sz--)
> > + *out_values++ = (s16)(be32_to_cpup(val++) & 0xffff);
> > +
> > + /* Terminate it */
> > + *out_values++ = -1;
> > + *out_values++ = -1;
> > +
> > + return 0;
> > +}
> > +
> > +static int edma_of_parse_dt(struct device *dev,
> > + struct device_node *node,
> > + struct edma_soc_info *pdata)
> > +{
> > + int ret = 0;
> > + u32 value;
> > + struct property *prop;
> > + size_t sz;
> > + struct edma_rsv_info *rsv_info;
> > + s16 (*rsv_chans)[2], (*rsv_slots)[2];
> > + s8 (*queue_tc_map)[2], (*queue_priority_map)[2];
> > +
> > + ret = of_property_read_u32(node, "dma-channels", &value);
> > + if (ret < 0)
> > + return ret;
> > + pdata->n_channel = value;
> > +
> > + ret = of_property_read_u32(node, "ti,edma-regions", &value);
> > + if (ret < 0)
> > + return ret;
> > + pdata->n_region = value;
> > +
> > + ret = of_property_read_u32(node, "ti,edma-slots", &value);
> > + if (ret < 0)
> > + return ret;
> > + pdata->n_slot = value;
> > +
> > + pdata->n_cc = 1;
> > + /* This is unused */
> > + pdata->n_tc = 3;
> > +
> > + rsv_info =
> > + devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
> > + if (!rsv_info)
> > + return -ENOMEM;
> > + pdata->rsv = rsv_info;
> > +
> > + /* Build the reserved channel/slots arrays */
> > + prop = of_find_property(node, "ti,edma-reserved-channels", &sz);
> > + if (!prop)
> > + return -EINVAL;
> > +
> > + rsv_chans =
> > + devm_kzalloc(dev, sz/sizeof(s16) + 2*sizeof(s16), GFP_KERNEL);
> > + if (!rsv_chans)
> > + return -ENOMEM;
> > + pdata->rsv->rsv_chans = rsv_chans;
> > +
> > + ret = edma_of_read_u32_to_s16_array(node, "ti,edma-reserved-channels",
> > + (s16 *)rsv_chans, sz/sizeof(u32));
> > + if (ret < 0)
> > + return ret;
> > +
> > + prop = of_find_property(node, "ti,edma-reserved-slots", &sz);
> > + if (!prop)
> > + return -EINVAL;
> > +
>
> Binding Documentation mentions edma-reserved-[channels/slots] as optional.
> But here the code returns as error if they are not found. Kindly reconfirm
>
> >From patch-set 5/13
>
> +Optional properties:
> +- ti,edma-reserved-channels: List of reserved channel regions
> +- ti,edma-reserved-slots: List of reserved slot regions
Good catch, the binding documentation is correct and I will fix my
implementation to match.
> > + rsv_slots = devm_kzalloc(dev,
> > + sz/sizeof(s16) + 2*sizeof(s16),
> > + GFP_KERNEL);
> > + if (!rsv_slots)
> > + return -ENOMEM;
> > + pdata->rsv->rsv_slots = rsv_slots;
> > +
> > + ret = edma_of_read_u32_to_s16_array(node,
> > + "ti,edma-reserved-slots",
> > + (s16 *)rsv_slots,
> > + sz/sizeof(u32));
> > + if (ret < 0)
> > + return ret;
> > +
> > + prop = of_find_property(node, "ti,edma-queue-tc-map", &sz);
> > + if (!prop)
> > + return -EINVAL;
> > +
> > + queue_tc_map = devm_kzalloc(dev,
> > + sz/sizeof(s8) + 2*sizeof(s8),
> > + GFP_KERNEL);
> > + if (!rsv_slots)
> > + return -ENOMEM;
> > + pdata->queue_tc_mapping = queue_tc_map;
> > +
> > + ret = edma_of_read_u32_to_s8_array(node,
> > + "ti,edma-queue-tc-map",
> > + (s8 *)queue_tc_map,
> > + sz/sizeof(u32));
> > + if (ret < 0)
> > + return ret;
> > +
> > + prop = of_find_property(node, "ti,edma-queue-priority-map", &sz);
> > + if (!prop)
> > + return -EINVAL;
> > +
> > + queue_priority_map = devm_kzalloc(dev,
> > + sz/sizeof(s8) + 2*sizeof(s8),
> > + GFP_KERNEL);
> > + if (!rsv_slots)
> > + return -ENOMEM;
> > + pdata->queue_priority_mapping = queue_priority_map;
> > +
> > + ret = edma_of_read_u32_to_s8_array(node,
> > + "ti,edma-queue-tc-map",
> > + (s8 *)queue_priority_map,
> > + sz/sizeof(u32));
> > + if (ret < 0)
> > + return ret;
> > +
> > + ret = of_property_read_u32(node, "ti,edma-default-queue", &value);
> > + if (ret < 0)
> > + return ret;
> > + pdata->default_queue = value;
> > +
> > + return ret;
> > +}
> > +
> > +static struct of_dma_filter_info edma_filter_info = {
> > + .filter_fn = edma_filter_fn,
> > +};
> >
> > static int __init edma_probe(struct platform_device *pdev)
> > {
> > struct edma_soc_info **info = pdev->dev.platform_data;
> > - const s8 (*queue_priority_mapping)[2];
> > - const s8 (*queue_tc_mapping)[2];
> > + s8 (*queue_priority_mapping)[2];
> > + s8 (*queue_tc_mapping)[2];
> > int i, j, off, ln, found = 0;
> > int status = -1;
> > - const s16 (*rsv_chans)[2];
> > - const s16 (*rsv_slots)[2];
> > + s16 (*rsv_chans)[2];
> > + s16 (*rsv_slots)[2];
>
> What is the significance of the number "2" in all above members?
Those should all be EDMA_MAX_CC, as that is the significance. I
will address that. Incidentally, this is expected to be short-lived
after Davinci ASoC is fully converted to dmaengine. One of the
big problems in the private EDMA API driver from an implementation
POV is that the driver attempt to encompass all channel controller
instances in a single device match. This results in this legacy
pdata structure that we adopt for compatibility. As part of folding
this into drivers/dma/edma.c, we'll have a device instance per
channel controller that will nicely clean this up. Not to mention
all the unused code we'll remove.
> > int irq[EDMA_MAX_CC] = {0, 0};
> > int err_irq[EDMA_MAX_CC] = {0, 0};
> > struct resource *r[EDMA_MAX_CC] = {NULL};
> > + struct resource res[EDMA_MAX_CC];
> > resource_size_t len[EDMA_MAX_CC];
> > char res_name[10];
> > char irq_name[10];
> > + struct device_node *node = pdev->dev.of_node;
> > + struct device *dev = &pdev->dev;
> > + struct edma_soc_info *pdata;
> > +
> > + if (node) {
> > + int ret;
> > + pdata = devm_kzalloc(dev,
> > + sizeof(struct edma_soc_info),
> > + GFP_KERNEL);
> > + edma_of_parse_dt(dev, node, pdata);
> > + info = &pdata;
> > + dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
> > + of_dma_controller_register(dev->of_node,
> > + of_dma_simple_xlate,
> > + &edma_filter_info);
> > + pm_runtime_enable(dev);
> > + ret = pm_runtime_get_sync(dev);
> > + if (IS_ERR_VALUE(ret)) {
> > + dev_err(dev, "pm_runtime_get_sync() failed\n");
> > + return ret;
> > + }
> > + }
> >
> > if (!info)
> > return -ENODEV;
> >
> > for (j = 0; j < EDMA_MAX_CC; j++) {
> > - sprintf(res_name, "edma_cc%d", j);
> > - r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > + if (node) {
> > + int err;
> > + err = of_address_to_resource(node, 0, &res[j]);
> > + if (err) {
> > + dev_err(dev,
> > + "unable to find 'reg' property\n");
> > + return -EIO;
> > + }
> > + r[j] = &res[j];
> > +
> > + } else {
> > + sprintf(res_name, "edma_cc%d", j);
> > + r[j] = platform_get_resource_byname(pdev,
> > + IORESOURCE_MEM,
> > res_name);
> > + }
> > if (!r[j] || !info[j]) {
> > if (found)
> > break;
> > @@ -1465,8 +1678,12 @@ static int __init edma_probe(struct platform_device *pdev)
> > }
> > }
> >
> > - sprintf(irq_name, "edma%d", j);
> > - irq[j] = platform_get_irq_byname(pdev, irq_name);
> > + if (node)
> > + irq[j] = irq_of_parse_and_map(node, 0);
> > + else {
> > + sprintf(irq_name, "edma%d", j);
> > + irq[j] = platform_get_irq_byname(pdev, irq_name);
> > + }
> > edma_cc[j]->irq_res_start = irq[j];
> > status = request_irq(irq[j], dma_irq_handler, 0, "edma",
> > &pdev->dev);
> > @@ -1476,8 +1693,12 @@ static int __init edma_probe(struct platform_device *pdev)
> > goto fail;
> > }
> >
> > - sprintf(irq_name, "edma%d_err", j);
> > - err_irq[j] = platform_get_irq_byname(pdev, irq_name);
> > + if (node)
> > + err_irq[j] = irq_of_parse_and_map(node, 2);
> > + else {
> > + sprintf(irq_name, "edma%d_err", j);
> > + err_irq[j] = platform_get_irq_byname(pdev, irq_name);
> > + }
> > edma_cc[j]->irq_res_end = err_irq[j];
> > status = request_irq(err_irq[j], dma_ccerr_handler, 0,
> > "edma_error", &pdev->dev);
> > @@ -1538,9 +1759,17 @@ fail1:
> > return status;
> > }
> >
> > +static const struct of_device_id edma_of_ids[] = {
> > + { .compatible = "ti,edma3", },
> > + {}
> > +};
> >
> > static struct platform_driver edma_driver = {
> > - .driver.name = "edma",
> > + .driver = {
> > + .name = "edma",
> > + .of_match_table = edma_of_ids,
>
> Won't this fail/warn when CONFIG_OF not selected/enabled?
No. of_match_table is no longer dependent on CONFIG_OF
> > + },
> > + .probe = edma_probe,
> > };
> >
> > static int __init edma_init(void)
> > @@ -1548,4 +1777,3 @@ static int __init edma_init(void)
> > return platform_driver_probe(&edma_driver, edma_probe);
> > }
> > arch_initcall(edma_init);
> > -
>
> Stray change I believe.
checkpatch found that bad whitespace.
> > diff --git a/arch/arm/include/asm/mach/edma.h b/arch/arm/include/asm/mach/edma.h
> > index 7e84c90..ce5f6f8 100644
> > --- a/arch/arm/include/asm/mach/edma.h
> > +++ b/arch/arm/include/asm/mach/edma.h
> > @@ -237,8 +237,8 @@ void edma_resume(unsigned channel);
> >
> > struct edma_rsv_info {
> >
> > - const s16 (*rsv_chans)[2];
> > - const s16 (*rsv_slots)[2];
> > + s16 (*rsv_chans)[2];
> > + s16 (*rsv_slots)[2];
> > };
> >
> > /* platform_data for EDMA driver */
> > @@ -260,8 +260,8 @@ struct edma_soc_info {
> > /* Resource reservation for other cores */
> > struct edma_rsv_info *rsv;
> >
> > - const s8 (*queue_tc_mapping)[2];
> > - const s8 (*queue_priority_mapping)[2];
> > + s8 (*queue_tc_mapping)[2];
> > + s8 (*queue_priority_mapping)[2];
> > };
> >
> > #endif
> > --
> > 1.7.9.5
> >
> > _______________________________________________
> > Davinci-linux-open-source mailing list
> > Davinci-linux-open-source@linux.davincidsp.com
> > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
> >
>
>
> Regards,
> Gururaja
> _______________________________________________
> Davinci-linux-open-source mailing list
> Davinci-linux-open-source@linux.davincidsp.com
> http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
^ permalink raw reply [flat|nested] 52+ messages in thread
end of thread, other threads:[~2012-10-09 18:58 UTC | newest]
Thread overview: 52+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-09-20 14:43 [RFC PATCH 00/13] DMA Engine support for AM33xx Matt Porter
[not found] ` <1348152226-13588-1-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
2012-09-20 14:43 ` [RFC PATCH 01/13] ARM: davinci: move private EDMA API to arm/common Matt Porter
[not found] ` <1348152226-13588-2-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
2012-09-21 7:10 ` Hebbar, Gururaja
2012-09-21 18:24 ` Matt Porter
2012-09-21 9:29 ` Russell King - ARM Linux
[not found] ` <20120921092923.GA31374-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org>
2012-09-21 9:33 ` Hebbar, Gururaja
2012-09-21 9:42 ` Russell King - ARM Linux
[not found] ` <20120921094205.GC31374-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org>
2012-09-21 18:34 ` Matt Porter
2012-09-21 18:50 ` Russell King - ARM Linux
2012-09-24 2:44 ` Hebbar, Gururaja
2012-09-20 14:43 ` [RFC PATCH 02/13] ARM: edma: remove unused transfer controller handlers Matt Porter
2012-09-20 14:43 ` [RFC PATCH 03/13] ARM: edma: add DT and runtime PM support for AM335x Matt Porter
[not found] ` <1348152226-13588-4-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
2012-09-21 8:53 ` Hebbar, Gururaja
2012-10-09 18:58 ` Matt Porter
2012-09-20 14:43 ` [RFC PATCH 04/13] dmaengine: edma: enable build " Matt Porter
2012-09-20 14:43 ` [RFC PATCH 05/13] dma: Add TI EDMA device tree binding Matt Porter
[not found] ` <1348152226-13588-6-git-send-email-mporter-l0cyMroinI0@public.gmane.org>
2012-09-21 8:45 ` Hebbar, Gururaja
2012-09-21 18:23 ` Matt Porter
2012-09-20 14:43 ` [RFC PATCH 06/13] ARM: omap: add hsmmc am33xx specific init Matt Porter
2012-09-20 14:43 ` [RFC PATCH 07/13] mmc: omap_hsmmc: dma_request_slave_channel() support for DT platforms Matt Porter
2012-09-20 22:16 ` Tony Lindgren
2012-09-20 14:43 ` [RFC PATCH 08/13] mmc: omap_hsmmc: limit max_segs with the EDMA DMAC Matt Porter
2012-09-21 17:15 ` S, Venkatraman
[not found] ` <CANfBPZ81anOy8fWgKM1PgCtB4V2pEp2x1Qi4x1uPsq7QieMN5g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2012-09-21 17:17 ` S, Venkatraman
2012-09-21 17:18 ` Felipe Balbi
[not found] ` <20120921171840.GB10409-S8G//mZuvNWo5Im9Ml3/Zg@public.gmane.org>
2012-09-21 17:33 ` S, Venkatraman
2012-09-21 18:54 ` Matt Porter
2012-09-21 18:42 ` Matt Porter
2012-09-21 18:47 ` Russell King - ARM Linux
[not found] ` <20120921184721.GD31374-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org>
2012-09-21 19:03 ` Matt Porter
2012-09-27 9:41 ` Vinod Koul
2012-10-01 16:39 ` Matt Porter
2012-10-02 12:03 ` Vinod Koul
2012-09-20 14:43 ` [RFC PATCH 09/13] mmc: omap_hsmmc: add generic DMA request support to the DT binding Matt Porter
2012-09-20 14:43 ` [RFC PATCH 10/13] spi: omap2-mcspi: dma_request_slave_channel() support for DT platforms Matt Porter
2012-09-20 22:09 ` Tony Lindgren
2012-09-21 8:16 ` Arnd Bergmann
2012-09-21 15:42 ` Tony Lindgren
[not found] ` <20120921154247.GZ28835-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
2012-09-21 18:37 ` Matt Porter
2012-09-27 9:36 ` Vinod Koul
2012-10-01 16:37 ` Matt Porter
2012-09-20 14:43 ` [RFC PATCH 11/13] spi: omap2-mcspi: add generic DMA request support to the DT binding Matt Porter
2012-09-20 14:43 ` [RFC PATCH 12/13] ARM: dts: add am33xx EDMA support Matt Porter
2012-09-20 14:43 ` [RFC PATCH 13/13] Documentation: add schedule for removing private EDMA API Matt Porter
2012-09-20 15:58 ` Mark Brown
2012-09-20 16:05 ` Matt Porter
2012-09-21 8:27 ` [RFC PATCH 00/13] DMA Engine support for AM33xx Hebbar, Gururaja
2012-09-21 18:22 ` Matt Porter
2012-09-24 11:26 ` Hebbar, Gururaja
2012-09-24 12:05 ` Matt Porter
2012-09-26 8:26 ` Hebbar, Gururaja
2012-09-26 13:01 ` Matt Porter
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