From: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
To: "Mylène Josserand"
<mylene.josserand-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Cc: wens-jdAy2FN1RRM@public.gmane.org,
linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org
Subject: Re: [PATCH 3/4] arm: dts: sun8i: a83t: Add CCI-400 node
Date: Wed, 13 Dec 2017 11:52:08 +0100 [thread overview]
Message-ID: <20171213105208.4rrxffplh7mfxviv@flea.lan> (raw)
In-Reply-To: <20171211075001.6100-4-mylene.josserand-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
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Hi,
On Mon, Dec 11, 2017 at 08:50:00AM +0100, Mylène Josserand wrote:
> Add CCI-400 node and control-port on CPUs needed by MCPM (ie SMP).
>
> Signed-off-by: Mylène Josserand <mylene.josserand-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> ---
> arch/arm/boot/dts/sun8i-a83t.dtsi | 41 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 41 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
> index eeb2e7d0d6dc..3e2aad537972 100644
> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
> @@ -62,48 +62,56 @@
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> reg = <0>;
> + cci-control-port = <&cci_control0>;
> };
>
> cpu@1 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> reg = <1>;
> + cci-control-port = <&cci_control0>;
> };
>
> cpu@2 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> reg = <2>;
> + cci-control-port = <&cci_control0>;
> };
>
> cpu@3 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> reg = <3>;
> + cci-control-port = <&cci_control0>;
> };
>
> cpu@100 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> reg = <0x100>;
> + cci-control-port = <&cci_control1>;
> };
>
> cpu@101 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> reg = <0x101>;
> + cci-control-port = <&cci_control1>;
> };
>
> cpu@102 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> reg = <0x102>;
> + cci-control-port = <&cci_control1>;
> };
>
> cpu@103 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> reg = <0x103>;
> + cci-control-port = <&cci_control1>;
> };
> };
>
> @@ -314,6 +322,39 @@
> status = "disabled";
> };
>
> + cci: cci@1790000 {
You're not using that label, and you should order the node by physical
address.
> + compatible = "arm,cci-400";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x01790000 0x1000>;
The size is 0x10000.
> + ranges = <0x0 0x01790000 0x10000>;
> +
> + cci_control0: slave-if@4000 {
> + compatible = "arm,cci-400-ctrl-if";
> + interface-type = "ace";
> + reg = <0x4000 0x1000>;
> + };
> +
> + cci_control1: slave-if@5000 {
> + compatible = "arm,cci-400-ctrl-if";
> + interface-type = "ace";
> + reg = <0x5000 0x1000>;
> + };
> +
> + pmu@9000 {
> + compatible = "arm,cci-400-pmu,r1";
> + reg = <0x9000 0x5000>;
> + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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next prev parent reply other threads:[~2017-12-13 10:52 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-11 7:49 [PATCH 0/4] Sunxi: Add SMP support on A83T Mylène Josserand
2017-12-11 7:49 ` [PATCH 1/4] ARM: sunxi: mcpm: Add support for A83T Mylène Josserand
[not found] ` <20171211075001.6100-1-mylene.josserand-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-11 7:49 ` [PATCH 2/4] arm: dts: sun8i: a83t: Add registers needed for MCPM Mylène Josserand
2017-12-13 10:50 ` Maxime Ripard
2017-12-11 19:35 ` [PATCH 0/4] Sunxi: Add SMP support on A83T Corentin Labbe
2017-12-12 8:19 ` Mylene JOSSERAND
2017-12-12 8:24 ` Maxime Ripard
2017-12-15 6:10 ` Corentin Labbe
2017-12-27 15:07 ` Mylene JOSSERAND
[not found] ` <20171227160729.4509bec5-K8i4uRanGBt8XcdJbWeDu7NAH6kLmebB@public.gmane.org>
2017-12-28 20:31 ` Corentin Labbe
2017-12-29 11:04 ` Mylene JOSSERAND
2017-12-12 9:40 ` Mylene JOSSERAND
[not found] ` <20171212104025.0bba3685-K8i4uRanGBt8XcdJbWeDu7NAH6kLmebB@public.gmane.org>
2017-12-12 10:01 ` Mylene JOSSERAND
2017-12-11 7:50 ` [PATCH 3/4] arm: dts: sun8i: a83t: Add CCI-400 node Mylène Josserand
[not found] ` <20171211075001.6100-4-mylene.josserand-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-13 10:52 ` Maxime Ripard [this message]
2017-12-11 7:50 ` [PATCH 4/4] arm: dts: sun8i: a83t: Set timer node to use phy timer Mylène Josserand
2017-12-13 10:59 ` Maxime Ripard
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