From: Icenowy Zheng <icenowy@aosc.io>
To: Rob Herring <robh+dt@kernel.org>,
Maxime Ripard <maxime.ripard@bootlin.com>,
Chen-Yu Tsai <wens@csie.org>,
Linus Walleij <linus.walleij@linaro.org>
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org,
linux-sunxi@googlegroups.com, Icenowy Zheng <icenowy@aosc.io>
Subject: [PATCH v2 3/6] clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks
Date: Sat, 3 Feb 2018 23:49:39 +0800 [thread overview]
Message-ID: <20180203154942.63566-4-icenowy@aosc.io> (raw)
In-Reply-To: <20180203154942.63566-1-icenowy@aosc.io>
On the new Allwinner H6 SoC, multiple PLL's are NMP style clocks
(modelled as NKMP with no K) and have fixed post-dividers.
Add fixed post divider support to the NKMP style clocks.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
No changes in v2.
drivers/clk/sunxi-ng/ccu_nkmp.c | 20 +++++++++++++++++---
drivers/clk/sunxi-ng/ccu_nkmp.h | 2 ++
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
index e58c95787f94..497ac20deb19 100644
--- a/drivers/clk/sunxi-ng/ccu_nkmp.c
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
@@ -81,7 +81,7 @@ static unsigned long ccu_nkmp_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
- unsigned long n, m, k, p;
+ unsigned long n, m, k, p, rate;
u32 reg;
reg = readl(nkmp->common.base + nkmp->common.reg);
@@ -107,7 +107,11 @@ static unsigned long ccu_nkmp_recalc_rate(struct clk_hw *hw,
p = reg >> nkmp->p.shift;
p &= (1 << nkmp->p.width) - 1;
- return (parent_rate * n * k >> p) / m;
+ rate = (parent_rate * n * k >> p) / m;
+ if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
+ rate /= nkmp->fixed_post_div;
+
+ return rate;
}
static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
@@ -116,6 +120,9 @@ static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
struct _ccu_nkmp _nkmp;
+ if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
+ rate *= nkmp->fixed_post_div;
+
_nkmp.min_n = nkmp->n.min ?: 1;
_nkmp.max_n = nkmp->n.max ?: 1 << nkmp->n.width;
_nkmp.min_k = nkmp->k.min ?: 1;
@@ -127,7 +134,11 @@ static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
ccu_nkmp_find_best(*parent_rate, rate, &_nkmp);
- return *parent_rate * _nkmp.n * _nkmp.k / (_nkmp.m * _nkmp.p);
+ rate = *parent_rate * _nkmp.n * _nkmp.k / (_nkmp.m * _nkmp.p);
+ if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
+ rate = rate / nkmp->fixed_post_div;
+
+ return rate;
}
static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -138,6 +149,9 @@ static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long flags;
u32 reg;
+ if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
+ rate = rate * nkmp->fixed_post_div;
+
_nkmp.min_n = nkmp->n.min ?: 1;
_nkmp.max_n = nkmp->n.max ?: 1 << nkmp->n.width;
_nkmp.min_k = nkmp->k.min ?: 1;
diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.h b/drivers/clk/sunxi-ng/ccu_nkmp.h
index a82facbc6144..6940503e7fc4 100644
--- a/drivers/clk/sunxi-ng/ccu_nkmp.h
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.h
@@ -34,6 +34,8 @@ struct ccu_nkmp {
struct ccu_div_internal m;
struct ccu_div_internal p;
+ unsigned int fixed_post_div;
+
struct ccu_common common;
};
--
2.15.1
next prev parent reply other threads:[~2018-02-03 15:49 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-03 15:49 [PATCH v2 0/6] Initial Allwinner H6 support Icenowy Zheng
2018-02-03 15:49 ` Icenowy Zheng [this message]
[not found] ` <20180203154942.63566-1-icenowy-h8G6r0blFSE@public.gmane.org>
2018-02-03 15:49 ` [PATCH v2 1/6] pinctrl: sunxi: support pin controllers with holes among IRQ banks Icenowy Zheng
[not found] ` <20180203154942.63566-2-icenowy-h8G6r0blFSE@public.gmane.org>
2018-02-07 8:51 ` Maxime Ripard
2018-02-03 15:49 ` [PATCH v2 2/6] pinctrl: sunxi: add support for the Allwinner H6 main pin controller Icenowy Zheng
[not found] ` <20180203154942.63566-3-icenowy-h8G6r0blFSE@public.gmane.org>
2018-02-08 20:16 ` Rob Herring
2018-02-13 0:38 ` [linux-sunxi] " André Przywara
2018-02-03 15:49 ` [PATCH v2 4/6] clk: sunxi-ng: add support for the Allwinner H6 CCU Icenowy Zheng
2018-02-07 9:02 ` Maxime Ripard
2018-02-07 9:11 ` Icenowy Zheng
2018-02-07 18:49 ` Maxime Ripard
2018-02-08 20:18 ` Rob Herring
2018-02-03 15:49 ` [PATCH v2 5/6] arm64: allwinner: h6: add the basical Allwinner H6 DTSI file Icenowy Zheng
2018-02-11 23:26 ` [linux-sunxi] " André Przywara
2018-02-12 9:16 ` Philippe Ombredanne
2018-02-03 15:49 ` [PATCH v2 6/6] arm64: allwinner: h6: add support for Pine H64 board Icenowy Zheng
[not found] ` <20180203154942.63566-7-icenowy-h8G6r0blFSE@public.gmane.org>
2018-02-11 23:26 ` André Przywara
2018-02-22 12:43 ` [PATCH v2 0/6] Initial Allwinner H6 support Linus Walleij
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