Re: [PATCH v7 08/12] dt-bindings: dma: ti: Add document for K3 UDMA

[Vinod Koul <vkoul@kernel.org>]

On 09-12-19, 11:43, Peter Ujfalusi wrote:
> New binding document for
> Texas Instruments K3 NAVSS Unified DMA – Peripheral Root Complex (UDMA-P).
> 
> UDMA-P is introduced as part of the K3 architecture and can be found in
> AM654 and j721e.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
>  .../devicetree/bindings/dma/ti/k3-udma.yaml   | 185 ++++++++++++++++++
>  1 file changed, 185 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/dma/ti/k3-udma.yaml
> 
> diff --git a/Documentation/devicetree/bindings/dma/ti/k3-udma.yaml b/Documentation/devicetree/bindings/dma/ti/k3-udma.yaml
> new file mode 100644
> index 000000000000..77aef4a4abce
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/ti/k3-udma.yaml
> @@ -0,0 +1,185 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/ti/k3-udma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Texas Instruments K3 NAVSS Unified DMA Device Tree Bindings
> +
> +maintainers:
> +  - Peter Ujfalusi <peter.ujfalusi@ti.com>
> +
> +description: |
> +  The UDMA-P is intended to perform similar (but significantly upgraded)
> +  functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P
> +  module supports the transmission and reception of various packet types.
> +  The UDMA-P is architected to facilitate the segmentation and reassembly of

How about:

The UDMA-P architecture facilitates the segmentation...

> +  SoC DMA data structure compliant packets to/from smaller data blocks that are
> +  natively compatible with the specific requirements of each connected
> +  peripheral.
> +  Multiple Tx and Rx channels are provided within the DMA which allow multiple
> +  segmentation or reassembly operations to be ongoing. The DMA controller
> +  maintains state information for each of the channels which allows packet
> +  segmentation and reassembly operations to be time division multiplexed between
> +  channels in order to share the underlying DMA hardware. An external DMA
> +  scheduler is used to control the ordering and rate at which this multiplexing
> +  occurs for Transmit operations. The ordering and rate of Receive operations
> +  is indirectly controlled by the order in which blocks are pushed into the DMA
> +  on the Rx PSI-L interface.
> +
> +  The UDMA-P also supports acting as both a UTC and UDMA-C for its internal
> +  channels. Channels in the UDMA-P can be configured to be either Packet-Based
> +  or Third-Party channels on a channel by channel basis.
> +
> +  All transfers within NAVSS is done between PSI-L source and destination
> +  threads.
> +  The peripherals serviced by UDMA can be PSI-L native (sa2ul, cpsw, etc) or
> +  legacy, non PSI-L native peripherals. In the later case a special, small PDMA
> +  is tasked to act as a bridge between the PSI-L fabric and the legacy
> +  peripheral.
> +
> +  PDMAs can be configured via UDMAP peer registers to match with the
> +  configuration of the legacy peripheral.
> +
> +allOf:
> +  - $ref: "../dma-controller.yaml#"
> +
> +properties:
> +  "#dma-cells":
> +    const: 1
> +    description: |
> +      The cell is the PSI-L  thread ID of the remote (to UDMAP) end.
> +      Valid ranges for thread ID depends on the data movement direction:
> +      for source thread IDs (rx): 0 - 0x7fff
> +      for destination thread IDs (tx): 0x8000 - 0xffff
> +
> +      PLease refer to the device documentation for the PSI-L thread map and also

s/PLease/Please

-- 
~Vinod