From: Shawn Guo <shawnguo@kernel.org>
To: Joakim Zhang <qiangqing.zhang@nxp.com>
Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
mark.rutland@arm.com, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
Anson.Huang@nxp.com, leonard.crestez@nxp.com,
daniel.baluta@nxp.com, aisheng.dong@nxp.com, peng.fan@nxp.com,
fugang.duan@nxp.com, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/7] clk: imx: imx8qxp: Enable SCU and LPCG clocks for I2C in CM40 SS
Date: Tue, 10 Mar 2020 11:45:11 +0800 [thread overview]
Message-ID: <20200310034506.GC15729@dragon> (raw)
In-Reply-To: <1581909561-12058-5-git-send-email-qiangqing.zhang@nxp.com>
On Mon, Feb 17, 2020 at 11:19:18AM +0800, Joakim Zhang wrote:
> Enable SCU and LPCG clocks for I2C in CM40 SS.
>
> Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
So you decided to stop waiting for Aisheng's new imx8qxp clock driver?
Shawn
> ---
> drivers/clk/imx/clk-imx8qxp-lpcg.c | 12 ++++++++++++
> drivers/clk/imx/clk-imx8qxp-lpcg.h | 3 +++
> drivers/clk/imx/clk-imx8qxp.c | 4 ++++
> 3 files changed, 19 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c b/drivers/clk/imx/clk-imx8qxp-lpcg.c
> index 04c8ee35e14c..795909ecfba6 100644
> --- a/drivers/clk/imx/clk-imx8qxp-lpcg.c
> +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c
> @@ -151,6 +151,17 @@ static const struct imx8qxp_lpcg_data imx8qxp_lpcg_lsio[] = {
> { IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK, "pwm6_lpcg_ipg_mstr_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 24, 0, },
> };
>
> +static const struct imx8qxp_lpcg_data imx8qxp_lpcg_cm40[] = {
> + { IMX_CM40_LPCG_I2C_CLK, "cm40_lpcg_i2c_clk", "cm40_i2c_clk", 0, CM40_I2C_LPCG, 0, 0, },
> + { IMX_CM40_LPCG_I2C_IPG_CLK, "cm40_lpcg_i2c_ipg_clk", "cm40_ipg_clk_root", 0, CM40_I2C_LPCG, 16, 0, },
> +};
> +
> +static const struct imx8qxp_ss_lpcg imx8qxp_ss_cm40 = {
> + .lpcg = imx8qxp_lpcg_cm40,
> + .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_cm40),
> + .num_max = IMX_CM40_LPCG_CLK_END,
> +};
> +
> static const struct imx8qxp_ss_lpcg imx8qxp_ss_lsio = {
> .lpcg = imx8qxp_lpcg_lsio,
> .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_lsio),
> @@ -219,6 +230,7 @@ static const struct of_device_id imx8qxp_lpcg_match[] = {
> { .compatible = "fsl,imx8qxp-lpcg-adma", &imx8qxp_ss_adma, },
> { .compatible = "fsl,imx8qxp-lpcg-conn", &imx8qxp_ss_conn, },
> { .compatible = "fsl,imx8qxp-lpcg-lsio", &imx8qxp_ss_lsio, },
> + { .compatible = "fsl,imx8qxp-lpcg-cm40", &imx8qxp_ss_cm40, },
> { /* sentinel */ }
> };
>
> diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.h b/drivers/clk/imx/clk-imx8qxp-lpcg.h
> index 2a37ce57c500..28ca730dd135 100644
> --- a/drivers/clk/imx/clk-imx8qxp-lpcg.h
> +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.h
> @@ -99,4 +99,7 @@
> #define ADMA_FLEXCAN_1_LPCG 0x1ce0000
> #define ADMA_FLEXCAN_2_LPCG 0x1cf0000
>
> +/* CM40 SS */
> +#define CM40_I2C_LPCG 0x60000
> +
> #endif /* _IMX8QXP_LPCG_H */
> diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
> index 5e2903efc488..d051073ff042 100644
> --- a/drivers/clk/imx/clk-imx8qxp.c
> +++ b/drivers/clk/imx/clk-imx8qxp.c
> @@ -53,6 +53,7 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
> clks[IMX_HSIO_PER_CLK] = clk_hw_register_fixed_rate(NULL, "hsio_per_clk_root", NULL, 0, 133333333);
> clks[IMX_LSIO_MEM_CLK] = clk_hw_register_fixed_rate(NULL, "lsio_mem_clk_root", NULL, 0, 200000000);
> clks[IMX_LSIO_BUS_CLK] = clk_hw_register_fixed_rate(NULL, "lsio_bus_clk_root", NULL, 0, 100000000);
> + clks[IMX_CM40_IPG_CLK] = clk_hw_register_fixed_rate(NULL, "cm40_ipg_clk_root", NULL, 0, 132000000);
>
> /* ARM core */
> clks[IMX_A35_CLK] = imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU);
> @@ -128,6 +129,9 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
> clks[IMX_GPU0_CORE_CLK] = imx_clk_scu("gpu_core0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER);
> clks[IMX_GPU0_SHADER_CLK] = imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC);
>
> + /* CM40 SS */
> + clks[IMX_CM40_I2C_CLK] = imx_clk_scu("cm40_i2c_clk", IMX_SC_R_M4_0_I2C, IMX_SC_PM_CLK_PER);
> +
> for (i = 0; i < clk_data->num; i++) {
> if (IS_ERR(clks[i]))
> pr_warn("i.MX clk %u: register failed with %ld\n",
> --
> 2.17.1
>
next prev parent reply other threads:[~2020-03-10 3:45 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-17 3:19 [PATCH 0/7] Add FlexCAN support on i.MX8QXP Joakim Zhang
2020-02-17 3:19 ` [PATCH 1/7] firmware: imx: scu-pd: add power domain for I2C and INTMUX in CM40 SS Joakim Zhang
2020-03-10 3:32 ` Shawn Guo
2020-02-17 3:19 ` [PATCH 2/7] clk: imx8: Add SCU and LPCG clocks for I2C " Joakim Zhang
2020-02-25 17:57 ` Rob Herring
2020-02-26 2:56 ` Joakim Zhang
2020-03-10 3:42 ` Shawn Guo
2020-02-17 3:19 ` [PATCH 3/7] bindings: clock: imx8qxp: add "fsl,imx8qxp-lpcg-cm40" compatible string Joakim Zhang
2020-02-25 17:58 ` Rob Herring
2020-02-17 3:19 ` [PATCH 4/7] clk: imx: imx8qxp: Enable SCU and LPCG clocks for I2C in CM40 SS Joakim Zhang
2020-03-10 3:45 ` Shawn Guo [this message]
2020-03-10 6:01 ` Joakim Zhang
2020-02-17 3:19 ` [PATCH 5/7] arch: arm64: dts: imx8qxp: add device node for I2C and INTMUX " Joakim Zhang
2020-03-10 3:49 ` Shawn Guo
2020-02-17 3:19 ` [PATCH 6/7] clk: imx: imx8qxp: add LPCG clock for FlexCAN in ADMA SS Joakim Zhang
2020-02-17 3:19 ` [PATCH 7/7] arch: arm64: dts: imx8qxp: add device node for CAN " Joakim Zhang
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