[PATCH 1/6] ARM: dts: imx6ul: segin: Fix stmpe touchscreen subnode name

[PATCH 1/6] ARM: dts: imx6ul: segin: Fix stmpe touchscreen subnode name

[Stefan Riedmueller]

The touchscreen subnode name needs to be stmpe_touchscreen as mentioned
in the dt-bindings.

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
 arch/arm/boot/dts/imx6ul-phytec-segin.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
index f1412df89173..2a3801e349b6 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
@@ -139,7 +139,7 @@ stmpe: touchscreen@44 {
 		pinctrl-0 = <&pinctrl_stmpe>;
 		status = "disabled";
 
-		touchscreen {
+		stmpe_touchscreen {
 			compatible = "st,stmpe-ts";
 			st,sample-time = <4>;
 			st,mod-12b = <1>;
-- 
2.25.1

[PATCH 2/6] ARM: dts: imx6: phytec: Set correct eeprom compatible

[Stefan Riedmueller]

Set the correct EEPROM compatible for phyCORE-i.MX 6 and phyFLEX-i.MX 6,
as stated in the device tree bindings.

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
 arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi      | 2 +-
 arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index bc43c75f1745..aa7fdb9ea5bd 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -116,7 +116,7 @@ &i2c1 {
 	status = "okay";
 
 	som_eeprom: eeprom@50 {
-		compatible = "atmel,24c32";
+		compatible = "catalyst,24c32", "atmel,24c32";
 		reg = <0x50>;
 	};
 
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
index 41ebe4599e43..a3f4e8f6cc9e 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
@@ -84,7 +84,7 @@ &i2c3 {
 	status = "okay";
 
 	eeprom@50 {
-		compatible = "atmel,24c32";
+		compatible = "st,24c32", "atmel,24c32";
 		reg = <0x50>;
 	};
 
-- 
2.25.1

[PATCH 3/6] ARM: dts: imx6: phytec: Add eeprom pagesize

[Stefan Riedmueller]

Defining the EEPROM pagesize can increase the write speed significantly.
Set it to the pagesize stated in the EEPROM's datasheet for
phyCORE-i.MX 6UL, phyCORE-i.MX 6 and phyFLEX-i.MX 6.

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
 arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi      | 1 +
 arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi | 1 +
 arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi  | 1 +
 3 files changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index aa7fdb9ea5bd..87adfb735f95 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -117,6 +117,7 @@ &i2c1 {
 
 	som_eeprom: eeprom@50 {
 		compatible = "catalyst,24c32", "atmel,24c32";
+		pagesize = <32>;
 		reg = <0x50>;
 	};
 
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
index a3f4e8f6cc9e..a80aa08a37cb 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
@@ -85,6 +85,7 @@ &i2c3 {
 
 	eeprom@50 {
 		compatible = "st,24c32", "atmel,24c32";
+		pagesize = <32>;
 		reg = <0x50>;
 	};
 
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
index ce14ce685d12..11fa3fb5947b 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
@@ -75,6 +75,7 @@ &i2c1 {
 
 	eeprom@52 {
 		compatible = "catalyst,24c32", "atmel,24c32";
+		pagesize = <32>;
 		reg = <0x52>;
 	};
 };
-- 
2.25.1

[PATCH 4/6] ARM: dts: imx6ul: segin: Add phyBOARD-Segin with eMMC phyCORE-i.MX6UL

[Stefan Riedmueller]

From: Yunus Bas <y.bas@phytec.de>

Add a PHYTEC phyBOARD-Segin full featured with phyCORE-i.MX 6UL with
eMMC and following features:
    - i.MX 6UL
    - 512 MB RAM
    - eMMC
    - USB Host/OTG
    - 2x 100 Mbit/s Ethernet
    - RS232
    - CAN

Signed-off-by: Yunus Bas <y.bas@phytec.de>
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
 arch/arm/boot/dts/Makefile                    |  1 +
 .../dts/imx6ul-phytec-segin-ff-rdk-emmc.dts   | 93 +++++++++++++++++++
 2 files changed, 94 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4572db3fa5ae..81ede0707a51 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -615,6 +615,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
 	imx6ul-pico-dwarf.dtb \
 	imx6ul-pico-hobbit.dtb \
 	imx6ul-pico-pi.dtb \
+	imx6ul-phytec-segin-ff-rdk-emmc.dtb \
 	imx6ul-phytec-segin-ff-rdk-nand.dtb \
 	imx6ul-tx6ul-0010.dtb \
 	imx6ul-tx6ul-0011.dtb \
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts
new file mode 100644
index 000000000000..934c05fad615
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (C) 2020 PHYTEC Messtechnik GmbH
+ * Author: Yunus Bas <y.bas@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6ul.dtsi"
+#include "imx6ul-phytec-phycore-som.dtsi"
+#include "imx6ul-phytec-segin.dtsi"
+#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
+
+/ {
+	model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with eMMC";
+	compatible = "phytec,imx6ul-pbacd10-emmc", "phytec,imx6ul-pbacd10",
+		     "phytec,imx6ul-pcl063","fsl,imx6ul";
+};
+
+&adc1 {
+	status = "okay";
+};
+
+&can1 {
+	status = "okay";
+};
+
+&tlv320 {
+	status = "okay";
+};
+
+&ecspi3 {
+	status = "okay";
+};
+
+&ethphy1 {
+	status = "okay";
+};
+
+&ethphy2 {
+	status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+};
+
+&fec2 {
+	status = "okay";
+};
+
+&i2c_rtc {
+	status = "okay";
+};
+
+&reg_can1_en {
+	status = "okay";
+};
+
+&reg_sound_1v8 {
+	status = "okay";
+};
+
+&reg_sound_3v3 {
+	status = "okay";
+};
+
+&sai2 {
+	status = "okay";
+};
+
+&sound {
+	status = "okay";
+};
+
+&uart5 {
+	status = "okay";
+};
+
+&usbotg1 {
+	status = "okay";
+};
+
+&usbotg2 {
+	status = "okay";
+};
+
+&usdhc1 {
+	status = "okay";
+};
+
+&usdhc2 {
+	status = "okay";
+};
-- 
2.25.1

[PATCH 5/6] ARM: dts: imx6ul: phytec: Add support for optional PEB-AV-02 LCD adapter

[Stefan Riedmueller]

The PHYTEC PEB-AV-02 adapter adds the capability to connect a parallel
LCD display to the phyBOARD-Segin full featured, either with capacitive
or resistive touch.

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
 .../dts/imx6ul-phytec-segin-ff-rdk-emmc.dts   |   1 +
 .../dts/imx6ul-phytec-segin-ff-rdk-nand.dts   |   1 +
 .../dts/imx6ul-phytec-segin-peb-av-02.dtsi    | 150 ++++++++++++++++++
 arch/arm/boot/dts/imx6ul-phytec-segin.dtsi    |  43 -----
 .../dts/imx6ull-phytec-segin-ff-rdk-emmc.dts  |   1 +
 .../dts/imx6ull-phytec-segin-ff-rdk-nand.dts  |   1 +
 .../dts/imx6ull-phytec-segin-peb-av-02.dtsi   |  26 +++
 arch/arm/boot/dts/imx6ull-phytec-segin.dtsi   |   7 -
 8 files changed, 180 insertions(+), 50 deletions(-)
 create mode 100644 arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi
 create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi

diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts
index 934c05fad615..83ef5af0501e 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts
@@ -9,6 +9,7 @@
 #include "imx6ul-phytec-phycore-som.dtsi"
 #include "imx6ul-phytec-segin.dtsi"
 #include "imx6ul-phytec-segin-peb-eval-01.dtsi"
+#include "imx6ul-phytec-segin-peb-av-02.dtsi"
 
 / {
 	model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with eMMC";
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
index bfda5eda7a25..8296059c0084 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
@@ -9,6 +9,7 @@
 #include "imx6ul-phytec-phycore-som.dtsi"
 #include "imx6ul-phytec-segin.dtsi"
 #include "imx6ul-phytec-segin-peb-eval-01.dtsi"
+#include "imx6ul-phytec-segin-peb-av-02.dtsi"
 
 / {
 	model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND";
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi
new file mode 100644
index 000000000000..86898546627c
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (C) 2016, 2020 PHYTEC Messtechnik
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ */
+
+/ {
+	backlight_lcd: backlight-lcd {
+		compatible = "pwm-backlight";
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <5>;
+		power-supply = <&reg_backlight_en>;
+		pwms = <&pwm3 0 5000000>;
+		status = "disabled";
+	};
+
+	lcd_panel: lcd-panel {
+		compatible = "edt,etm0700g0edh6";
+		backlight = <&backlight_lcd>;
+		status = "disabled";
+
+		port {
+			lcd_panel_in: endpoint {
+				remote-endpoint = <&lcdif_parallel_out>;
+			};
+		};
+	};
+
+	reg_backlight_en: regulator-backlight-en {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_backlight_en>;
+		regulator-name = "backlight-lcd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&lcdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lcdif_dat>;
+	status = "disabled";
+
+	port {
+		lcdif_parallel_out: endpoint {
+			remote-endpoint = <&lcd_panel_in>;
+		};
+	};
+};
+
+&i2c1 {
+	edt_ft5406: touchscreen@38 {
+		compatible = "edt,edt-ft5406";
+		reg = <0x38>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_edt_ft5406>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+		wakeup-source;
+		status = "disabled";
+	};
+
+	stmpe: touchscreen@44 {
+		compatible = "st,stmpe811";
+		reg = <0x44>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_stmpe>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-parent = <&gpio5>;
+		status = "disabled";
+
+		stmpe_touchscreen {
+			compatible = "st,stmpe-ts";
+			st,sample-time = <4>;
+			st,mod-12b = <1>;
+			st,ref-sel = <0>;
+			st,adc-freq = <1>;
+			st,ave-ctrl = <1>;
+			st,touch-det-delay = <2>;
+			st,settling = <2>;
+			st,fraction-z = <7>;
+			st,i-drive = <1>;
+			touchscreen-inverted-x = <1>;
+			touchscreen-inverted-y = <1>;
+		};
+	};
+};
+
+&pwm3 {
+	#pwm-cells = <2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm3>;
+	status = "disabled";
+};
+
+&iomuxc {
+	pinctrl_edt_ft5406: edtft5406grp {
+		fsl,pins = <
+			MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x1b0b0
+		>;
+	};
+
+	pinctrl_backlight_en: bachlightengrp {
+		fsl,pins = <
+			MX6UL_PAD_UART1_CTS_B__GPIO1_IO18	0x1b0b0
+		>;
+	};
+
+	pinctrl_lcdif_dat: lcdifdatgrp {
+		fsl,pins = <
+			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x59
+			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x59
+			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x59
+			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x59
+			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x59
+			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x59
+			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x59
+			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x59
+			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x59
+			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x59
+			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x59
+			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x59
+			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x59
+			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x59
+			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x59
+			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x59
+			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x59
+			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x59
+			MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x59
+			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x59
+			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x59
+			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x59
+		>;
+	};
+
+	pinctrl_pwm3: pwm3grp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO04__PWM3_OUT	0x0b0b0
+		>;
+	};
+
+	pinctrl_stmpe: stmpegrp {
+		fsl,pins = <
+			MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x17059
+		>;
+	};
+};
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
index 2a3801e349b6..df8d228df89d 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
@@ -130,31 +130,6 @@ tlv320: codec@18 {
 		status = "disabled";
 	};
 
-	stmpe: touchscreen@44 {
-		compatible = "st,stmpe811";
-		reg = <0x44>;
-		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
-		interrupt-parent = <&gpio5>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_stmpe>;
-		status = "disabled";
-
-		stmpe_touchscreen {
-			compatible = "st,stmpe-ts";
-			st,sample-time = <4>;
-			st,mod-12b = <1>;
-			st,ref-sel = <0>;
-			st,adc-freq = <1>;
-			st,ave-ctrl = <1>;
-			st,touch-det-delay = <2>;
-			st,settling = <2>;
-			st,fraction-z = <7>;
-			st,i-drive = <1>;
-			touchscreen-inverted-x = <1>;
-			touchscreen-inverted-y = <1>;
-		};
-	};
-
 	i2c_rtc: rtc@68 {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_rtc_int>;
@@ -176,12 +151,6 @@ ethphy2: ethernet-phy@2 {
 	};
 };
 
-&pwm3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm3>;
-	status = "disabled";
-};
-
 &sai2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_sai2>;
@@ -267,12 +236,6 @@ MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x17059
 		>;
 	};
 
-	pinctrl_pwm3: pwm3grp {
-		fsl,pins = <
-			MX6UL_PAD_GPIO1_IO04__PWM3_OUT	0x0b0b0
-		>;
-	};
-
 	pinctrl_rtc_int: rtcintgrp {
 		fsl,pins = <
 			MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x17059
@@ -289,12 +252,6 @@ MX6UL_PAD_JTAG_TMS__SAI2_MCLK		0x17088
 		>;
 	};
 
-	pinctrl_stmpe: stmpegrp {
-		fsl,pins = <
-			MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x17059
-		>;
-	};
-
 	pinctrl_uart5: uart5grp {
 		fsl,pins = <
 			MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX	0x1b0b1
diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
index 9648d4ecaf58..8e2a4c5d7765 100644
--- a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
+++ b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
@@ -9,6 +9,7 @@
 #include "imx6ull-phytec-phycore-som.dtsi"
 #include "imx6ull-phytec-segin.dtsi"
 #include "imx6ull-phytec-segin-peb-eval-01.dtsi"
+#include "imx6ull-phytec-segin-peb-av-02.dtsi"
 
 / {
 	model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with eMMC";
diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
index 656baf846453..c8d3eff9ed4b 100644
--- a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts
@@ -9,6 +9,7 @@
 #include "imx6ull-phytec-phycore-som.dtsi"
 #include "imx6ull-phytec-segin.dtsi"
 #include "imx6ull-phytec-segin-peb-eval-01.dtsi"
+#include "imx6ull-phytec-segin-peb-av-02.dtsi"
 
 / {
 	model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with NAND";
diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi
new file mode 100644
index 000000000000..06bb7f327780
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (C) 2018 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ */
+
+#include "imx6ul-phytec-segin-peb-av-02.dtsi"
+
+&iomuxc {
+	/delete-node/ edtft5406grp;
+	/delete-node/ stmpegrp;
+};
+
+&iomuxc_snvs {
+	pinctrl_edt_ft5406: edtft5406grp {
+		fsl,pins = <
+			MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x1b0b0
+		>;
+	};
+
+	pinctrl_stmpe: stmpegrp {
+		fsl,pins = <
+			MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x17059
+		>;
+	};
+};
diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi
index c1595fc785f7..e287a0453b5f 100644
--- a/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi
+++ b/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi
@@ -14,7 +14,6 @@ / {
 &iomuxc {
 	/delete-node/ flexcan1engrp;
 	/delete-node/ rtcintgrp;
-	/delete-node/ stmpegrp;
 };
 
 &iomuxc_snvs {
@@ -29,10 +28,4 @@ pinctrl_rtc_int: rtcintgrp {
 			MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x17059
 		>;
 	};
-
-	pinctrl_stmpe: stmpegrp {
-		fsl,pins = <
-			MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x17059
-		>;
-	};
 };
-- 
2.25.1

[PATCH 6/6] ARM: dts: imx6ul: segin: peb-av-02: Mark stmpe touch as wakeup-source

[Stefan Riedmueller]

Mark the STMPE resistive touch controller as a wakeup-source.

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
 arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi
index 86898546627c..610b778c753a 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi
@@ -70,6 +70,7 @@ stmpe: touchscreen@44 {
 		pinctrl-0 = <&pinctrl_stmpe>;
 		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 		interrupt-parent = <&gpio5>;
+		wakeup-source;
 		status = "disabled";
 
 		stmpe_touchscreen {
-- 
2.25.1

Re: [PATCH 1/6] ARM: dts: imx6ul: segin: Fix stmpe touchscreen subnode name

[Stefan Riedmüller]

Hi,

just a gentle ping for this series.

Stefan

On 22.09.20 11:23, Stefan Riedmueller wrote:
> The touchscreen subnode name needs to be stmpe_touchscreen as mentioned
> in the dt-bindings.
> 
> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
> ---
>   arch/arm/boot/dts/imx6ul-phytec-segin.dtsi | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
> index f1412df89173..2a3801e349b6 100644
> --- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
> +++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
> @@ -139,7 +139,7 @@ stmpe: touchscreen@44 {
>   		pinctrl-0 = <&pinctrl_stmpe>;
>   		status = "disabled";
>   
> -		touchscreen {
> +		stmpe_touchscreen {
>   			compatible = "st,stmpe-ts";
>   			st,sample-time = <4>;
>   			st,mod-12b = <1>;
> 

Re: [PATCH 4/6] ARM: dts: imx6ul: segin: Add phyBOARD-Segin with eMMC phyCORE-i.MX6UL

[Shawn Guo]

On Tue, Sep 22, 2020 at 11:23:11AM +0200, Stefan Riedmueller wrote:
> From: Yunus Bas <y.bas@phytec.de>
> 
> Add a PHYTEC phyBOARD-Segin full featured with phyCORE-i.MX 6UL with
> eMMC and following features:
>     - i.MX 6UL
>     - 512 MB RAM
>     - eMMC
>     - USB Host/OTG
>     - 2x 100 Mbit/s Ethernet
>     - RS232
>     - CAN
> 
> Signed-off-by: Yunus Bas <y.bas@phytec.de>
> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
> ---
>  arch/arm/boot/dts/Makefile                    |  1 +
>  .../dts/imx6ul-phytec-segin-ff-rdk-emmc.dts   | 93 +++++++++++++++++++
>  2 files changed, 94 insertions(+)
>  create mode 100644 arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 4572db3fa5ae..81ede0707a51 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -615,6 +615,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
>  	imx6ul-pico-dwarf.dtb \
>  	imx6ul-pico-hobbit.dtb \
>  	imx6ul-pico-pi.dtb \
> +	imx6ul-phytec-segin-ff-rdk-emmc.dtb \
>  	imx6ul-phytec-segin-ff-rdk-nand.dtb \
>  	imx6ul-tx6ul-0010.dtb \
>  	imx6ul-tx6ul-0011.dtb \
> diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts
> new file mode 100644
> index 000000000000..934c05fad615
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts
> @@ -0,0 +1,93 @@
> +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
> +/*
> + * Copyright (C) 2020 PHYTEC Messtechnik GmbH
> + * Author: Yunus Bas <y.bas@phytec.de>
> + */
> +
> +/dts-v1/;
> +#include "imx6ul.dtsi"
> +#include "imx6ul-phytec-phycore-som.dtsi"
> +#include "imx6ul-phytec-segin.dtsi"
> +#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
> +
> +/ {
> +	model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with eMMC";
> +	compatible = "phytec,imx6ul-pbacd10-emmc", "phytec,imx6ul-pbacd10",
> +		     "phytec,imx6ul-pcl063","fsl,imx6ul";
> +};
> +
> +&adc1 {
> +	status = "okay";
> +};
> +
> +&can1 {
> +	status = "okay";
> +};
> +
> +&tlv320 {
> +	status = "okay";
> +};

It breaks the alphabetic order.

Shawn

> +
> +&ecspi3 {
> +	status = "okay";
> +};
> +
> +&ethphy1 {
> +	status = "okay";
> +};
> +
> +&ethphy2 {
> +	status = "okay";
> +};
> +
> +&fec1 {
> +	status = "okay";
> +};
> +
> +&fec2 {
> +	status = "okay";
> +};
> +
> +&i2c_rtc {
> +	status = "okay";
> +};
> +
> +&reg_can1_en {
> +	status = "okay";
> +};
> +
> +&reg_sound_1v8 {
> +	status = "okay";
> +};
> +
> +&reg_sound_3v3 {
> +	status = "okay";
> +};
> +
> +&sai2 {
> +	status = "okay";
> +};
> +
> +&sound {
> +	status = "okay";
> +};
> +
> +&uart5 {
> +	status = "okay";
> +};
> +
> +&usbotg1 {
> +	status = "okay";
> +};
> +
> +&usbotg2 {
> +	status = "okay";
> +};
> +
> +&usdhc1 {
> +	status = "okay";
> +};
> +
> +&usdhc2 {
> +	status = "okay";
> +};
> -- 
> 2.25.1
> 

Re: [PATCH 1/6] ARM: dts: imx6ul: segin: Fix stmpe touchscreen subnode name

[Shawn Guo]

On Tue, Sep 22, 2020 at 11:23:08AM +0200, Stefan Riedmueller wrote:
> The touchscreen subnode name needs to be stmpe_touchscreen as mentioned
> in the dt-bindings.
> 
> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>

Applied, thanks.

Re: [PATCH 2/6] ARM: dts: imx6: phytec: Set correct eeprom compatible

[Shawn Guo]

On Tue, Sep 22, 2020 at 11:23:09AM +0200, Stefan Riedmueller wrote:
> Set the correct EEPROM compatible for phyCORE-i.MX 6 and phyFLEX-i.MX 6,
> as stated in the device tree bindings.
> 
> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>

Applied, thanks.

Re: [PATCH 3/6] ARM: dts: imx6: phytec: Add eeprom pagesize

[Shawn Guo]

On Tue, Sep 22, 2020 at 11:23:10AM +0200, Stefan Riedmueller wrote:
> Defining the EEPROM pagesize can increase the write speed significantly.
> Set it to the pagesize stated in the EEPROM's datasheet for
> phyCORE-i.MX 6UL, phyCORE-i.MX 6 and phyFLEX-i.MX 6.
> 
> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>

Applied, thanks.

Re: [PATCH 4/6] ARM: dts: imx6ul: segin: Add phyBOARD-Segin with eMMC phyCORE-i.MX6UL

[Stefan Riedmüller]

Hi Shawn,

On 28.10.20 09:46, Shawn Guo wrote:
> On Tue, Sep 22, 2020 at 11:23:11AM +0200, Stefan Riedmueller wrote:
>> From: Yunus Bas <y.bas@phytec.de>
>>
>> Add a PHYTEC phyBOARD-Segin full featured with phyCORE-i.MX 6UL with
>> eMMC and following features:
>>      - i.MX 6UL
>>      - 512 MB RAM
>>      - eMMC
>>      - USB Host/OTG
>>      - 2x 100 Mbit/s Ethernet
>>      - RS232
>>      - CAN
>>
>> Signed-off-by: Yunus Bas <y.bas@phytec.de>
>> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
>> ---
>>   arch/arm/boot/dts/Makefile                    |  1 +
>>   .../dts/imx6ul-phytec-segin-ff-rdk-emmc.dts   | 93 +++++++++++++++++++
>>   2 files changed, 94 insertions(+)
>>   create mode 100644 arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index 4572db3fa5ae..81ede0707a51 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -615,6 +615,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
>>   	imx6ul-pico-dwarf.dtb \
>>   	imx6ul-pico-hobbit.dtb \
>>   	imx6ul-pico-pi.dtb \
>> +	imx6ul-phytec-segin-ff-rdk-emmc.dtb \
>>   	imx6ul-phytec-segin-ff-rdk-nand.dtb \
>>   	imx6ul-tx6ul-0010.dtb \
>>   	imx6ul-tx6ul-0011.dtb \
>> diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts
>> new file mode 100644
>> index 000000000000..934c05fad615
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts
>> @@ -0,0 +1,93 @@
>> +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
>> +/*
>> + * Copyright (C) 2020 PHYTEC Messtechnik GmbH
>> + * Author: Yunus Bas <y.bas@phytec.de>
>> + */
>> +
>> +/dts-v1/;
>> +#include "imx6ul.dtsi"
>> +#include "imx6ul-phytec-phycore-som.dtsi"
>> +#include "imx6ul-phytec-segin.dtsi"
>> +#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
>> +
>> +/ {
>> +	model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with eMMC";
>> +	compatible = "phytec,imx6ul-pbacd10-emmc", "phytec,imx6ul-pbacd10",
>> +		     "phytec,imx6ul-pcl063","fsl,imx6ul";
>> +};
>> +
>> +&adc1 {
>> +	status = "okay";
>> +};
>> +
>> +&can1 {
>> +	status = "okay";
>> +};
>> +
>> +&tlv320 {
>> +	status = "okay";
>> +};
> 
> It breaks the alphabetic order.

Ah sorry, I missed that. I'll send a v2.

Thanks,
Stefan

> 
> Shawn
> 
>> +
>> +&ecspi3 {
>> +	status = "okay";
>> +};
>> +
>> +&ethphy1 {
>> +	status = "okay";
>> +};
>> +
>> +&ethphy2 {
>> +	status = "okay";
>> +};
>> +
>> +&fec1 {
>> +	status = "okay";
>> +};
>> +
>> +&fec2 {
>> +	status = "okay";
>> +};
>> +
>> +&i2c_rtc {
>> +	status = "okay";
>> +};
>> +
>> +&reg_can1_en {
>> +	status = "okay";
>> +};
>> +
>> +&reg_sound_1v8 {
>> +	status = "okay";
>> +};
>> +
>> +&reg_sound_3v3 {
>> +	status = "okay";
>> +};
>> +
>> +&sai2 {
>> +	status = "okay";
>> +};
>> +
>> +&sound {
>> +	status = "okay";
>> +};
>> +
>> +&uart5 {
>> +	status = "okay";
>> +};
>> +
>> +&usbotg1 {
>> +	status = "okay";
>> +};
>> +
>> +&usbotg2 {
>> +	status = "okay";
>> +};
>> +
>> +&usdhc1 {
>> +	status = "okay";
>> +};
>> +
>> +&usdhc2 {
>> +	status = "okay";
>> +};
>> -- 
>> 2.25.1
>>