* [PATCH 0/5] ASoC: Mediatek: Add support for MT8192 SoC
@ 2020-10-02 7:35 Jiaxin Yu
2020-10-02 7:35 ` [PATCH 1/5] ASoC: mediatek: mt6359: add the calibration functions Jiaxin Yu
` (4 more replies)
0 siblings, 5 replies; 12+ messages in thread
From: Jiaxin Yu @ 2020-10-02 7:35 UTC (permalink / raw)
To: broonie, tiwai, matthias.bgg, robh+dt, p.zabel, tzungbi,
alsa-devel, linux-arm-kernel, linux-mediatek, devicetree
Cc: shane.chien, kuninori.morimoto.gx, maowenan, Jiaxin Yu
This series of patches adds support for Mediatek AFE for MT8192 SoC. At the same
time, the calibration function of MT6359 is completed with real machine driver.
The patch is based on broonie tree "for-next" branch.
Jiaxin Yu (5):
ASoC: mediatek: mt6359: add the calibration functions
ASoC: mediatek: mt8192: add platform driver
dt-bindings: mediatek: mt8192: add audio afe document
ASoC: mediatek: mt8192: add machine driver with mt6359, rt1015 and
rt5682
dt-bindings: mediatek: mt8192: add mt8192-mt6358-rt1015-rt5682
document
.../bindings/sound/mt8192-afe-pcm.yaml | 98 +
.../sound/mt8192-mt6359-rt1015-rt5682.yaml | 44 +
sound/soc/codecs/mt6359.c | 110 +
sound/soc/codecs/mt6359.h | 7 +
sound/soc/mediatek/Kconfig | 23 +
sound/soc/mediatek/Makefile | 1 +
sound/soc/mediatek/common/mtk-afe-fe-dai.c | 13 +-
sound/soc/mediatek/common/mtk-base-afe.h | 1 +
sound/soc/mediatek/mt8192/Makefile | 16 +
sound/soc/mediatek/mt8192/mt8192-afe-clk.c | 669 ++++
sound/soc/mediatek/mt8192/mt8192-afe-clk.h | 244 ++
sound/soc/mediatek/mt8192/mt8192-afe-common.h | 170 +
.../soc/mediatek/mt8192/mt8192-afe-control.c | 163 +
sound/soc/mediatek/mt8192/mt8192-afe-gpio.c | 306 ++
sound/soc/mediatek/mt8192/mt8192-afe-gpio.h | 19 +
sound/soc/mediatek/mt8192/mt8192-afe-pcm.c | 2389 +++++++++++++
sound/soc/mediatek/mt8192/mt8192-dai-adda.c | 1489 ++++++++
sound/soc/mediatek/mt8192/mt8192-dai-i2s.c | 2139 +++++++++++
sound/soc/mediatek/mt8192/mt8192-dai-pcm.c | 409 +++
sound/soc/mediatek/mt8192/mt8192-dai-tdm.c | 778 ++++
.../mediatek/mt8192/mt8192-interconnection.h | 65 +
.../mt8192/mt8192-mt6359-rt1015-rt5682.c | 1058 ++++++
sound/soc/mediatek/mt8192/mt8192-reg.h | 3131 +++++++++++++++++
23 files changed, 13338 insertions(+), 4 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
create mode 100644 Documentation/devicetree/bindings/sound/mt8192-mt6359-rt1015-rt5682.yaml
create mode 100644 sound/soc/mediatek/mt8192/Makefile
create mode 100644 sound/soc/mediatek/mt8192/mt8192-afe-clk.c
create mode 100644 sound/soc/mediatek/mt8192/mt8192-afe-clk.h
create mode 100644 sound/soc/mediatek/mt8192/mt8192-afe-common.h
create mode 100644 sound/soc/mediatek/mt8192/mt8192-afe-control.c
create mode 100644 sound/soc/mediatek/mt8192/mt8192-afe-gpio.c
create mode 100644 sound/soc/mediatek/mt8192/mt8192-afe-gpio.h
create mode 100644 sound/soc/mediatek/mt8192/mt8192-afe-pcm.c
create mode 100644 sound/soc/mediatek/mt8192/mt8192-dai-adda.c
create mode 100644 sound/soc/mediatek/mt8192/mt8192-dai-i2s.c
create mode 100644 sound/soc/mediatek/mt8192/mt8192-dai-pcm.c
create mode 100644 sound/soc/mediatek/mt8192/mt8192-dai-tdm.c
create mode 100644 sound/soc/mediatek/mt8192/mt8192-interconnection.h
create mode 100644 sound/soc/mediatek/mt8192/mt8192-mt6359-rt1015-rt5682.c
create mode 100644 sound/soc/mediatek/mt8192/mt8192-reg.h
--
2.18.0
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/5] ASoC: mediatek: mt6359: add the calibration functions
2020-10-02 7:35 [PATCH 0/5] ASoC: Mediatek: Add support for MT8192 SoC Jiaxin Yu
@ 2020-10-02 7:35 ` Jiaxin Yu
2020-10-02 7:35 ` [PATCH 3/5] dt-bindings: mediatek: mt8192: add audio afe document Jiaxin Yu
` (3 subsequent siblings)
4 siblings, 0 replies; 12+ messages in thread
From: Jiaxin Yu @ 2020-10-02 7:35 UTC (permalink / raw)
To: broonie, tiwai, matthias.bgg, robh+dt, p.zabel, tzungbi,
alsa-devel, linux-arm-kernel, linux-mediatek, devicetree
Cc: shane.chien, kuninori.morimoto.gx, maowenan, Jiaxin Yu
Add the calibraion functions for initializing the codec when registering
the machine driver.
Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
---
sound/soc/codecs/mt6359.c | 110 ++++++++++++++++++++++++++++++++++++++
sound/soc/codecs/mt6359.h | 7 +++
2 files changed, 117 insertions(+)
diff --git a/sound/soc/codecs/mt6359.c b/sound/soc/codecs/mt6359.c
index 81aafb553bdd9..d20c59a875246 100644
--- a/sound/soc/codecs/mt6359.c
+++ b/sound/soc/codecs/mt6359.c
@@ -68,6 +68,38 @@ static void mt6359_reset_capture_gpio(struct mt6359_priv *priv)
0x3 << 0, 0x0);
}
+/* use only when doing mtkaif calibraiton at the boot time */
+static void mt6359_set_dcxo(struct mt6359_priv *priv, bool enable)
+{
+ regmap_update_bits(priv->regmap, MT6359_DCXO_CW12,
+ 0x1 << RG_XO_AUDIO_EN_M_SFT,
+ (enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT);
+}
+
+/* use only when doing mtkaif calibraiton at the boot time */
+static void mt6359_set_clksq(struct mt6359_priv *priv, bool enable)
+{
+ /* Enable/disable CLKSQ 26MHz */
+ regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON23,
+ RG_CLKSQ_EN_MASK_SFT,
+ (enable ? 1 : 0) << RG_CLKSQ_EN_SFT);
+}
+
+/* use only when doing mtkaif calibraiton at the boot time */
+static void mt6359_set_aud_global_bias(struct mt6359_priv *priv, bool enable)
+{
+ regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON13,
+ RG_AUDGLB_PWRDN_VA32_MASK_SFT,
+ (enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA32_SFT);
+}
+
+/* use only when doing mtkaif calibraiton at the boot time */
+static void mt6359_set_topck(struct mt6359_priv *priv, bool enable)
+{
+ regmap_update_bits(priv->regmap, MT6359_AUD_TOP_CKPDN_CON0,
+ 0x0066, enable ? 0x0 : 0x66);
+}
+
static void mt6359_set_decoder_clk(struct mt6359_priv *priv, bool enable)
{
regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON13,
@@ -122,6 +154,84 @@ static void mt6359_mtkaif_tx_disable(struct mt6359_priv *priv)
0xff00, 0x3000);
}
+void mt6359_set_mtkaif_protocol(struct snd_soc_component *cmpnt,
+ int mtkaif_protocol)
+{
+ struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
+
+ priv->mtkaif_protocol = mtkaif_protocol;
+}
+EXPORT_SYMBOL_GPL(mt6359_set_mtkaif_protocol);
+
+void mt6359_mtkaif_calibration_enable(struct snd_soc_component *cmpnt)
+{
+ struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
+
+ mt6359_set_playback_gpio(priv);
+ mt6359_set_capture_gpio(priv);
+ mt6359_mtkaif_tx_enable(priv);
+
+ mt6359_set_dcxo(priv, true);
+ mt6359_set_aud_global_bias(priv, true);
+ mt6359_set_clksq(priv, true);
+ mt6359_set_topck(priv, true);
+
+ /* set dat_miso_loopback on */
+ regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
+ RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
+ 1 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
+ regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
+ RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
+ 1 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
+ regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1,
+ RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK_SFT,
+ 1 << RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_SFT);
+}
+EXPORT_SYMBOL_GPL(mt6359_mtkaif_calibration_enable);
+
+void mt6359_mtkaif_calibration_disable(struct snd_soc_component *cmpnt)
+{
+ struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
+
+ /* set dat_miso_loopback off */
+ regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
+ RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
+ 0 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
+ regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
+ RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
+ 0 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
+ regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1,
+ RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK_SFT,
+ 0 << RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_SFT);
+
+ mt6359_set_topck(priv, false);
+ mt6359_set_clksq(priv, false);
+ mt6359_set_aud_global_bias(priv, false);
+ mt6359_set_dcxo(priv, false);
+
+ mt6359_mtkaif_tx_disable(priv);
+ mt6359_reset_playback_gpio(priv);
+ mt6359_reset_capture_gpio(priv);
+}
+EXPORT_SYMBOL_GPL(mt6359_mtkaif_calibration_disable);
+
+void mt6359_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt,
+ int phase_1, int phase_2, int phase_3)
+{
+ struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
+
+ regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
+ RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT,
+ phase_1 << RG_AUD_PAD_TOP_PHASE_MODE_SFT);
+ regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
+ RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT,
+ phase_2 << RG_AUD_PAD_TOP_PHASE_MODE2_SFT);
+ regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1,
+ RG_AUD_PAD_TOP_PHASE_MODE3_MASK_SFT,
+ phase_3 << RG_AUD_PAD_TOP_PHASE_MODE3_SFT);
+}
+EXPORT_SYMBOL_GPL(mt6359_set_mtkaif_calibration_phase);
+
static void zcd_disable(struct mt6359_priv *priv)
{
regmap_write(priv->regmap, MT6359_ZCD_CON0, 0x0000);
diff --git a/sound/soc/codecs/mt6359.h b/sound/soc/codecs/mt6359.h
index 3792e534a91b6..af6f07fbc4fd1 100644
--- a/sound/soc/codecs/mt6359.h
+++ b/sound/soc/codecs/mt6359.h
@@ -2637,4 +2637,11 @@ struct mt6359_priv {
(type) == MIC_TYPE_MUX_DCC_ECM_DIFF || \
(type) == MIC_TYPE_MUX_DCC_ECM_SINGLE)
+void mt6359_set_mtkaif_protocol(struct snd_soc_component *cmpnt,
+ int mtkaif_protocol);
+void mt6359_mtkaif_calibration_enable(struct snd_soc_component *cmpnt);
+void mt6359_mtkaif_calibration_disable(struct snd_soc_component *cmpnt);
+void mt6359_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt,
+ int phase_1, int phase_2, int phase_3);
+
#endif/* end _MT6359_H_ */
--
2.18.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/5] dt-bindings: mediatek: mt8192: add audio afe document
2020-10-02 7:35 [PATCH 0/5] ASoC: Mediatek: Add support for MT8192 SoC Jiaxin Yu
2020-10-02 7:35 ` [PATCH 1/5] ASoC: mediatek: mt6359: add the calibration functions Jiaxin Yu
@ 2020-10-02 7:35 ` Jiaxin Yu
2020-10-05 13:55 ` Rob Herring
2020-10-05 13:57 ` Rob Herring
2020-10-02 7:35 ` [PATCH 4/5] ASoC: mediatek: mt8192: add machine driver with mt6359, rt1015 and rt5682 Jiaxin Yu
` (2 subsequent siblings)
4 siblings, 2 replies; 12+ messages in thread
From: Jiaxin Yu @ 2020-10-02 7:35 UTC (permalink / raw)
To: broonie, tiwai, matthias.bgg, robh+dt, p.zabel, tzungbi,
alsa-devel, linux-arm-kernel, linux-mediatek, devicetree
Cc: shane.chien, kuninori.morimoto.gx, maowenan, Jiaxin Yu
This patch adds mt8192 audio afe document.
Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
---
.../bindings/sound/mt8192-afe-pcm.yaml | 98 +++++++++++++++++++
1 file changed, 98 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
diff --git a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
new file mode 100644
index 0000000000000..43852315f1867
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/mt8192-afe-pcm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek AFE PCM controller for mt8192
+
+maintainers:
+ - Jiaxin Yu <jiaxin.yu@mediatek.com>
+ - Shane Chien <shane.chien@mediatek.com>
+
+properties:
+ compatible:
+ contains:
+ const: mediatek,mt8192-audio
+
+ interrupts:
+ maxItems: 1
+ description: AFE interrupt line
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: audiosys
+
+ apmixedsys:
+ maxItems: 1
+ description: The mediatek apmixedsys controller
+
+ infracfg:
+ maxItems: 1
+ description: The mediatek infracfg controller
+
+ topckgen:
+ maxItems: 1
+ description: The mediatek topckgen controller
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: AFE clock
+ - description: ADDA DAC clock
+ - description: ADDA DAC pre-distortion clock
+ - description: audio infra sys clock
+ - description: audio infra 26M clock
+
+ clock-names:
+ items:
+ - const: aud_afe_clk
+ - const: aud_dac_clk
+ - const: aud_dac_predis_clk
+ - const: aud_infra_clk
+ - const: aud_infra_26m_clk
+
+required:
+ - compatible
+ - interrupts
+ - resets
+ - reset-names
+ - power-domains
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8192-clk.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/mt8192-power.h>
+
+ afe: mt8192-afe-pcm {
+ compatible = "mediatek,mt8192-audio";
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&watchdog MT8192_TOPRGU_AUDIO_SW_RST>;
+ reset-names = "audiosys";
+ apmixedsys = <&apmixedsys>;
+ infracfg = <&infracfg>;
+ topckgen = <&topckgen>;
+ power-domains = <&scpsys MT8192_POWER_DOMAIN_AUDIO>;
+ clocks = <&audsys CLK_AUD_AFE>,
+ <&audsys CLK_AUD_DAC>,
+ <&audsys CLK_AUD_DAC_PREDIS>,
+ <&infracfg CLK_INFRA_AUDIO>,
+ <&infracfg CLK_INFRA_AUDIO_26M_B>;
+ clock-names = "aud_afe_clk",
+ "aud_dac_clk",
+ "aud_dac_predis_clk",
+ "aud_infra_clk",
+ "aud_infra_26m_clk";
+ };
+
+...
--
2.18.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 4/5] ASoC: mediatek: mt8192: add machine driver with mt6359, rt1015 and rt5682
2020-10-02 7:35 [PATCH 0/5] ASoC: Mediatek: Add support for MT8192 SoC Jiaxin Yu
2020-10-02 7:35 ` [PATCH 1/5] ASoC: mediatek: mt6359: add the calibration functions Jiaxin Yu
2020-10-02 7:35 ` [PATCH 3/5] dt-bindings: mediatek: mt8192: add audio afe document Jiaxin Yu
@ 2020-10-02 7:35 ` Jiaxin Yu
2020-10-02 7:35 ` [PATCH 5/5] dt-bindings: mediatek: mt8192: add mt8192-mt6358-rt1015-rt5682 document Jiaxin Yu
[not found] ` <1601624142-18991-3-git-send-email-jiaxin.yu@mediatek.com>
4 siblings, 0 replies; 12+ messages in thread
From: Jiaxin Yu @ 2020-10-02 7:35 UTC (permalink / raw)
To: broonie, tiwai, matthias.bgg, robh+dt, p.zabel, tzungbi,
alsa-devel, linux-arm-kernel, linux-mediatek, devicetree
Cc: shane.chien, kuninori.morimoto.gx, maowenan, Jiaxin Yu
This patch adds support for the machine board with mt6359, rt1015 and rt5682.
Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
---
sound/soc/mediatek/Kconfig | 13 +
sound/soc/mediatek/mt8192/Makefile | 2 +
.../mt8192/mt8192-mt6359-rt1015-rt5682.c | 1058 +++++++++++++++++
3 files changed, 1073 insertions(+)
create mode 100644 sound/soc/mediatek/mt8192/mt8192-mt6359-rt1015-rt5682.c
diff --git a/sound/soc/mediatek/Kconfig b/sound/soc/mediatek/Kconfig
index 10588cf809dc7..dc628fb6c1025 100644
--- a/sound/soc/mediatek/Kconfig
+++ b/sound/soc/mediatek/Kconfig
@@ -167,3 +167,16 @@ config SND_SOC_MT8192
that can be used with other codecs.
Select Y if you have such device.
If unsure select "N".
+
+config SND_SOC_MT8192_MT6359_RT1015_RT5682
+ tristate "ASoC Audio driver for MT8192 with MT6359 RT1015 RT5682 codec"
+ depends on I2C
+ depends on SND_SOC_MT8192
+ select SND_SOC_MT6359
+ select SND_SOC_RT1015
+ select SND_SOC_RT5682_I2C
+ help
+ This adds ASoC driver for Mediatek MT8192 boards
+ with the MT6359 RT1015 RT5682 audio codec.
+ Select Y if you have such device.
+ If unsure select "N".
diff --git a/sound/soc/mediatek/mt8192/Makefile b/sound/soc/mediatek/mt8192/Makefile
index dd18486881708..8b27d82626ea4 100644
--- a/sound/soc/mediatek/mt8192/Makefile
+++ b/sound/soc/mediatek/mt8192/Makefile
@@ -12,3 +12,5 @@ snd-soc-mt8192-afe-objs := \
mt8192-dai-tdm.o
obj-$(CONFIG_SND_SOC_MT8192) += snd-soc-mt8192-afe.o
+obj-$(CONFIG_SND_SOC_MT8192_MT6359_RT1015_RT5682) += \
+ mt8192-mt6359-rt1015-rt5682.o
diff --git a/sound/soc/mediatek/mt8192/mt8192-mt6359-rt1015-rt5682.c b/sound/soc/mediatek/mt8192/mt8192-mt6359-rt1015-rt5682.c
new file mode 100644
index 0000000000000..cd38b0249db43
--- /dev/null
+++ b/sound/soc/mediatek/mt8192/mt8192-mt6359-rt1015-rt5682.c
@@ -0,0 +1,1058 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// mt8192-mt6359-rt1015-rt5682.c --
+// MT8192-MT6359-RT1015-RT6358 ALSA SoC machine driver
+//
+// Copyright (c) 2020 MediaTek Inc.
+// Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
+//
+
+#include <linux/input.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <sound/jack.h>
+#include <sound/pcm_params.h>
+#include <sound/rt5682.h>
+#include <sound/soc.h>
+
+#include "../../codecs/mt6359.h"
+#include "../../codecs/rt1015.h"
+#include "../../codecs/rt5682.h"
+#include "../common/mtk-afe-platform-driver.h"
+#include "mt8192-afe-common.h"
+#include "mt8192-afe-clk.h"
+#include "mt8192-afe-gpio.h"
+
+#define RT1015_CODEC_DAI "rt1015-aif"
+#define RT1015_DEV0_NAME "rt1015.1-0028"
+#define RT1015_DEV1_NAME "rt1015.1-0029"
+
+#define RT5682_CODEC_DAI "rt5682-aif1"
+#define RT5682_DEV0_NAME "rt5682.1-001a"
+
+static struct snd_soc_jack headset_jack;
+
+static const struct snd_soc_dapm_widget
+mt8192_mt6359_rt1015_rt5682_widgets[] = {
+ SND_SOC_DAPM_SPK("Left Spk", NULL),
+ SND_SOC_DAPM_SPK("Right Spk", NULL),
+ SND_SOC_DAPM_HP("Headphone Jack", NULL),
+ SND_SOC_DAPM_MIC("Headset Mic", NULL),
+};
+
+static const struct snd_soc_dapm_route mt8192_mt6359_rt1015_rt5682_routes[] = {
+ /* speaker */
+ { "Left Spk", NULL, "Left SPO" },
+ { "Right Spk", NULL, "Right SPO" },
+ /* headset */
+ { "Headphone Jack", NULL, "HPOL" },
+ { "Headphone Jack", NULL, "HPOR" },
+ { "IN1P", NULL, "Headset Mic" },
+};
+
+static const struct snd_kcontrol_new mt8192_mt6359_rt1015_rt5682_controls[] = {
+ SOC_DAPM_PIN_SWITCH("Left Spk"),
+ SOC_DAPM_PIN_SWITCH("Right Spk"),
+ SOC_DAPM_PIN_SWITCH("Headphone Jack"),
+ SOC_DAPM_PIN_SWITCH("Headset Mic"),
+};
+
+static int mt8192_rt1015_i2s_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_card *card = rtd->card;
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai;
+ unsigned int rate = params_rate(params);
+ unsigned int mclk_fs_ratio = 128;
+ unsigned int mclk_fs = rate * mclk_fs_ratio;
+ int ret, i;
+
+ for_each_rtd_codec_dais(rtd, i, codec_dai) {
+ ret = snd_soc_dai_set_bclk_ratio(codec_dai, 64);
+ if (ret) {
+ dev_err(card->dev, "failed to set bclk ratio\n");
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_pll(codec_dai, 0,
+ RT1015_PLL_S_BCLK,
+ params_rate(params) * 64,
+ params_rate(params) * 256);
+ if (ret) {
+ dev_err(card->dev, "failed to set pll\n");
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai,
+ RT1015_SCLK_S_PLL,
+ params_rate(params) * 256,
+ SND_SOC_CLOCK_IN);
+ if (ret) {
+ dev_err(card->dev, "failed to set sysclk\n");
+ return ret;
+ }
+ }
+
+ return snd_soc_dai_set_sysclk(cpu_dai, 0, mclk_fs, SND_SOC_CLOCK_OUT);
+}
+
+static int mt8192_rt5682_i2s_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_card *card = rtd->card;
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+ unsigned int rate = params_rate(params);
+ unsigned int mclk_fs_ratio = 128;
+ unsigned int mclk_fs = rate * mclk_fs_ratio;
+ int bitwidth;
+ int ret;
+
+ bitwidth = snd_pcm_format_width(params_format(params));
+ if (bitwidth < 0) {
+ dev_err(card->dev, "invalid bit width: %d\n", bitwidth);
+ return bitwidth;
+ }
+
+ ret = snd_soc_dai_set_tdm_slot(codec_dai, 0x00, 0x0, 0x2, bitwidth);
+ if (ret) {
+ dev_err(card->dev, "failed to set tdm slot\n");
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_pll(codec_dai, RT5682_PLL1,
+ RT5682_PLL1_S_BCLK1,
+ params_rate(params) * 64,
+ params_rate(params) * 512);
+ if (ret) {
+ dev_err(card->dev, "failed to set pll\n");
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai,
+ RT5682_SCLK_S_PLL1,
+ params_rate(params) * 512,
+ SND_SOC_CLOCK_IN);
+ if (ret) {
+ dev_err(card->dev, "failed to set sysclk\n");
+ return ret;
+ }
+
+ return snd_soc_dai_set_sysclk(cpu_dai, 0, mclk_fs, SND_SOC_CLOCK_OUT);
+}
+
+static const struct snd_soc_ops mt8192_rt1015_i2s_ops = {
+ .hw_params = mt8192_rt1015_i2s_hw_params,
+};
+
+static const struct snd_soc_ops mt8192_rt5682_i2s_ops = {
+ .hw_params = mt8192_rt5682_i2s_hw_params,
+};
+
+static int mt8192_mt6359_mtkaif_calibration(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_component *cmpnt_afe =
+ snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
+ struct snd_soc_component *cmpnt_codec =
+ asoc_rtd_to_codec(rtd, 0)->component;
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt_afe);
+ struct mt8192_afe_private *afe_priv = afe->platform_priv;
+ int phase;
+ unsigned int monitor;
+ int test_done_1, test_done_2, test_done_3;
+ int cycle_1, cycle_2, cycle_3;
+ int prev_cycle_1, prev_cycle_2, prev_cycle_3;
+ int chosen_phase_1, chosen_phase_2, chosen_phase_3;
+ int counter;
+ int mtkaif_calib_ok;
+
+ dev_info(afe->dev, "%s(), start\n", __func__);
+
+ pm_runtime_get_sync(afe->dev);
+ mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA, 1);
+ mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA, 0);
+ mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA_CH34, 1);
+ mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA_CH34, 0);
+
+ mt6359_mtkaif_calibration_enable(cmpnt_codec);
+
+ /* set clock protocol 2 */
+ regmap_update_bits(afe->regmap, AFE_AUD_PAD_TOP, 0xff, 0x38);
+ regmap_update_bits(afe->regmap, AFE_AUD_PAD_TOP, 0xff, 0x39);
+
+ /* set test type to synchronizer pulse */
+ regmap_update_bits(afe_priv->topckgen,
+ CKSYS_AUD_TOP_CFG, 0xffff, 0x4);
+
+ mtkaif_calib_ok = true;
+ afe_priv->mtkaif_calibration_num_phase = 42; /* mt6359: 0 ~ 42 */
+ afe_priv->mtkaif_chosen_phase[0] = -1;
+ afe_priv->mtkaif_chosen_phase[1] = -1;
+ afe_priv->mtkaif_chosen_phase[2] = -1;
+
+ for (phase = 0;
+ phase <= afe_priv->mtkaif_calibration_num_phase &&
+ mtkaif_calib_ok;
+ phase++) {
+ mt6359_set_mtkaif_calibration_phase(cmpnt_codec,
+ phase, phase, phase);
+
+ regmap_update_bits(afe_priv->topckgen,
+ CKSYS_AUD_TOP_CFG, 0x1, 0x1);
+
+ test_done_1 = 0;
+ test_done_2 = 0;
+ test_done_3 = 0;
+ cycle_1 = -1;
+ cycle_2 = -1;
+ cycle_3 = -1;
+ counter = 0;
+ while (test_done_1 == 0 ||
+ test_done_2 == 0 ||
+ test_done_3 == 0) {
+ regmap_read(afe_priv->topckgen,
+ CKSYS_AUD_TOP_MON, &monitor);
+
+ test_done_1 = (monitor >> 28) & 0x1;
+ test_done_2 = (monitor >> 29) & 0x1;
+ test_done_3 = (monitor >> 30) & 0x1;
+ if (test_done_1 == 1)
+ cycle_1 = monitor & 0xf;
+
+ if (test_done_2 == 1)
+ cycle_2 = (monitor >> 4) & 0xf;
+
+ if (test_done_3 == 1)
+ cycle_3 = (monitor >> 8) & 0xf;
+
+ /* handle if never test done */
+ if (++counter > 10000) {
+ dev_err(afe->dev, "%s(), test fail, cycle_1 %d, cycle_2 %d, cycle_3 %d, monitor 0x%x\n",
+ __func__,
+ cycle_1, cycle_2, cycle_3, monitor);
+ mtkaif_calib_ok = false;
+ break;
+ }
+ }
+
+ if (phase == 0) {
+ prev_cycle_1 = cycle_1;
+ prev_cycle_2 = cycle_2;
+ prev_cycle_3 = cycle_3;
+ }
+
+ if (cycle_1 != prev_cycle_1 &&
+ afe_priv->mtkaif_chosen_phase[0] < 0) {
+ afe_priv->mtkaif_chosen_phase[0] = phase - 1;
+ afe_priv->mtkaif_phase_cycle[0] = prev_cycle_1;
+ }
+
+ if (cycle_2 != prev_cycle_2 &&
+ afe_priv->mtkaif_chosen_phase[1] < 0) {
+ afe_priv->mtkaif_chosen_phase[1] = phase - 1;
+ afe_priv->mtkaif_phase_cycle[1] = prev_cycle_2;
+ }
+
+ if (cycle_3 != prev_cycle_3 &&
+ afe_priv->mtkaif_chosen_phase[2] < 0) {
+ afe_priv->mtkaif_chosen_phase[2] = phase - 1;
+ afe_priv->mtkaif_phase_cycle[2] = prev_cycle_3;
+ }
+
+ regmap_update_bits(afe_priv->topckgen,
+ CKSYS_AUD_TOP_CFG, 0x1, 0x0);
+
+ if (afe_priv->mtkaif_chosen_phase[0] >= 0 &&
+ afe_priv->mtkaif_chosen_phase[1] >= 0 &&
+ afe_priv->mtkaif_chosen_phase[2] >= 0)
+ break;
+ }
+
+ if (afe_priv->mtkaif_chosen_phase[0] < 0)
+ chosen_phase_1 = 0;
+ else
+ chosen_phase_1 = afe_priv->mtkaif_chosen_phase[0];
+
+ if (afe_priv->mtkaif_chosen_phase[1] < 0)
+ chosen_phase_2 = 0;
+ else
+ chosen_phase_2 = afe_priv->mtkaif_chosen_phase[1];
+
+ if (afe_priv->mtkaif_chosen_phase[2] < 0)
+ chosen_phase_3 = 0;
+ else
+ chosen_phase_3 = afe_priv->mtkaif_chosen_phase[2];
+
+ mt6359_set_mtkaif_calibration_phase(cmpnt_codec,
+ chosen_phase_1,
+ chosen_phase_2,
+ chosen_phase_3);
+
+ /* disable rx fifo */
+ regmap_update_bits(afe->regmap, AFE_AUD_PAD_TOP, 0xff, 0x38);
+
+ mt6359_mtkaif_calibration_disable(cmpnt_codec);
+
+ mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA, 1);
+ mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA, 0);
+ mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA_CH34, 1);
+ mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA_CH34, 0);
+ pm_runtime_put(afe->dev);
+
+ dev_info(afe->dev, "%s(), mtkaif_chosen_phase[0/1/2]:%d/%d/%d\n",
+ __func__,
+ afe_priv->mtkaif_chosen_phase[0],
+ afe_priv->mtkaif_chosen_phase[1],
+ afe_priv->mtkaif_chosen_phase[2]);
+
+ return 0;
+}
+
+static int mt8192_mt6359_init(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_component *cmpnt_afe =
+ snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
+ struct snd_soc_component *cmpnt_codec =
+ asoc_rtd_to_codec(rtd, 0)->component;
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt_afe);
+ struct mt8192_afe_private *afe_priv = afe->platform_priv;
+
+ /* set mtkaif protocol */
+ mt6359_set_mtkaif_protocol(cmpnt_codec,
+ MT6359_MTKAIF_PROTOCOL_2_CLK_P2);
+ afe_priv->mtkaif_protocol = MTKAIF_PROTOCOL_2_CLK_P2;
+
+ /* mtkaif calibration */
+ mt8192_mt6359_mtkaif_calibration(rtd);
+
+ return 0;
+}
+
+static int mt8192_rt5682_init(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_component *cmpnt_codec =
+ asoc_rtd_to_codec(rtd, 0)->component;
+ struct snd_soc_jack *jack = &headset_jack;
+ int ret;
+
+ ret = snd_soc_card_jack_new(rtd->card, "Headset Jack",
+ SND_JACK_HEADSET | SND_JACK_BTN_0 |
+ SND_JACK_BTN_1 | SND_JACK_BTN_2 |
+ SND_JACK_BTN_3,
+ jack, NULL, 0);
+ if (ret) {
+ dev_err(rtd->dev, "Headset Jack creation failed: %d\n", ret);
+ return ret;
+ }
+
+ snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
+ snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
+ snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
+ snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
+
+ ret = snd_soc_component_set_jack(cmpnt_codec, jack, NULL);
+ if (ret) {
+ dev_err(rtd->dev, "Headset Jack set failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+};
+
+static int mt8192_i2s_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
+ struct snd_pcm_hw_params *params)
+{
+ /* fix BE i2s format to 32bit, clean param mask first */
+ snd_mask_reset_range(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT),
+ 0, SNDRV_PCM_FORMAT_LAST);
+
+ params_set_format(params, SNDRV_PCM_FORMAT_S24_LE);
+
+ return 0;
+}
+
+static int
+mt8192_mt6359_rt1015_rt5682_capture1_startup(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_component *component =
+ snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
+ int ret;
+
+ static const unsigned int channels[] = {
+ 1, 2, 4
+ };
+ static const struct snd_pcm_hw_constraint_list constraints_channels = {
+ .count = ARRAY_SIZE(channels),
+ .list = channels,
+ .mask = 0,
+ };
+ static const unsigned int rates[] = {
+ 8000, 16000, 32000, 48000, 96000, 192000
+ };
+ static const struct snd_pcm_hw_constraint_list constraints_rates = {
+ .count = ARRAY_SIZE(rates),
+ .list = rates,
+ .mask = 0,
+ };
+
+ struct snd_pcm_runtime *runtime = substream->runtime;
+
+ ret = snd_pcm_hw_constraint_list(runtime, 0,
+ SNDRV_PCM_HW_PARAM_CHANNELS,
+ &constraints_channels);
+ if (ret < 0) {
+ dev_err(afe->dev, "hw_constraint_list channels failed\n");
+ return ret;
+ }
+
+ ret = snd_pcm_hw_constraint_list(runtime, 0,
+ SNDRV_PCM_HW_PARAM_RATE,
+ &constraints_rates);
+ if (ret < 0) {
+ dev_err(afe->dev, "hw_constraint_list rate failed\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct snd_soc_ops mt8192_mt6359_rt1015_rt5682_capture1_ops = {
+ .startup = mt8192_mt6359_rt1015_rt5682_capture1_startup,
+};
+
+/* FE */
+SND_SOC_DAILINK_DEFS(playback1,
+ DAILINK_COMP_ARRAY(COMP_CPU("DL1")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(playback12,
+ DAILINK_COMP_ARRAY(COMP_CPU("DL12")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(playback2,
+ DAILINK_COMP_ARRAY(COMP_CPU("DL2")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(playback3,
+ DAILINK_COMP_ARRAY(COMP_CPU("DL3")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(playback4,
+ DAILINK_COMP_ARRAY(COMP_CPU("DL4")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(playback5,
+ DAILINK_COMP_ARRAY(COMP_CPU("DL5")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(playback6,
+ DAILINK_COMP_ARRAY(COMP_CPU("DL6")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(playback7,
+ DAILINK_COMP_ARRAY(COMP_CPU("DL7")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(playback8,
+ DAILINK_COMP_ARRAY(COMP_CPU("DL8")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(playback9,
+ DAILINK_COMP_ARRAY(COMP_CPU("DL9")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(capture1,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL1")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(capture2,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL2")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(capture3,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL3")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(capture4,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL4")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(capture5,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL5")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(capture6,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL6")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(capture7,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL7")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(capture8,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL8")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(capture_mono1,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL_MONO_1")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(capture_mono2,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL_MONO_2")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(capture_mono3,
+ DAILINK_COMP_ARRAY(COMP_CPU("UL_MONO_3")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(playback_hdmi,
+ DAILINK_COMP_ARRAY(COMP_CPU("HDMI")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+/* BE */
+SND_SOC_DAILINK_DEFS(primary_codec,
+ DAILINK_COMP_ARRAY(COMP_CPU("ADDA")),
+ DAILINK_COMP_ARRAY(COMP_CODEC("mt6359-sound",
+ "mt6359-snd-codec-aif1")),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(primary_codec_ch34,
+ DAILINK_COMP_ARRAY(COMP_CPU("ADDA_CH34")),
+ DAILINK_COMP_ARRAY(COMP_CODEC("mt6359-sound",
+ "mt6359-snd-codec-aif2")),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(ap_dmic,
+ DAILINK_COMP_ARRAY(COMP_CPU("AP_DMIC")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(ap_dmic_ch34,
+ DAILINK_COMP_ARRAY(COMP_CPU("AP_DMIC_CH34")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(i2s0,
+ DAILINK_COMP_ARRAY(COMP_CPU("I2S0")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(i2s1,
+ DAILINK_COMP_ARRAY(COMP_CPU("I2S1")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(i2s2,
+ DAILINK_COMP_ARRAY(COMP_CPU("I2S2")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(i2s3,
+ DAILINK_COMP_ARRAY(COMP_CPU("I2S3")),
+ DAILINK_COMP_ARRAY(COMP_CODEC(RT1015_DEV0_NAME,
+ RT1015_CODEC_DAI),
+ COMP_CODEC(RT1015_DEV1_NAME,
+ RT1015_CODEC_DAI)),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(i2s5,
+ DAILINK_COMP_ARRAY(COMP_CPU("I2S5")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(i2s6,
+ DAILINK_COMP_ARRAY(COMP_CPU("I2S6")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(i2s7,
+ DAILINK_COMP_ARRAY(COMP_CPU("I2S7")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(i2s8,
+ DAILINK_COMP_ARRAY(COMP_CPU("I2S8")),
+ DAILINK_COMP_ARRAY(COMP_CODEC(RT5682_DEV0_NAME,
+ RT5682_CODEC_DAI)),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(i2s9,
+ DAILINK_COMP_ARRAY(COMP_CPU("I2S9")),
+ DAILINK_COMP_ARRAY(COMP_CODEC(RT5682_DEV0_NAME,
+ RT5682_CODEC_DAI)),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(connsys_i2s,
+ DAILINK_COMP_ARRAY(COMP_CPU("CONNSYS_I2S")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(pcm1,
+ DAILINK_COMP_ARRAY(COMP_CPU("PCM 1")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(pcm2,
+ DAILINK_COMP_ARRAY(COMP_CPU("PCM 2")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+SND_SOC_DAILINK_DEFS(tdm,
+ DAILINK_COMP_ARRAY(COMP_CPU("TDM")),
+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
+static struct snd_soc_dai_link mt8192_mt6359_rt1015_rt5682_dai_links[] = {
+ /* Front End DAI links */
+ {
+ .name = "Playback_1",
+ .stream_name = "Playback_1",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .dpcm_playback = 1,
+ SND_SOC_DAILINK_REG(playback1),
+ },
+ {
+ .name = "Playback_12",
+ .stream_name = "Playback_12",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .dpcm_playback = 1,
+ SND_SOC_DAILINK_REG(playback12),
+ },
+ {
+ .name = "Playback_2",
+ .stream_name = "Playback_2",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .dpcm_playback = 1,
+ SND_SOC_DAILINK_REG(playback2),
+ },
+ {
+ .name = "Playback_3",
+ .stream_name = "Playback_3",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .dpcm_playback = 1,
+ SND_SOC_DAILINK_REG(playback3),
+ },
+ {
+ .name = "Playback_4",
+ .stream_name = "Playback_4",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .dpcm_playback = 1,
+ SND_SOC_DAILINK_REG(playback4),
+ },
+ {
+ .name = "Playback_5",
+ .stream_name = "Playback_5",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .dpcm_playback = 1,
+ SND_SOC_DAILINK_REG(playback5),
+ },
+ {
+ .name = "Playback_6",
+ .stream_name = "Playback_6",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .dpcm_playback = 1,
+ SND_SOC_DAILINK_REG(playback6),
+ },
+ {
+ .name = "Playback_7",
+ .stream_name = "Playback_7",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .dpcm_playback = 1,
+ SND_SOC_DAILINK_REG(playback7),
+ },
+ {
+ .name = "Playback_8",
+ .stream_name = "Playback_8",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .dpcm_playback = 1,
+ SND_SOC_DAILINK_REG(playback8),
+ },
+ {
+ .name = "Playback_9",
+ .stream_name = "Playback_9",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .dpcm_playback = 1,
+ SND_SOC_DAILINK_REG(playback9),
+ },
+ {
+ .name = "Capture_1",
+ .stream_name = "Capture_1",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .dpcm_capture = 1,
+ .ops = &mt8192_mt6359_rt1015_rt5682_capture1_ops,
+ SND_SOC_DAILINK_REG(capture1),
+ },
+ {
+ .name = "Capture_2",
+ .stream_name = "Capture_2",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .dpcm_capture = 1,
+ SND_SOC_DAILINK_REG(capture2),
+ },
+ {
+ .name = "Capture_3",
+ .stream_name = "Capture_3",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .dpcm_capture = 1,
+ SND_SOC_DAILINK_REG(capture3),
+ },
+ {
+ .name = "Capture_4",
+ .stream_name = "Capture_4",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .dpcm_capture = 1,
+ SND_SOC_DAILINK_REG(capture4),
+ },
+ {
+ .name = "Capture_5",
+ .stream_name = "Capture_5",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .dpcm_capture = 1,
+ SND_SOC_DAILINK_REG(capture5),
+ },
+ {
+ .name = "Capture_6",
+ .stream_name = "Capture_6",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .dpcm_capture = 1,
+ SND_SOC_DAILINK_REG(capture6),
+ },
+ {
+ .name = "Capture_7",
+ .stream_name = "Capture_7",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .dpcm_capture = 1,
+ SND_SOC_DAILINK_REG(capture7),
+ },
+ {
+ .name = "Capture_8",
+ .stream_name = "Capture_8",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .dpcm_capture = 1,
+ SND_SOC_DAILINK_REG(capture8),
+ },
+ {
+ .name = "Capture_Mono_1",
+ .stream_name = "Capture_Mono_1",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .dpcm_capture = 1,
+ SND_SOC_DAILINK_REG(capture_mono1),
+ },
+ {
+ .name = "Capture_Mono_2",
+ .stream_name = "Capture_Mono_2",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .dpcm_capture = 1,
+ SND_SOC_DAILINK_REG(capture_mono2),
+ },
+ {
+ .name = "Capture_Mono_3",
+ .stream_name = "Capture_Mono_3",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .dpcm_capture = 1,
+ SND_SOC_DAILINK_REG(capture_mono3),
+ },
+ {
+ .name = "playback_hdmi",
+ .stream_name = "Playback_HDMI",
+ .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
+ SND_SOC_DPCM_TRIGGER_PRE},
+ .dynamic = 1,
+ .dpcm_playback = 1,
+ SND_SOC_DAILINK_REG(playback_hdmi),
+ },
+ /* Back End DAI links */
+ {
+ .name = "Primary Codec",
+ .no_pcm = 1,
+ .dpcm_playback = 1,
+ .dpcm_capture = 1,
+ .ignore_suspend = 1,
+ .init = mt8192_mt6359_init,
+ SND_SOC_DAILINK_REG(primary_codec),
+ },
+ {
+ .name = "Primary Codec CH34",
+ .no_pcm = 1,
+ .dpcm_playback = 1,
+ .dpcm_capture = 1,
+ .ignore_suspend = 1,
+ SND_SOC_DAILINK_REG(primary_codec_ch34),
+ },
+ {
+ .name = "AP_DMIC",
+ .no_pcm = 1,
+ .dpcm_capture = 1,
+ .ignore_suspend = 1,
+ SND_SOC_DAILINK_REG(ap_dmic),
+ },
+ {
+ .name = "AP_DMIC_CH34",
+ .no_pcm = 1,
+ .dpcm_capture = 1,
+ .ignore_suspend = 1,
+ SND_SOC_DAILINK_REG(ap_dmic_ch34),
+ },
+ {
+ .name = "I2S0",
+ .no_pcm = 1,
+ .dpcm_capture = 1,
+ .ignore_suspend = 1,
+ .be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
+ SND_SOC_DAILINK_REG(i2s0),
+ },
+ {
+ .name = "I2S1",
+ .no_pcm = 1,
+ .dpcm_playback = 1,
+ .ignore_suspend = 1,
+ .be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
+ SND_SOC_DAILINK_REG(i2s1),
+ },
+ {
+ .name = "I2S2",
+ .no_pcm = 1,
+ .dpcm_capture = 1,
+ .ignore_suspend = 1,
+ .be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
+ SND_SOC_DAILINK_REG(i2s2),
+ },
+ {
+ .name = "I2S3",
+ .no_pcm = 1,
+ .dpcm_playback = 1,
+ .ignore_suspend = 1,
+ .be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
+ SND_SOC_DAILINK_REG(i2s3),
+ .ops = &mt8192_rt1015_i2s_ops,
+ },
+ {
+ .name = "I2S5",
+ .no_pcm = 1,
+ .dpcm_playback = 1,
+ .ignore_suspend = 1,
+ .be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
+ SND_SOC_DAILINK_REG(i2s5),
+ },
+ {
+ .name = "I2S6",
+ .no_pcm = 1,
+ .dpcm_capture = 1,
+ .ignore_suspend = 1,
+ .be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
+ SND_SOC_DAILINK_REG(i2s6),
+ },
+ {
+ .name = "I2S7",
+ .no_pcm = 1,
+ .dpcm_playback = 1,
+ .ignore_suspend = 1,
+ .be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
+ SND_SOC_DAILINK_REG(i2s7),
+ },
+ {
+ .name = "I2S8",
+ .no_pcm = 1,
+ .dpcm_capture = 1,
+ .ignore_suspend = 1,
+ .init = mt8192_rt5682_init,
+ .be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
+ SND_SOC_DAILINK_REG(i2s8),
+ .ops = &mt8192_rt5682_i2s_ops,
+ },
+ {
+ .name = "I2S9",
+ .no_pcm = 1,
+ .dpcm_playback = 1,
+ .ignore_suspend = 1,
+ .be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
+ SND_SOC_DAILINK_REG(i2s9),
+ .ops = &mt8192_rt5682_i2s_ops,
+ },
+ {
+ .name = "CONNSYS_I2S",
+ .no_pcm = 1,
+ .dpcm_capture = 1,
+ .ignore_suspend = 1,
+ SND_SOC_DAILINK_REG(connsys_i2s),
+ },
+ {
+ .name = "PCM 1",
+ .no_pcm = 1,
+ .dpcm_playback = 1,
+ .dpcm_capture = 1,
+ .ignore_suspend = 1,
+ SND_SOC_DAILINK_REG(pcm1),
+ },
+ {
+ .name = "PCM 2",
+ .no_pcm = 1,
+ .dpcm_playback = 1,
+ .dpcm_capture = 1,
+ .ignore_suspend = 1,
+ SND_SOC_DAILINK_REG(pcm2),
+ },
+ {
+ .name = "TDM",
+ .no_pcm = 1,
+ .dpcm_playback = 1,
+ .ignore_suspend = 1,
+ SND_SOC_DAILINK_REG(tdm),
+ },
+};
+
+static struct snd_soc_codec_conf rt1015_amp_conf[] = {
+ {
+ .dlc = COMP_CODEC_CONF(RT1015_DEV0_NAME),
+ .name_prefix = "Left",
+ },
+ {
+ .dlc = COMP_CODEC_CONF(RT1015_DEV1_NAME),
+ .name_prefix = "Right",
+ },
+};
+
+static struct snd_soc_card mt8192_mt6359_rt1015_rt5682_soc_card = {
+ .name = "mt8192_mt6359_rt1015_rt5682",
+ .owner = THIS_MODULE,
+ .dai_link = mt8192_mt6359_rt1015_rt5682_dai_links,
+ .num_links = ARRAY_SIZE(mt8192_mt6359_rt1015_rt5682_dai_links),
+ .controls = mt8192_mt6359_rt1015_rt5682_controls,
+ .num_controls = ARRAY_SIZE(mt8192_mt6359_rt1015_rt5682_controls),
+ .dapm_widgets = mt8192_mt6359_rt1015_rt5682_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(mt8192_mt6359_rt1015_rt5682_widgets),
+ .dapm_routes = mt8192_mt6359_rt1015_rt5682_routes,
+ .num_dapm_routes = ARRAY_SIZE(mt8192_mt6359_rt1015_rt5682_routes),
+ .codec_conf = rt1015_amp_conf,
+ .num_configs = ARRAY_SIZE(rt1015_amp_conf),
+};
+
+static int mt8192_mt6359_rt1015_rt5682_dev_probe(struct platform_device *pdev)
+{
+ struct snd_soc_card *card = &mt8192_mt6359_rt1015_rt5682_soc_card;
+ struct device_node *platform_node;
+ int ret, i;
+ struct snd_soc_dai_link *dai_link;
+
+ card->dev = &pdev->dev;
+
+ platform_node = of_parse_phandle(pdev->dev.of_node,
+ "mediatek,platform", 0);
+ if (!platform_node) {
+ dev_err(&pdev->dev, "Property 'platform' missing or invalid\n");
+ return -EINVAL;
+ }
+
+ for_each_card_prelinks(card, i, dai_link) {
+ if (!dai_link->platforms->name)
+ dai_link->platforms->of_node = platform_node;
+ }
+
+ ret = mt8192_afe_gpio_init(&pdev->dev);
+ if (ret) {
+ dev_err(&pdev->dev, "init gpio error %d\n", ret);
+ return ret;
+ }
+
+ return devm_snd_soc_register_card(&pdev->dev, card);
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id mt8192_mt6359_rt1015_rt5682_dt_match[] = {
+ {.compatible = "mediatek,mt8192_mt6359_rt1015_rt5682",},
+ {}
+};
+#endif
+
+static const struct dev_pm_ops mt8192_mt6359_rt1015_rt5682_pm_ops = {
+ .poweroff = snd_soc_poweroff,
+ .restore = snd_soc_resume,
+};
+
+static struct platform_driver mt8192_mt6359_rt1015_rt5682_driver = {
+ .driver = {
+ .name = "mt8192_mt6359_rt1015_rt5682",
+#ifdef CONFIG_OF
+ .of_match_table = mt8192_mt6359_rt1015_rt5682_dt_match,
+#endif
+ .pm = &mt8192_mt6359_rt1015_rt5682_pm_ops,
+ },
+ .probe = mt8192_mt6359_rt1015_rt5682_dev_probe,
+};
+
+module_platform_driver(mt8192_mt6359_rt1015_rt5682_driver);
+
+/* Module information */
+MODULE_DESCRIPTION("MT8192-MT6359-RT1015-RT5682 ALSA SoC machine driver");
+MODULE_AUTHOR("Jiaxin Yu <jiaxin.yu@mediatek.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("mt8192_mt6359_rt1015_rt5682 soc card");
--
2.18.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 5/5] dt-bindings: mediatek: mt8192: add mt8192-mt6358-rt1015-rt5682 document
2020-10-02 7:35 [PATCH 0/5] ASoC: Mediatek: Add support for MT8192 SoC Jiaxin Yu
` (2 preceding siblings ...)
2020-10-02 7:35 ` [PATCH 4/5] ASoC: mediatek: mt8192: add machine driver with mt6359, rt1015 and rt5682 Jiaxin Yu
@ 2020-10-02 7:35 ` Jiaxin Yu
2020-10-06 20:43 ` Rob Herring
[not found] ` <1601624142-18991-3-git-send-email-jiaxin.yu@mediatek.com>
4 siblings, 1 reply; 12+ messages in thread
From: Jiaxin Yu @ 2020-10-02 7:35 UTC (permalink / raw)
To: broonie, tiwai, matthias.bgg, robh+dt, p.zabel, tzungbi,
alsa-devel, linux-arm-kernel, linux-mediatek, devicetree
Cc: shane.chien, kuninori.morimoto.gx, maowenan, Jiaxin Yu
This patch adds document for the machine board with mt6358, rt1015 and rt5682.
Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
---
.../sound/mt8192-mt6359-rt1015-rt5682.yaml | 44 +++++++++++++++++++
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/mt8192-mt6359-rt1015-rt5682.yaml
diff --git a/Documentation/devicetree/bindings/sound/mt8192-mt6359-rt1015-rt5682.yaml b/Documentation/devicetree/bindings/sound/mt8192-mt6359-rt1015-rt5682.yaml
new file mode 100644
index 0000000000000..dff5004cd0368
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/mt8192-mt6359-rt1015-rt5682.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/mt8192-mt6359-rt1015-rt5682.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek MT8192 with MT6359, RT1015 and RT5682 ASoC sound card driver
+
+maintainers:
+ - Jiaxin Yu <jiaxin.yu@mediatek.com>
+ - Shane Chien <shane.chien@mediatek.com>
+
+description:
+ This binding describes the MT8192 sound card.
+
+properties:
+ compatible:
+ contains:
+ const: mediatek,mt8192_mt6359_rt1015_rt5682
+
+ mediatek,platform:
+ $ref: "/schemas/types.yaml#/definitions/phandle"
+ description: |
+ The DT/OF node which is used to specify the link's platform driver.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - mediatek,platform
+
+examples:
+ - |
+
+ sound: mt8192-sound {
+ compatible = "mediatek,mt8192-mt6359-rt1015-rt5682";
+ mediatek,platform = <&afe>;
+ pinctrl-names = "aud_clk_mosi_off",
+ "aud_clk_mosi_on";
+ pinctrl-0 = <&aud_clk_mosi_off>;
+ pinctrl-1 = <&aud_clk_mosi_on>;
+ };
+
+...
--
2.18.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 2/5] ASoC: mediatek: mt8192: add platform driver
[not found] ` <1601624142-18991-3-git-send-email-jiaxin.yu@mediatek.com>
@ 2020-10-02 7:59 ` Philipp Zabel
0 siblings, 0 replies; 12+ messages in thread
From: Philipp Zabel @ 2020-10-02 7:59 UTC (permalink / raw)
To: Jiaxin Yu, broonie, tiwai, matthias.bgg, robh+dt, tzungbi,
alsa-devel, linux-arm-kernel, linux-mediatek, devicetree
Cc: shane.chien, kuninori.morimoto.gx, maowenan
Hi Jiaxin,
On Fri, 2020-10-02 at 15:35 +0800, Jiaxin Yu wrote:
> +static int mt8192_afe_pcm_dev_probe(struct platform_device *pdev)
> +{
[...]
> + /* reset controller to reset audio regs before regmap cache */
> + rstc = devm_reset_control_get(dev, "audiosys");
Please use devm_reset_control_get_exclusive() instead.
regards
Philipp
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/5] dt-bindings: mediatek: mt8192: add audio afe document
2020-10-02 7:35 ` [PATCH 3/5] dt-bindings: mediatek: mt8192: add audio afe document Jiaxin Yu
@ 2020-10-05 13:55 ` Rob Herring
2020-10-12 5:47 ` Jiaxin Yu
2020-10-05 13:57 ` Rob Herring
1 sibling, 1 reply; 12+ messages in thread
From: Rob Herring @ 2020-10-05 13:55 UTC (permalink / raw)
To: Jiaxin Yu
Cc: linux-mediatek, linux-arm-kernel, shane.chien, robh+dt, maowenan,
matthias.bgg, p.zabel, broonie, alsa-devel, kuninori.morimoto.gx,
devicetree, tiwai, tzungbi
On Fri, 02 Oct 2020 15:35:40 +0800, Jiaxin Yu wrote:
> This patch adds mt8192 audio afe document.
>
> Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
> ---
> .../bindings/sound/mt8192-afe-pcm.yaml | 98 +++++++++++++++++++
> 1 file changed, 98 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
Documentation/devicetree/bindings/sound/mt8192-afe-pcm.example.dts:19:18: fatal error: dt-bindings/clock/mt8192-clk.h: No such file or directory
19 | #include <dt-bindings/clock/mt8192-clk.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:342: Documentation/devicetree/bindings/sound/mt8192-afe-pcm.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1366: dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1375582
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure dt-schema is up to date:
pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/5] dt-bindings: mediatek: mt8192: add audio afe document
2020-10-02 7:35 ` [PATCH 3/5] dt-bindings: mediatek: mt8192: add audio afe document Jiaxin Yu
2020-10-05 13:55 ` Rob Herring
@ 2020-10-05 13:57 ` Rob Herring
2020-10-12 5:56 ` Jiaxin Yu
1 sibling, 1 reply; 12+ messages in thread
From: Rob Herring @ 2020-10-05 13:57 UTC (permalink / raw)
To: Jiaxin Yu
Cc: broonie, tiwai, matthias.bgg, p.zabel, tzungbi, alsa-devel,
linux-arm-kernel, linux-mediatek, devicetree, shane.chien,
kuninori.morimoto.gx, maowenan
On Fri, Oct 02, 2020 at 03:35:40PM +0800, Jiaxin Yu wrote:
> This patch adds mt8192 audio afe document.
>
> Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
> ---
> .../bindings/sound/mt8192-afe-pcm.yaml | 98 +++++++++++++++++++
> 1 file changed, 98 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
>
> diff --git a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> new file mode 100644
> index 0000000000000..43852315f1867
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> @@ -0,0 +1,98 @@
> +# SPDX-License-Identifier: GPL-2.0
Dual license new bindings:
(GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/sound/mt8192-afe-pcm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek AFE PCM controller for mt8192
> +
> +maintainers:
> + - Jiaxin Yu <jiaxin.yu@mediatek.com>
> + - Shane Chien <shane.chien@mediatek.com>
> +
> +properties:
> + compatible:
> + contains:
So any other string in addition is okay?
> + const: mediatek,mt8192-audio
> +
> + interrupts:
> + maxItems: 1
> + description: AFE interrupt line
Drop description.
> +
> + resets:
> + maxItems: 1
> +
> + reset-names:
> + const: audiosys
> +
> + apmixedsys:
> + maxItems: 1
This is an array?
> + description: The mediatek apmixedsys controller
> +
> + infracfg:
> + maxItems: 1
> + description: The mediatek infracfg controller
> +
> + topckgen:
> + maxItems: 1
> + description: The mediatek topckgen controller
These all need a type reference and and vendor prefix.
> +
> + power-domains:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: AFE clock
> + - description: ADDA DAC clock
> + - description: ADDA DAC pre-distortion clock
> + - description: audio infra sys clock
> + - description: audio infra 26M clock
> +
> + clock-names:
> + items:
> + - const: aud_afe_clk
> + - const: aud_dac_clk
> + - const: aud_dac_predis_clk
> + - const: aud_infra_clk
> + - const: aud_infra_26m_clk
> +
> +required:
> + - compatible
> + - interrupts
> + - resets
> + - reset-names
> + - power-domains
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8192-clk.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/mt8192-power.h>
> +
> + afe: mt8192-afe-pcm {
> + compatible = "mediatek,mt8192-audio";
> + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
> + resets = <&watchdog MT8192_TOPRGU_AUDIO_SW_RST>;
> + reset-names = "audiosys";
> + apmixedsys = <&apmixedsys>;
> + infracfg = <&infracfg>;
> + topckgen = <&topckgen>;
> + power-domains = <&scpsys MT8192_POWER_DOMAIN_AUDIO>;
> + clocks = <&audsys CLK_AUD_AFE>,
> + <&audsys CLK_AUD_DAC>,
> + <&audsys CLK_AUD_DAC_PREDIS>,
> + <&infracfg CLK_INFRA_AUDIO>,
> + <&infracfg CLK_INFRA_AUDIO_26M_B>;
> + clock-names = "aud_afe_clk",
> + "aud_dac_clk",
> + "aud_dac_predis_clk",
> + "aud_infra_clk",
> + "aud_infra_26m_clk";
> + };
> +
> +...
> --
> 2.18.0
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 5/5] dt-bindings: mediatek: mt8192: add mt8192-mt6358-rt1015-rt5682 document
2020-10-02 7:35 ` [PATCH 5/5] dt-bindings: mediatek: mt8192: add mt8192-mt6358-rt1015-rt5682 document Jiaxin Yu
@ 2020-10-06 20:43 ` Rob Herring
2020-10-12 6:20 ` Jiaxin Yu
0 siblings, 1 reply; 12+ messages in thread
From: Rob Herring @ 2020-10-06 20:43 UTC (permalink / raw)
To: Jiaxin Yu
Cc: broonie, tiwai, matthias.bgg, p.zabel, tzungbi, alsa-devel,
linux-arm-kernel, linux-mediatek, devicetree, shane.chien,
kuninori.morimoto.gx, maowenan
On Fri, Oct 02, 2020 at 03:35:42PM +0800, Jiaxin Yu wrote:
> This patch adds document for the machine board with mt6358, rt1015 and rt5682.
>
> Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
> ---
> .../sound/mt8192-mt6359-rt1015-rt5682.yaml | 44 +++++++++++++++++++
> 1 file changed, 44 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/sound/mt8192-mt6359-rt1015-rt5682.yaml
>
> diff --git a/Documentation/devicetree/bindings/sound/mt8192-mt6359-rt1015-rt5682.yaml b/Documentation/devicetree/bindings/sound/mt8192-mt6359-rt1015-rt5682.yaml
> new file mode 100644
> index 0000000000000..dff5004cd0368
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/mt8192-mt6359-rt1015-rt5682.yaml
> @@ -0,0 +1,44 @@
> +# SPDX-License-Identifier: GPL-2.0
Dual license new bindings:
(GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/sound/mt8192-mt6359-rt1015-rt5682.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek MT8192 with MT6359, RT1015 and RT5682 ASoC sound card driver
> +
> +maintainers:
> + - Jiaxin Yu <jiaxin.yu@mediatek.com>
> + - Shane Chien <shane.chien@mediatek.com>
> +
> +description:
> + This binding describes the MT8192 sound card.
> +
> +properties:
> + compatible:
> + contains:
Drop this. Other strings shouldn't be allowed.
> + const: mediatek,mt8192_mt6359_rt1015_rt5682
Just a list of part numbers? A different codec would be a different
compatible and driver? You should have a link to the codec and you can
read it's compatible to get what codec you have.
> +
> + mediatek,platform:
> + $ref: "/schemas/types.yaml#/definitions/phandle"
> + description: |
> + The DT/OF node which is used to specify the link's platform driver.
What's "link's platform driver"? A DT doesn't have drivers.
> +
> +additionalProperties: false
> +
> +required:
> + - compatible
> + - mediatek,platform
> +
> +examples:
> + - |
> +
> + sound: mt8192-sound {
> + compatible = "mediatek,mt8192-mt6359-rt1015-rt5682";
> + mediatek,platform = <&afe>;
> + pinctrl-names = "aud_clk_mosi_off",
> + "aud_clk_mosi_on";
> + pinctrl-0 = <&aud_clk_mosi_off>;
> + pinctrl-1 = <&aud_clk_mosi_on>;
> + };
> +
> +...
> --
> 2.18.0
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/5] dt-bindings: mediatek: mt8192: add audio afe document
2020-10-05 13:55 ` Rob Herring
@ 2020-10-12 5:47 ` Jiaxin Yu
0 siblings, 0 replies; 12+ messages in thread
From: Jiaxin Yu @ 2020-10-12 5:47 UTC (permalink / raw)
To: Rob Herring
Cc: linux-mediatek, linux-arm-kernel, shane.chien, robh+dt, maowenan,
matthias.bgg, p.zabel, broonie, alsa-devel, kuninori.morimoto.gx,
devicetree, tiwai, tzungbi
On Mon, 2020-10-05 at 08:55 -0500, Rob Herring wrote:
> On Fri, 02 Oct 2020 15:35:40 +0800, Jiaxin Yu wrote:
> > This patch adds mt8192 audio afe document.
> >
> > Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
> > ---
> > .../bindings/sound/mt8192-afe-pcm.yaml | 98 +++++++++++++++++++
> > 1 file changed, 98 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> >
>
>
> My bot found errors running 'make dt_binding_check' on your patch:
>
> Documentation/devicetree/bindings/sound/mt8192-afe-pcm.example.dts:19:18: fatal error: dt-bindings/clock/mt8192-clk.h: No such file or directory
> 19 | #include <dt-bindings/clock/mt8192-clk.h>
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> compilation terminated.
> make[1]: *** [scripts/Makefile.lib:342: Documentation/devicetree/bindings/sound/mt8192-afe-pcm.example.dt.yaml] Error 1
> make[1]: *** Waiting for unfinished jobs....
> make: *** [Makefile:1366: dt_binding_check] Error 2
>
>
> See https://patchwork.ozlabs.org/patch/1375582
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure dt-schema is up to date:
>
> pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade
>
> Please check and re-submit.
>
Sorry, I should add a dependency description.
"dt-bindings/clock/mt8192-clk.h" is included in
https://patchwork.kernel.org/cover/11752231 series of patches, but they
has not been accepted.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/5] dt-bindings: mediatek: mt8192: add audio afe document
2020-10-05 13:57 ` Rob Herring
@ 2020-10-12 5:56 ` Jiaxin Yu
0 siblings, 0 replies; 12+ messages in thread
From: Jiaxin Yu @ 2020-10-12 5:56 UTC (permalink / raw)
To: Rob Herring
Cc: broonie, tiwai, matthias.bgg, p.zabel, tzungbi, alsa-devel,
linux-arm-kernel, linux-mediatek, devicetree, shane.chien,
kuninori.morimoto.gx, maowenan
On Mon, 2020-10-05 at 08:57 -0500, Rob Herring wrote:
> On Fri, Oct 02, 2020 at 03:35:40PM +0800, Jiaxin Yu wrote:
> > This patch adds mt8192 audio afe document.
> >
> > Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
> > ---
> > .../bindings/sound/mt8192-afe-pcm.yaml | 98 +++++++++++++++++++
> > 1 file changed, 98 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> > new file mode 100644
> > index 0000000000000..43852315f1867
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> > @@ -0,0 +1,98 @@
> > +# SPDX-License-Identifier: GPL-2.0
>
> Dual license new bindings:
>
> (GPL-2.0-only OR BSD-2-Clause)
>
Ok, got it.
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/sound/mt8192-afe-pcm.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek AFE PCM controller for mt8192
> > +
> > +maintainers:
> > + - Jiaxin Yu <jiaxin.yu@mediatek.com>
> > + - Shane Chien <shane.chien@mediatek.com>
> > +
> > +properties:
> > + compatible:
> > + contains:
>
> So any other string in addition is okay?
>
No, there will be no other string. So do I need to remove "contains"?
> > + const: mediatek,mt8192-audio
> > +
> > + interrupts:
> > + maxItems: 1
> > + description: AFE interrupt line
>
> Drop description.
>
Ok.
> > +
> > + resets:
> > + maxItems: 1
> > +
> > + reset-names:
> > + const: audiosys
> > +
> > + apmixedsys:
> > + maxItems: 1
>
> This is an array?
>
No, it is just a phandle to the mediatek apmixedsys controller.
> > + description: The mediatek apmixedsys controller
> > +
> > + infracfg:
> > + maxItems: 1
> > + description: The mediatek infracfg controller
> > +
> > + topckgen:
> > + maxItems: 1
> > + description: The mediatek topckgen controller
>
> These all need a type reference and and vendor prefix.
>
Should I change it to the following?
mediatek,topckgen:
$ref: "/schemas/types.yaml#/definitions/phandle"
maxItems: 1
description: The phandle of the mediatek topckgen controller
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: AFE clock
> > + - description: ADDA DAC clock
> > + - description: ADDA DAC pre-distortion clock
> > + - description: audio infra sys clock
> > + - description: audio infra 26M clock
> > +
> > + clock-names:
> > + items:
> > + - const: aud_afe_clk
> > + - const: aud_dac_clk
> > + - const: aud_dac_predis_clk
> > + - const: aud_infra_clk
> > + - const: aud_infra_26m_clk
> > +
> > +required:
> > + - compatible
> > + - interrupts
> > + - resets
> > + - reset-names
> > + - power-domains
> > + - clocks
> > + - clock-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8192-clk.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/power/mt8192-power.h>
> > +
> > + afe: mt8192-afe-pcm {
> > + compatible = "mediatek,mt8192-audio";
> > + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
> > + resets = <&watchdog MT8192_TOPRGU_AUDIO_SW_RST>;
> > + reset-names = "audiosys";
> > + apmixedsys = <&apmixedsys>;
> > + infracfg = <&infracfg>;
> > + topckgen = <&topckgen>;
> > + power-domains = <&scpsys MT8192_POWER_DOMAIN_AUDIO>;
> > + clocks = <&audsys CLK_AUD_AFE>,
> > + <&audsys CLK_AUD_DAC>,
> > + <&audsys CLK_AUD_DAC_PREDIS>,
> > + <&infracfg CLK_INFRA_AUDIO>,
> > + <&infracfg CLK_INFRA_AUDIO_26M_B>;
> > + clock-names = "aud_afe_clk",
> > + "aud_dac_clk",
> > + "aud_dac_predis_clk",
> > + "aud_infra_clk",
> > + "aud_infra_26m_clk";
> > + };
> > +
> > +...
> > --
> > 2.18.0
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 5/5] dt-bindings: mediatek: mt8192: add mt8192-mt6358-rt1015-rt5682 document
2020-10-06 20:43 ` Rob Herring
@ 2020-10-12 6:20 ` Jiaxin Yu
0 siblings, 0 replies; 12+ messages in thread
From: Jiaxin Yu @ 2020-10-12 6:20 UTC (permalink / raw)
To: Rob Herring
Cc: broonie, tiwai, matthias.bgg, p.zabel, tzungbi, alsa-devel,
linux-arm-kernel, linux-mediatek, devicetree, shane.chien,
kuninori.morimoto.gx, maowenan
On Tue, 2020-10-06 at 15:43 -0500, Rob Herring wrote:
> On Fri, Oct 02, 2020 at 03:35:42PM +0800, Jiaxin Yu wrote:
> > This patch adds document for the machine board with mt6358, rt1015 and rt5682.
> >
> > Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
> > ---
> > .../sound/mt8192-mt6359-rt1015-rt5682.yaml | 44 +++++++++++++++++++
> > 1 file changed, 44 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/sound/mt8192-mt6359-rt1015-rt5682.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/sound/mt8192-mt6359-rt1015-rt5682.yaml b/Documentation/devicetree/bindings/sound/mt8192-mt6359-rt1015-rt5682.yaml
> > new file mode 100644
> > index 0000000000000..dff5004cd0368
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/sound/mt8192-mt6359-rt1015-rt5682.yaml
> > @@ -0,0 +1,44 @@
> > +# SPDX-License-Identifier: GPL-2.0
>
> Dual license new bindings:
>
> (GPL-2.0-only OR BSD-2-Clause)
>
Ok, got it.
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/sound/mt8192-mt6359-rt1015-rt5682.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek MT8192 with MT6359, RT1015 and RT5682 ASoC sound card driver
> > +
> > +maintainers:
> > + - Jiaxin Yu <jiaxin.yu@mediatek.com>
> > + - Shane Chien <shane.chien@mediatek.com>
> > +
> > +description:
> > + This binding describes the MT8192 sound card.
> > +
> > +properties:
> > + compatible:
> > + contains:
>
> Drop this. Other strings shouldn't be allowed.
>
Should I need to remove "contains"?
> > + const: mediatek,mt8192_mt6359_rt1015_rt5682
>
> Just a list of part numbers? A different codec would be a different
> compatible and driver? You should have a link to the codec and you can
> read it's compatible to get what codec you have.
>
THis bindings is dedicated to the mt8192 with mt6359, rt1015 and rt5682.
We are not ready to configure dai-link in DTS. Is this mandatory now?
> > +
> > + mediatek,platform:
> > + $ref: "/schemas/types.yaml#/definitions/phandle"
> > + description: |
> > + The DT/OF node which is used to specify the link's platform driver.
>
> What's "link's platform driver"? A DT doesn't have drivers.
>
There's something wrong with my description. "mediatek,platform" is the
phandle of MT8192 ASoC platform.
> > +
> > +additionalProperties: false
> > +
> > +required:
> > + - compatible
> > + - mediatek,platform
> > +
> > +examples:
> > + - |
> > +
> > + sound: mt8192-sound {
> > + compatible = "mediatek,mt8192-mt6359-rt1015-rt5682";
> > + mediatek,platform = <&afe>;
> > + pinctrl-names = "aud_clk_mosi_off",
> > + "aud_clk_mosi_on";
> > + pinctrl-0 = <&aud_clk_mosi_off>;
> > + pinctrl-1 = <&aud_clk_mosi_on>;
> > + };
> > +
> > +...
> > --
> > 2.18.0
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2020-10-12 6:21 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-02 7:35 [PATCH 0/5] ASoC: Mediatek: Add support for MT8192 SoC Jiaxin Yu
2020-10-02 7:35 ` [PATCH 1/5] ASoC: mediatek: mt6359: add the calibration functions Jiaxin Yu
2020-10-02 7:35 ` [PATCH 3/5] dt-bindings: mediatek: mt8192: add audio afe document Jiaxin Yu
2020-10-05 13:55 ` Rob Herring
2020-10-12 5:47 ` Jiaxin Yu
2020-10-05 13:57 ` Rob Herring
2020-10-12 5:56 ` Jiaxin Yu
2020-10-02 7:35 ` [PATCH 4/5] ASoC: mediatek: mt8192: add machine driver with mt6359, rt1015 and rt5682 Jiaxin Yu
2020-10-02 7:35 ` [PATCH 5/5] dt-bindings: mediatek: mt8192: add mt8192-mt6358-rt1015-rt5682 document Jiaxin Yu
2020-10-06 20:43 ` Rob Herring
2020-10-12 6:20 ` Jiaxin Yu
[not found] ` <1601624142-18991-3-git-send-email-jiaxin.yu@mediatek.com>
2020-10-02 7:59 ` [PATCH 2/5] ASoC: mediatek: mt8192: add platform driver Philipp Zabel
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