* [PATCH v3 01/11] dt-bindings: usb: generic-ohci: Document dr_mode property
[not found] <20210630073013.22415-1-biju.das.jz@bp.renesas.com>
@ 2021-06-30 7:30 ` Biju Das
2021-07-14 21:16 ` Rob Herring
2021-06-30 7:30 ` [PATCH v3 02/11] dt-bindings: usb: generic-ehci: " Biju Das
` (5 subsequent siblings)
6 siblings, 1 reply; 18+ messages in thread
From: Biju Das @ 2021-06-30 7:30 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Greg Kroah-Hartman, linux-usb, devicetree,
Geert Uytterhoeven, Yoshihiro Shimoda, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Document the optional property dr_mode present on both RZ/G2 and
R-Car Gen3 SoCs.
It fixes the dtbs_check warning,
'dr_mode' does not match any of the regexes: 'pinctrl-[0-9]+'
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2->v3:
* Dropped RZ/G2L SoC and USBPHY control IP is modelled as reset binding.
v2:
* New patch
---
Documentation/devicetree/bindings/usb/generic-ohci.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
index 0f5f6ea702d0..569777a76c90 100644
--- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
@@ -109,6 +109,11 @@ properties:
iommus:
maxItems: 1
+ dr_mode:
+ enum:
+ - host
+ - otg
+
required:
- compatible
- reg
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 02/11] dt-bindings: usb: generic-ehci: Document dr_mode property
[not found] <20210630073013.22415-1-biju.das.jz@bp.renesas.com>
2021-06-30 7:30 ` [PATCH v3 01/11] dt-bindings: usb: generic-ohci: Document dr_mode property Biju Das
@ 2021-06-30 7:30 ` Biju Das
2021-07-14 21:16 ` Rob Herring
2021-06-30 7:30 ` [PATCH v3 03/11] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings Biju Das
` (4 subsequent siblings)
6 siblings, 1 reply; 18+ messages in thread
From: Biju Das @ 2021-06-30 7:30 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Greg Kroah-Hartman, linux-usb, devicetree,
Geert Uytterhoeven, Yoshihiro Shimoda, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Document the optional property dr_mode present on both RZ/G2 and
R-Car Gen3 SoCs.
It fixes dtbs_check warning,
'dr_mode' does not match any of the regexes: 'pinctrl-[0-9]+'
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2->v3:
* Dropped RZ/G2L SoC and USBPHY control IP is modelled as reset binding.
v2:
* New patch
---
Documentation/devicetree/bindings/usb/generic-ehci.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
index 8089dc956ba3..f6e5e4abb85b 100644
--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
@@ -142,6 +142,11 @@ properties:
iommus:
maxItems: 1
+ dr_mode:
+ enum:
+ - host
+ - otg
+
required:
- compatible
- reg
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 03/11] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings
[not found] <20210630073013.22415-1-biju.das.jz@bp.renesas.com>
2021-06-30 7:30 ` [PATCH v3 01/11] dt-bindings: usb: generic-ohci: Document dr_mode property Biju Das
2021-06-30 7:30 ` [PATCH v3 02/11] dt-bindings: usb: generic-ehci: " Biju Das
@ 2021-06-30 7:30 ` Biju Das
2021-07-01 14:02 ` Rob Herring
2021-07-01 20:23 ` Rob Herring
2021-06-30 7:30 ` [PATCH v3 07/11] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings Biju Das
` (3 subsequent siblings)
6 siblings, 2 replies; 18+ messages in thread
From: Biju Das @ 2021-06-30 7:30 UTC (permalink / raw)
To: Philipp Zabel, Rob Herring
Cc: Biju Das, devicetree, Geert Uytterhoeven, Yoshihiro Shimoda,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
Add device tree binding document for RZ/G2L USBPHY Control Device.
It mainly controls reset and power down of the USB/PHY.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3:
* New patch.
* Modelled USBPHY control from phy bindings to reset bindings, since the
IP mainly contols the reset of USB PHY.
---
.../reset/renesas,rzg2l-usbphy-ctrl.yaml | 66 +++++++++++++++++++
1 file changed, 66 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
diff --git a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
new file mode 100644
index 000000000000..2a398c7ce7c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L USBPHY Control
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+description:
+ The RZ/G2L USBPHY Control mainly controls reset and power down of the
+ USB/PHY.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
+ - const: renesas,rzg2l-usbphy-ctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ '#reset-cells':
+ # see reset.txt in the same directory
+ const: 1
+ description: |
+ The phandle's argument in the reset specifier is the PHY reset associated
+ with the USB port.
+ 0 = Port 1 Phy reset
+ 1 = Port 2 Phy reset
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+ - power-domains
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r9a07g044-cpg.h>
+
+ phyrst: usbphy-ctrl@11c40000 {
+ compatible = "renesas,r9a07g044-usbphy-ctrl",
+ "renesas,rzg2l-usbphy-ctrl";
+ reg = <0x11c40000 0x10000>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
+ resets = <&cpg R9A07G044_USB_PRESETN>;
+ power-domains = <&cpg>;
+ #reset-cells = <1>;
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 07/11] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings
[not found] <20210630073013.22415-1-biju.das.jz@bp.renesas.com>
` (2 preceding siblings ...)
2021-06-30 7:30 ` [PATCH v3 03/11] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings Biju Das
@ 2021-06-30 7:30 ` Biju Das
2021-06-30 9:29 ` Geert Uytterhoeven
2021-06-30 7:30 ` [PATCH v3 08/11] arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support Biju Das
` (2 subsequent siblings)
6 siblings, 1 reply; 18+ messages in thread
From: Biju Das @ 2021-06-30 7:30 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Kishon Vijay Abraham I, Vinod Koul, Yoshihiro Shimoda,
linux-phy, devicetree, Geert Uytterhoeven, Chris Paterson,
Biju Das, Prabhakar Mahadev Lad, linux-renesas-soc
Document USB phy bindings for RZ/G2L SoC.
RZ/G2L USB2.0 phy uses line ctrl register for OTG_ID pin changes. Apart
from this it uses a different OTG-BC interrupt bit for device recognition.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2->v3
* Created a new compatible for RZ/G2L as per Geert's suggestion.
* Added resets required properties for RZ/G2L SoC.
---
.../bindings/phy/renesas,usb2-phy.yaml | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
index d5dc5a3cdceb..a7e585ff28dc 100644
--- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
@@ -30,6 +30,9 @@ properties:
- renesas,usb2-phy-r8a77995 # R-Car D3
- const: renesas,rcar-gen3-usb2-phy
+ - items:
+ - const: renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
+
reg:
maxItems: 1
@@ -91,6 +94,21 @@ required:
- clocks
- '#phy-cells'
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,usb2-phy-r9a07g044
+ then:
+ properties:
+ resets:
+ items:
+ - description: USB phy reset
+ - description: reset of USB 2.0 host side
+ required:
+ - resets
+
additionalProperties: false
examples:
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 08/11] arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support
[not found] <20210630073013.22415-1-biju.das.jz@bp.renesas.com>
` (3 preceding siblings ...)
2021-06-30 7:30 ` [PATCH v3 07/11] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings Biju Das
@ 2021-06-30 7:30 ` Biju Das
2021-06-30 7:30 ` [PATCH v3 09/11] dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings Biju Das
2021-06-30 7:30 ` [PATCH v3 11/11] arm64: dts: renesas: r9a07g044: Add USB2.0 device support Biju Das
6 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2021-06-30 7:30 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add USB2.0 phy and host support to SoC DT.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
V3:
* Added reset entries
* Updated compatible, phy and reset entries.
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 94 ++++++++++++++++++++++
1 file changed, 94 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 9a7489dc70d1..746f71696e37 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -200,6 +200,100 @@
<0x0 0x11940000 0 0x60000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
+
+ phyrst: usbphy-ctrl@11c40000 {
+ compatible = "renesas,r9a07g044-usbphy-ctrl",
+ "renesas,rzg2l-usbphy-ctrl";
+ reg = <0 0x11c40000 0 0x10000>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
+ resets = <&cpg R9A07G044_USB_PRESETN>;
+ power-domains = <&cpg>;
+ #reset-cells = <1>;
+ };
+
+ ohci0: usb@11c50000 {
+ compatible = "generic-ohci";
+ reg = <0 0x11c50000 0 0x100>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A07G044_USB_U2H0_HRESETN>;
+ phys = <&usb2_phy0 1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ohci1: usb@11c70000 {
+ compatible = "generic-ohci";
+ reg = <0 0x11c70000 0 0x100>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>,
+ <&cpg R9A07G044_USB_U2H1_HRESETN>;
+ phys = <&usb2_phy1 1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci0: usb@11c50100 {
+ compatible = "generic-ehci";
+ reg = <0 0x11c50100 0 0x100>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A07G044_USB_U2H0_HRESETN>;
+ phys = <&usb2_phy0 2>;
+ phy-names = "usb";
+ companion = <&ohci0>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci1: usb@11c70100 {
+ compatible = "generic-ehci";
+ reg = <0 0x11c70100 0 0x100>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>,
+ <&cpg R9A07G044_USB_U2H1_HRESETN>;
+ phys = <&usb2_phy1 2>;
+ phy-names = "usb";
+ companion = <&ohci1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy0: usb-phy@11c50200 {
+ compatible = "renesas,usb2-phy-r9a07g044";
+ reg = <0 0x11c50200 0 0x700>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A07G044_USB_U2H0_HRESETN>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy1: usb-phy@11c70200 {
+ compatible = "renesas,usb2-phy-r9a07g044";
+ reg = <0 0x11c70200 0 0x700>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>,
+ <&cpg R9A07G044_USB_U2H1_HRESETN>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
};
timer {
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 09/11] dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings
[not found] <20210630073013.22415-1-biju.das.jz@bp.renesas.com>
` (4 preceding siblings ...)
2021-06-30 7:30 ` [PATCH v3 08/11] arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support Biju Das
@ 2021-06-30 7:30 ` Biju Das
2021-07-14 21:24 ` Rob Herring
2021-06-30 7:30 ` [PATCH v3 11/11] arm64: dts: renesas: r9a07g044: Add USB2.0 device support Biju Das
6 siblings, 1 reply; 18+ messages in thread
From: Biju Das @ 2021-06-30 7:30 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Greg Kroah-Hartman, Yoshihiro Shimoda, linux-usb,
devicetree, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Document RZ/G2L (R9A07G044L) SoC bindings.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3:
* Updated the bindings as per the USBPHY control IP.
---
.../bindings/usb/renesas,usbhs.yaml | 21 +++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
index ad73339ffe1d..5562839bef8d 100644
--- a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
+++ b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
@@ -17,7 +17,9 @@ properties:
- const: renesas,rza1-usbhs
- items:
- - const: renesas,usbhs-r7s9210 # RZ/A2
+ - enum:
+ - renesas,usbhs-r7s9210 # RZ/A2
+ - renesas,usbhs-r9a07g044 # RZ/G2{L,LC}
- const: renesas,rza2-usbhs
- items:
@@ -59,7 +61,7 @@ properties:
- description: USB 2.0 clock selector
interrupts:
- maxItems: 1
+ minItems: 1
renesas,buswait:
$ref: /schemas/types.yaml#/definitions/uint32
@@ -108,6 +110,21 @@ required:
- clocks
- interrupts
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,usbhs-r9a07g044
+ then:
+ properties:
+ interrupts:
+ items:
+ - description: U2P_IXL_INT
+ - description: U2P_INT_DMA[0]
+ - description: U2P_INT_DMA[1]
+ - description: U2P_INT_DMAERR
+
additionalProperties: false
examples:
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 11/11] arm64: dts: renesas: r9a07g044: Add USB2.0 device support
[not found] <20210630073013.22415-1-biju.das.jz@bp.renesas.com>
` (5 preceding siblings ...)
2021-06-30 7:30 ` [PATCH v3 09/11] dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings Biju Das
@ 2021-06-30 7:30 ` Biju Das
6 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2021-06-30 7:30 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add USB2.0 device support to RZ/G2L SoC DT.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
V3:
* Updated reset entries.
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 746f71696e37..3e3a234efa27 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -294,6 +294,25 @@
power-domains = <&cpg>;
status = "disabled";
};
+
+ hsusb: usb@11c60000 {
+ compatible = "renesas,usbhs-r9a07g044",
+ "renesas,rza2-usbhs";
+ reg = <0 0x11c60000 0 0x10000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
+ renesas,buswait = <7>;
+ phys = <&usb2_phy0 3>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
};
timer {
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v3 07/11] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings
2021-06-30 7:30 ` [PATCH v3 07/11] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings Biju Das
@ 2021-06-30 9:29 ` Geert Uytterhoeven
2021-06-30 10:28 ` Biju Das
2021-07-14 21:21 ` Rob Herring
0 siblings, 2 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2021-06-30 9:29 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Kishon Vijay Abraham I, Vinod Koul,
Yoshihiro Shimoda, linux-phy,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, Linux-Renesas
Hi Biju,
Thanks for your patch!
On Wed, Jun 30, 2021 at 9:31 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Document USB phy bindings for RZ/G2L SoC.
>
> RZ/G2L USB2.0 phy uses line ctrl register for OTG_ID pin changes. Apart
> from this it uses a different OTG-BC interrupt bit for device recognition.
Nothing about resets? But see below...
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3
> * Created a new compatible for RZ/G2L as per Geert's suggestion.
> * Added resets required properties for RZ/G2L SoC.
> ---
> .../bindings/phy/renesas,usb2-phy.yaml | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> index d5dc5a3cdceb..a7e585ff28dc 100644
> --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> @@ -30,6 +30,9 @@ properties:
> - renesas,usb2-phy-r8a77995 # R-Car D3
> - const: renesas,rcar-gen3-usb2-phy
>
> + - items:
> + - const: renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
> +
> reg:
> maxItems: 1
>
> @@ -91,6 +94,21 @@ required:
> - clocks
> - '#phy-cells'
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,usb2-phy-r9a07g044
> + then:
> + properties:
> + resets:
> + items:
> + - description: USB phy reset
> + - description: reset of USB 2.0 host side
Do you need the second reset?
Looking at your .dtsi patch, the second reset is shared with ehci/ohci,
so perhaps it makes sense to drop it from the phy node?
> + required:
> + - resets
> +
> additionalProperties: false
>
> examples:
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH v3 07/11] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings
2021-06-30 9:29 ` Geert Uytterhoeven
@ 2021-06-30 10:28 ` Biju Das
2021-07-14 21:21 ` Rob Herring
1 sibling, 0 replies; 18+ messages in thread
From: Biju Das @ 2021-06-30 10:28 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Rob Herring, Kishon Vijay Abraham I, Vinod Koul,
Yoshihiro Shimoda, linux-phy,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, Linux-Renesas
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH v3 07/11] dt-bindings: phy: renesas,usb2-phy: Document
> RZ/G2L phy bindings
>
> Hi Biju,
>
> Thanks for your patch!
>
> On Wed, Jun 30, 2021 at 9:31 AM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > Document USB phy bindings for RZ/G2L SoC.
> >
> > RZ/G2L USB2.0 phy uses line ctrl register for OTG_ID pin changes.
> > Apart from this it uses a different OTG-BC interrupt bit for device
> recognition.
>
> Nothing about resets? But see below...
Initially the reset of USB/PHY port is in asserted state. So we need
to perform a release reset using USBPHY control IP.
OK, will add this in V4.
>
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v2->v3
> > * Created a new compatible for RZ/G2L as per Geert's suggestion.
> > * Added resets required properties for RZ/G2L SoC.
> > ---
> > .../bindings/phy/renesas,usb2-phy.yaml | 18 ++++++++++++++++++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > index d5dc5a3cdceb..a7e585ff28dc 100644
> > --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > @@ -30,6 +30,9 @@ properties:
> > - renesas,usb2-phy-r8a77995 # R-Car D3
> > - const: renesas,rcar-gen3-usb2-phy
> >
> > + - items:
> > + - const: renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
> > +
> > reg:
> > maxItems: 1
> >
> > @@ -91,6 +94,21 @@ required:
> > - clocks
> > - '#phy-cells'
> >
> > +allOf:
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: renesas,usb2-phy-r9a07g044
> > + then:
> > + properties:
> > + resets:
> > + items:
> > + - description: USB phy reset
> > + - description: reset of USB 2.0 host side
>
> Do you need the second reset?
> Looking at your .dtsi patch, the second reset is shared with ehci/ohci, so
> perhaps it makes sense to drop it from the phy node?
OK. Agreed will drop the second reset from phy node.
Cheers,
Biju
>
> > + required:
> > + - resets
> > +
> > additionalProperties: false
> >
> > examples:
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 03/11] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings
2021-06-30 7:30 ` [PATCH v3 03/11] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings Biju Das
@ 2021-07-01 14:02 ` Rob Herring
2021-07-01 20:23 ` Rob Herring
1 sibling, 0 replies; 18+ messages in thread
From: Rob Herring @ 2021-07-01 14:02 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Yoshihiro Shimoda, Geert Uytterhoeven,
Chris Paterson, linux-renesas-soc, devicetree,
Prabhakar Mahadev Lad, Philipp Zabel, Biju Das
On Wed, 30 Jun 2021 08:30:05 +0100, Biju Das wrote:
> Add device tree binding document for RZ/G2L USBPHY Control Device.
> It mainly controls reset and power down of the USB/PHY.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v3:
> * New patch.
> * Modelled USBPHY control from phy bindings to reset bindings, since the
> IP mainly contols the reset of USB PHY.
> ---
> .../reset/renesas,rzg2l-usbphy-ctrl.yaml | 66 +++++++++++++++++++
> 1 file changed, 66 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.example.dts:19:18: fatal error: dt-bindings/clock/r9a07g044-cpg.h: No such file or directory
19 | #include <dt-bindings/clock/r9a07g044-cpg.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:380: Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1416: dt_binding_check] Error 2
\ndoc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1498761
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 03/11] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings
2021-06-30 7:30 ` [PATCH v3 03/11] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings Biju Das
2021-07-01 14:02 ` Rob Herring
@ 2021-07-01 20:23 ` Rob Herring
2021-07-03 10:53 ` Biju Das
1 sibling, 1 reply; 18+ messages in thread
From: Rob Herring @ 2021-07-01 20:23 UTC (permalink / raw)
To: Biju Das
Cc: Philipp Zabel, devicetree, Geert Uytterhoeven, Yoshihiro Shimoda,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
On Wed, Jun 30, 2021 at 08:30:05AM +0100, Biju Das wrote:
> Add device tree binding document for RZ/G2L USBPHY Control Device.
> It mainly controls reset and power down of the USB/PHY.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v3:
> * New patch.
> * Modelled USBPHY control from phy bindings to reset bindings, since the
> IP mainly contols the reset of USB PHY.
> ---
> .../reset/renesas,rzg2l-usbphy-ctrl.yaml | 66 +++++++++++++++++++
> 1 file changed, 66 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
> new file mode 100644
> index 000000000000..2a398c7ce7c8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
> @@ -0,0 +1,66 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G2L USBPHY Control
> +
> +maintainers:
> + - Biju Das <biju.das.jz@bp.renesas.com>
> +
> +description:
> + The RZ/G2L USBPHY Control mainly controls reset and power down of the
> + USB/PHY.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
> + - const: renesas,rzg2l-usbphy-ctrl
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + '#reset-cells':
> + # see reset.txt in the same directory
Drop the reference. With that,
Reviewed-by: Rob Herring <robh@kernel.org>
> + const: 1
> + description: |
> + The phandle's argument in the reset specifier is the PHY reset associated
> + with the USB port.
> + 0 = Port 1 Phy reset
> + 1 = Port 2 Phy reset
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - resets
> + - power-domains
> + - '#reset-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/r9a07g044-cpg.h>
> +
> + phyrst: usbphy-ctrl@11c40000 {
> + compatible = "renesas,r9a07g044-usbphy-ctrl",
> + "renesas,rzg2l-usbphy-ctrl";
> + reg = <0x11c40000 0x10000>;
> + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
> + resets = <&cpg R9A07G044_USB_PRESETN>;
> + power-domains = <&cpg>;
> + #reset-cells = <1>;
> + };
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH v3 03/11] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings
2021-07-01 20:23 ` Rob Herring
@ 2021-07-03 10:53 ` Biju Das
0 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2021-07-03 10:53 UTC (permalink / raw)
To: Rob Herring
Cc: Philipp Zabel, devicetree, Geert Uytterhoeven, Yoshihiro Shimoda,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
Hi Rob,
Thanks for the feedback.
> Subject: Re: [PATCH v3 03/11] dt-bindings: reset: Document RZ/G2L USBPHY
> Control bindings
>
> On Wed, Jun 30, 2021 at 08:30:05AM +0100, Biju Das wrote:
> > Add device tree binding document for RZ/G2L USBPHY Control Device.
> > It mainly controls reset and power down of the USB/PHY.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v3:
> > * New patch.
> > * Modelled USBPHY control from phy bindings to reset bindings, since
> the
> > IP mainly contols the reset of USB PHY.
> > ---
> > .../reset/renesas,rzg2l-usbphy-ctrl.yaml | 66 +++++++++++++++++++
> > 1 file changed, 66 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.ya
> > ml
> > b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.ya
> > ml
> > new file mode 100644
> > index 000000000000..2a398c7ce7c8
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctr
> > +++ l.yaml
> > @@ -0,0 +1,66 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fschemas%2Freset%2Frenesas%2Crzg2l-usbphy-ctrl.yaml%23&am
> > +p;data=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7C770350c845f64b015f680
> > +8d93cce253d%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637607678355
> > +475757%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLC
> > +JBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=9vEtPav6hmc1axa6Vj2NqT%
> > +2BT0EOoyXTelx2Ft5fCEKE%3D&reserved=0
> > +$schema:
> > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=04%7C01%7Cbiju.das.
> > +jz%40bp.renesas.com%7C770350c845f64b015f6808d93cce253d%7C53d82571da19
> > +47e49cb4625a166a4a2a%7C0%7C0%7C637607678355475757%7CUnknown%7CTWFpbGZ
> > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%
> > +3D%7C1000&sdata=1e4CSqGpir0E%2B7izDrdcuB%2F%2FpL7fqfPNRBPCs0w%2B%
> > +2B84%3D&reserved=0
> > +
> > +title: Renesas RZ/G2L USBPHY Control
> > +
> > +maintainers:
> > + - Biju Das <biju.das.jz@bp.renesas.com>
> > +
> > +description:
> > + The RZ/G2L USBPHY Control mainly controls reset and power down of
> > +the
> > + USB/PHY.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
> > + - const: renesas,rzg2l-usbphy-ctrl
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + resets:
> > + maxItems: 1
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + '#reset-cells':
> > + # see reset.txt in the same directory
>
> Drop the reference. With that,
OK. Will drop the reference in next version.
Thanks,
Biju
>
> Reviewed-by: Rob Herring <robh@kernel.org>
>
> > + const: 1
> > + description: |
> > + The phandle's argument in the reset specifier is the PHY reset
> associated
> > + with the USB port.
> > + 0 = Port 1 Phy reset
> > + 1 = Port 2 Phy reset
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - resets
> > + - power-domains
> > + - '#reset-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/r9a07g044-cpg.h>
> > +
> > + phyrst: usbphy-ctrl@11c40000 {
> > + compatible = "renesas,r9a07g044-usbphy-ctrl",
> > + "renesas,rzg2l-usbphy-ctrl";
> > + reg = <0x11c40000 0x10000>;
> > + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
> > + resets = <&cpg R9A07G044_USB_PRESETN>;
> > + power-domains = <&cpg>;
> > + #reset-cells = <1>;
> > + };
> > --
> > 2.17.1
> >
> >
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 01/11] dt-bindings: usb: generic-ohci: Document dr_mode property
2021-06-30 7:30 ` [PATCH v3 01/11] dt-bindings: usb: generic-ohci: Document dr_mode property Biju Das
@ 2021-07-14 21:16 ` Rob Herring
0 siblings, 0 replies; 18+ messages in thread
From: Rob Herring @ 2021-07-14 21:16 UTC (permalink / raw)
To: Biju Das
Cc: Geert Uytterhoeven, devicetree, Rob Herring, Yoshihiro Shimoda,
linux-renesas-soc, linux-usb, Chris Paterson, Greg Kroah-Hartman,
Biju Das, Prabhakar Mahadev Lad
On Wed, 30 Jun 2021 08:30:03 +0100, Biju Das wrote:
> Document the optional property dr_mode present on both RZ/G2 and
> R-Car Gen3 SoCs.
>
> It fixes the dtbs_check warning,
> 'dr_mode' does not match any of the regexes: 'pinctrl-[0-9]+'
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3:
> * Dropped RZ/G2L SoC and USBPHY control IP is modelled as reset binding.
> v2:
> * New patch
> ---
> Documentation/devicetree/bindings/usb/generic-ohci.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 02/11] dt-bindings: usb: generic-ehci: Document dr_mode property
2021-06-30 7:30 ` [PATCH v3 02/11] dt-bindings: usb: generic-ehci: " Biju Das
@ 2021-07-14 21:16 ` Rob Herring
0 siblings, 0 replies; 18+ messages in thread
From: Rob Herring @ 2021-07-14 21:16 UTC (permalink / raw)
To: Biju Das
Cc: Prabhakar Mahadev Lad, linux-renesas-soc, Yoshihiro Shimoda,
Greg Kroah-Hartman, Geert Uytterhoeven, Chris Paterson,
devicetree, linux-usb, Rob Herring, Biju Das
On Wed, 30 Jun 2021 08:30:04 +0100, Biju Das wrote:
> Document the optional property dr_mode present on both RZ/G2 and
> R-Car Gen3 SoCs.
>
> It fixes dtbs_check warning,
> 'dr_mode' does not match any of the regexes: 'pinctrl-[0-9]+'
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3:
> * Dropped RZ/G2L SoC and USBPHY control IP is modelled as reset binding.
> v2:
> * New patch
> ---
> Documentation/devicetree/bindings/usb/generic-ehci.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 07/11] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings
2021-06-30 9:29 ` Geert Uytterhoeven
2021-06-30 10:28 ` Biju Das
@ 2021-07-14 21:21 ` Rob Herring
2021-07-18 8:29 ` Biju Das
1 sibling, 1 reply; 18+ messages in thread
From: Rob Herring @ 2021-07-14 21:21 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Biju Das, Kishon Vijay Abraham I, Vinod Koul, Yoshihiro Shimoda,
linux-phy,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, Linux-Renesas
On Wed, Jun 30, 2021 at 11:29:36AM +0200, Geert Uytterhoeven wrote:
> Hi Biju,
>
> Thanks for your patch!
>
> On Wed, Jun 30, 2021 at 9:31 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > Document USB phy bindings for RZ/G2L SoC.
> >
> > RZ/G2L USB2.0 phy uses line ctrl register for OTG_ID pin changes. Apart
> > from this it uses a different OTG-BC interrupt bit for device recognition.
>
> Nothing about resets? But see below...
>
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v2->v3
> > * Created a new compatible for RZ/G2L as per Geert's suggestion.
> > * Added resets required properties for RZ/G2L SoC.
> > ---
> > .../bindings/phy/renesas,usb2-phy.yaml | 18 ++++++++++++++++++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > index d5dc5a3cdceb..a7e585ff28dc 100644
> > --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > @@ -30,6 +30,9 @@ properties:
> > - renesas,usb2-phy-r8a77995 # R-Car D3
> > - const: renesas,rcar-gen3-usb2-phy
> >
> > + - items:
> > + - const: renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
> > +
> > reg:
> > maxItems: 1
> >
> > @@ -91,6 +94,21 @@ required:
> > - clocks
> > - '#phy-cells'
> >
> > +allOf:
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: renesas,usb2-phy-r9a07g044
> > + then:
> > + properties:
> > + resets:
> > + items:
> > + - description: USB phy reset
> > + - description: reset of USB 2.0 host side
>
> Do you need the second reset?
> Looking at your .dtsi patch, the second reset is shared with ehci/ohci,
> so perhaps it makes sense to drop it from the phy node?
The existing binding has the host reset (and peripheral, but no phy
reset). Was that a mistake too? Smells like collecting resources the
driver happens to want, not what the h/w connections are.
Rob
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 09/11] dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings
2021-06-30 7:30 ` [PATCH v3 09/11] dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings Biju Das
@ 2021-07-14 21:24 ` Rob Herring
2021-07-15 7:18 ` Biju Das
0 siblings, 1 reply; 18+ messages in thread
From: Rob Herring @ 2021-07-14 21:24 UTC (permalink / raw)
To: Biju Das
Cc: Greg Kroah-Hartman, Yoshihiro Shimoda, linux-usb, devicetree,
Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
On Wed, Jun 30, 2021 at 08:30:11AM +0100, Biju Das wrote:
> Document RZ/G2L (R9A07G044L) SoC bindings.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v3:
> * Updated the bindings as per the USBPHY control IP.
> ---
> .../bindings/usb/renesas,usbhs.yaml | 21 +++++++++++++++++--
> 1 file changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
> index ad73339ffe1d..5562839bef8d 100644
> --- a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
> +++ b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
> @@ -17,7 +17,9 @@ properties:
> - const: renesas,rza1-usbhs
>
> - items:
> - - const: renesas,usbhs-r7s9210 # RZ/A2
> + - enum:
> + - renesas,usbhs-r7s9210 # RZ/A2
> + - renesas,usbhs-r9a07g044 # RZ/G2{L,LC}
> - const: renesas,rza2-usbhs
>
> - items:
> @@ -59,7 +61,7 @@ properties:
> - description: USB 2.0 clock selector
>
> interrupts:
> - maxItems: 1
> + minItems: 1
maxItems: 4
>
> renesas,buswait:
> $ref: /schemas/types.yaml#/definitions/uint32
> @@ -108,6 +110,21 @@ required:
> - clocks
> - interrupts
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,usbhs-r9a07g044
> + then:
> + properties:
> + interrupts:
> + items:
> + - description: U2P_IXL_INT
> + - description: U2P_INT_DMA[0]
> + - description: U2P_INT_DMA[1]
> + - description: U2P_INT_DMAERR
If the first interrupt is the same on all devices, then this items
list should be moved to the top level and just have a 'minItems: 4'
here.
else:
properties:
interrupts:
maxItems: 1
> +
> additionalProperties: false
>
> examples:
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH v3 09/11] dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings
2021-07-14 21:24 ` Rob Herring
@ 2021-07-15 7:18 ` Biju Das
0 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2021-07-15 7:18 UTC (permalink / raw)
To: Rob Herring
Cc: Greg Kroah-Hartman, Yoshihiro Shimoda, linux-usb, devicetree,
Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Hi Rob,
Thanks for the feedback.
> Subject: Re: [PATCH v3 09/11] dt-bindings: usb: renesas,usbhs: Document
> RZ/G2L bindings
>
> On Wed, Jun 30, 2021 at 08:30:11AM +0100, Biju Das wrote:
> > Document RZ/G2L (R9A07G044L) SoC bindings.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v3:
> > * Updated the bindings as per the USBPHY control IP.
> > ---
> > .../bindings/usb/renesas,usbhs.yaml | 21 +++++++++++++++++--
> > 1 file changed, 19 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
> > b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
> > index ad73339ffe1d..5562839bef8d 100644
> > --- a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
> > +++ b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
> > @@ -17,7 +17,9 @@ properties:
> > - const: renesas,rza1-usbhs
> >
> > - items:
> > - - const: renesas,usbhs-r7s9210 # RZ/A2
> > + - enum:
> > + - renesas,usbhs-r7s9210 # RZ/A2
> > + - renesas,usbhs-r9a07g044 # RZ/G2{L,LC}
> > - const: renesas,rza2-usbhs
> >
> > - items:
> > @@ -59,7 +61,7 @@ properties:
> > - description: USB 2.0 clock selector
> >
> > interrupts:
> > - maxItems: 1
> > + minItems: 1
>
> maxItems: 4
OK.
>
> >
> > renesas,buswait:
> > $ref: /schemas/types.yaml#/definitions/uint32
> > @@ -108,6 +110,21 @@ required:
> > - clocks
> > - interrupts
> >
> > +allOf:
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: renesas,usbhs-r9a07g044
> > + then:
> > + properties:
> > + interrupts:
> > + items:
> > + - description: U2P_IXL_INT
> > + - description: U2P_INT_DMA[0]
> > + - description: U2P_INT_DMA[1]
> > + - description: U2P_INT_DMAERR
>
> If the first interrupt is the same on all devices, then this items list
> should be moved to the top level and just have a 'minItems: 4'
> here.
From the hardware point, it is same "HSUSB interrupt"
But HW manual is representing it differently
R-Car Gen2, RZ/G1:-USB2.0_597 (OTG)
R-Car Gen3, RZ/G2:- EHCI/OHCI OTG.ch0
RZ/G2L: U2P_IXL_INT
Other devices ??.
So it make sense to leave as it is. Please let me know if you think other wise.
Regards,
Biju
>
>
> else:
> properties:
> interrupts:
> maxItems: 1
>
>
> > +
> > additionalProperties: false
> >
> > examples:
> > --
> > 2.17.1
> >
> >
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH v3 07/11] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings
2021-07-14 21:21 ` Rob Herring
@ 2021-07-18 8:29 ` Biju Das
0 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2021-07-18 8:29 UTC (permalink / raw)
To: Rob Herring, Geert Uytterhoeven
Cc: Kishon Vijay Abraham I, Vinod Koul, Yoshihiro Shimoda, linux-phy,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, Linux-Renesas
Hi Rob,
> -----Original Message-----
> Subject: Re: [PATCH v3 07/11] dt-bindings: phy: renesas,usb2-phy: Document
> RZ/G2L phy bindings
>
> On Wed, Jun 30, 2021 at 11:29:36AM +0200, Geert Uytterhoeven wrote:
> > Hi Biju,
> >
> > Thanks for your patch!
> >
> > On Wed, Jun 30, 2021 at 9:31 AM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > > Document USB phy bindings for RZ/G2L SoC.
> > >
> > > RZ/G2L USB2.0 phy uses line ctrl register for OTG_ID pin changes.
> > > Apart from this it uses a different OTG-BC interrupt bit for device
> recognition.
> >
> > Nothing about resets? But see below...
> >
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v2->v3
> > > * Created a new compatible for RZ/G2L as per Geert's suggestion.
> > > * Added resets required properties for RZ/G2L SoC.
> > > ---
> > > .../bindings/phy/renesas,usb2-phy.yaml | 18
> ++++++++++++++++++
> > > 1 file changed, 18 insertions(+)
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > > b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > > index d5dc5a3cdceb..a7e585ff28dc 100644
> > > --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > > +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > > @@ -30,6 +30,9 @@ properties:
> > > - renesas,usb2-phy-r8a77995 # R-Car D3
> > > - const: renesas,rcar-gen3-usb2-phy
> > >
> > > + - items:
> > > + - const: renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
> > > +
> > > reg:
> > > maxItems: 1
> > >
> > > @@ -91,6 +94,21 @@ required:
> > > - clocks
> > > - '#phy-cells'
> > >
> > > +allOf:
> > > + - if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + const: renesas,usb2-phy-r9a07g044
> > > + then:
> > > + properties:
> > > + resets:
> > > + items:
> > > + - description: USB phy reset
> > > + - description: reset of USB 2.0 host side
> >
> > Do you need the second reset?
> > Looking at your .dtsi patch, the second reset is shared with
> > ehci/ohci, so perhaps it makes sense to drop it from the phy node?
>
> The existing binding has the host reset (and peripheral, but no phy
> reset). Was that a mistake too? Smells like collecting resources the
> driver happens to want, not what the h/w connections are.
On that SoC's there is no USBPHY control IP to control the reset. But PHY
is part of either host block or peripheral block. On RZ/G2L as well PHY is
part of Host block but we have dedicated IP to control the reset.
Regards,
Biju
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2021-07-18 8:29 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
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2021-06-30 7:30 ` [PATCH v3 01/11] dt-bindings: usb: generic-ohci: Document dr_mode property Biju Das
2021-07-14 21:16 ` Rob Herring
2021-06-30 7:30 ` [PATCH v3 02/11] dt-bindings: usb: generic-ehci: " Biju Das
2021-07-14 21:16 ` Rob Herring
2021-06-30 7:30 ` [PATCH v3 03/11] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings Biju Das
2021-07-01 14:02 ` Rob Herring
2021-07-01 20:23 ` Rob Herring
2021-07-03 10:53 ` Biju Das
2021-06-30 7:30 ` [PATCH v3 07/11] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings Biju Das
2021-06-30 9:29 ` Geert Uytterhoeven
2021-06-30 10:28 ` Biju Das
2021-07-14 21:21 ` Rob Herring
2021-07-18 8:29 ` Biju Das
2021-06-30 7:30 ` [PATCH v3 08/11] arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support Biju Das
2021-06-30 7:30 ` [PATCH v3 09/11] dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings Biju Das
2021-07-14 21:24 ` Rob Herring
2021-07-15 7:18 ` Biju Das
2021-06-30 7:30 ` [PATCH v3 11/11] arm64: dts: renesas: r9a07g044: Add USB2.0 device support Biju Das
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