* [PATCH] arm64: dts: intel: socfpga_agilex: use defined GIC interrupt type for ECC
@ 2022-05-30 6:12 niravkumar.l.rabara
2022-05-30 6:36 ` Krzysztof Kozlowski
2022-05-30 7:25 ` [PATCH v2] " niravkumar.l.rabara
0 siblings, 2 replies; 5+ messages in thread
From: niravkumar.l.rabara @ 2022-05-30 6:12 UTC (permalink / raw)
To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski
Cc: devicetree, linux-kernel, niravkumar.l.rabara
From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Use defined GIC interrupt type instead of hard-coded numbers for ECC
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
---
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index caccb0334ada..7bbec8aafa62 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -581,7 +581,7 @@ eccmgr {
sdramedac {
compatible = "altr,sdram-edac-s10";
altr,sdr-syscon = <&sdr>;
- interrupts = <16 4>;
+ interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
};
ocram-ecc@ff8cc000 {
@@ -589,7 +589,7 @@ ocram-ecc@ff8cc000 {
"altr,socfpga-a10-ocram-ecc";
reg = <0xff8cc000 0x100>;
altr,ecc-parent = <&ocram>;
- interrupts = <1 4>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
};
usb0-ecc@ff8c4000 {
@@ -597,7 +597,7 @@ usb0-ecc@ff8c4000 {
"altr,socfpga-usb-ecc";
reg = <0xff8c4000 0x100>;
altr,ecc-parent = <&usb0>;
- interrupts = <2 4>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
};
emac0-rx-ecc@ff8c0000 {
@@ -605,7 +605,7 @@ emac0-rx-ecc@ff8c0000 {
"altr,socfpga-eth-mac-ecc";
reg = <0xff8c0000 0x100>;
altr,ecc-parent = <&gmac0>;
- interrupts = <4 4>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
};
emac0-tx-ecc@ff8c0400 {
@@ -613,7 +613,7 @@ emac0-tx-ecc@ff8c0400 {
"altr,socfpga-eth-mac-ecc";
reg = <0xff8c0400 0x100>;
altr,ecc-parent = <&gmac0>;
- interrupts = <5 4>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
};
sdmmca-ecc@ff8c8c00 {
@@ -621,8 +621,8 @@ sdmmca-ecc@ff8c8c00 {
"altr,socfpga-sdmmc-ecc";
reg = <0xff8c8c00 0x100>;
altr,ecc-parent = <&mmc>;
- interrupts = <14 4>,
- <15 4>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
+ <15 IRQ_TYPE_LEVEL_HIGH>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] arm64: dts: intel: socfpga_agilex: use defined GIC interrupt type for ECC
2022-05-30 6:12 [PATCH] arm64: dts: intel: socfpga_agilex: use defined GIC interrupt type for ECC niravkumar.l.rabara
@ 2022-05-30 6:36 ` Krzysztof Kozlowski
2022-05-30 7:25 ` [PATCH v2] " niravkumar.l.rabara
1 sibling, 0 replies; 5+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-30 6:36 UTC (permalink / raw)
To: niravkumar.l.rabara, Dinh Nguyen, Rob Herring, Krzysztof Kozlowski
Cc: devicetree, linux-kernel
On 30/05/2022 08:12, niravkumar.l.rabara@intel.com wrote:
> From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
>
> Use defined GIC interrupt type instead of hard-coded numbers for ECC
What is an ECC in the context of commit log? Please also add full-stop.
The code looks good, so with some explanation of ECC:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> ---
> arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2] arm64: dts: intel: socfpga_agilex: use defined GIC interrupt type for ECC
2022-05-30 6:12 [PATCH] arm64: dts: intel: socfpga_agilex: use defined GIC interrupt type for ECC niravkumar.l.rabara
2022-05-30 6:36 ` Krzysztof Kozlowski
@ 2022-05-30 7:25 ` niravkumar.l.rabara
2022-05-30 7:31 ` Krzysztof Kozlowski
1 sibling, 1 reply; 5+ messages in thread
From: niravkumar.l.rabara @ 2022-05-30 7:25 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Dinh Nguyen, Rob Herring, devicetree, linux-kernel, niravkumar.l.rabara
From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Use defined GIC interrupt type instead of hard-coded numbers for ECC
(Error Correction Code) memory, which creates edac sysfs interface.
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
---
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index caccb0334ada..7bbec8aafa62 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -581,7 +581,7 @@ eccmgr {
sdramedac {
compatible = "altr,sdram-edac-s10";
altr,sdr-syscon = <&sdr>;
- interrupts = <16 4>;
+ interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
};
ocram-ecc@ff8cc000 {
@@ -589,7 +589,7 @@ ocram-ecc@ff8cc000 {
"altr,socfpga-a10-ocram-ecc";
reg = <0xff8cc000 0x100>;
altr,ecc-parent = <&ocram>;
- interrupts = <1 4>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
};
usb0-ecc@ff8c4000 {
@@ -597,7 +597,7 @@ usb0-ecc@ff8c4000 {
"altr,socfpga-usb-ecc";
reg = <0xff8c4000 0x100>;
altr,ecc-parent = <&usb0>;
- interrupts = <2 4>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
};
emac0-rx-ecc@ff8c0000 {
@@ -605,7 +605,7 @@ emac0-rx-ecc@ff8c0000 {
"altr,socfpga-eth-mac-ecc";
reg = <0xff8c0000 0x100>;
altr,ecc-parent = <&gmac0>;
- interrupts = <4 4>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
};
emac0-tx-ecc@ff8c0400 {
@@ -613,7 +613,7 @@ emac0-tx-ecc@ff8c0400 {
"altr,socfpga-eth-mac-ecc";
reg = <0xff8c0400 0x100>;
altr,ecc-parent = <&gmac0>;
- interrupts = <5 4>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
};
sdmmca-ecc@ff8c8c00 {
@@ -621,8 +621,8 @@ sdmmca-ecc@ff8c8c00 {
"altr,socfpga-sdmmc-ecc";
reg = <0xff8c8c00 0x100>;
altr,ecc-parent = <&mmc>;
- interrupts = <14 4>,
- <15 4>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
+ <15 IRQ_TYPE_LEVEL_HIGH>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH v2] arm64: dts: intel: socfpga_agilex: use defined GIC interrupt type for ECC
2022-05-30 7:25 ` [PATCH v2] " niravkumar.l.rabara
@ 2022-05-30 7:31 ` Krzysztof Kozlowski
2022-06-14 15:53 ` Dinh Nguyen
0 siblings, 1 reply; 5+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-30 7:31 UTC (permalink / raw)
To: niravkumar.l.rabara, Krzysztof Kozlowski
Cc: Dinh Nguyen, Rob Herring, devicetree, linux-kernel
On 30/05/2022 09:25, niravkumar.l.rabara@intel.com wrote:
> From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
>
> Use defined GIC interrupt type instead of hard-coded numbers for ECC
> (Error Correction Code) memory, which creates edac sysfs interface.
Ah, ECC was about device node... sounds fine.
Anyway, please always include tags you received.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2] arm64: dts: intel: socfpga_agilex: use defined GIC interrupt type for ECC
2022-05-30 7:31 ` Krzysztof Kozlowski
@ 2022-06-14 15:53 ` Dinh Nguyen
0 siblings, 0 replies; 5+ messages in thread
From: Dinh Nguyen @ 2022-06-14 15:53 UTC (permalink / raw)
To: Krzysztof Kozlowski, niravkumar.l.rabara, Krzysztof Kozlowski
Cc: Rob Herring, devicetree, linux-kernel
On 5/30/22 02:31, Krzysztof Kozlowski wrote:
> On 30/05/2022 09:25, niravkumar.l.rabara@intel.com wrote:
>> From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
>>
>> Use defined GIC interrupt type instead of hard-coded numbers for ECC
>> (Error Correction Code) memory, which creates edac sysfs interface.
>
> Ah, ECC was about device node... sounds fine.
>
> Anyway, please always include tags you received.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
>
> Best regards,
> Krzysztof
Applied!
Thanks,
Dinh
^ permalink raw reply [flat|nested] 5+ messages in thread
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2022-05-30 6:12 [PATCH] arm64: dts: intel: socfpga_agilex: use defined GIC interrupt type for ECC niravkumar.l.rabara
2022-05-30 6:36 ` Krzysztof Kozlowski
2022-05-30 7:25 ` [PATCH v2] " niravkumar.l.rabara
2022-05-30 7:31 ` Krzysztof Kozlowski
2022-06-14 15:53 ` Dinh Nguyen
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