From: vijayakannan.ayyathurai@intel.com
To: daniel.lezcano@linaro.org, tglx@linutronix.de, robh+dt@kernel.org
Cc: devicetree@vger.kernel.org, andriy.shevchenko@linux.intel.com,
mgross@linux.intel.com, wan.ahmad.zainie.wan.mohamad@intel.com,
lakshmi.bai.raja.subramanian@intel.com,
vijayakannan.ayyathurai@intel.com
Subject: [PATCH v1 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC timer
Date: Thu, 26 Nov 2020 18:34:08 +0800 [thread overview]
Message-ID: <2938028520edbd0140805a22bdacd0b30c45b2df.1606377035.git.vijayakannan.ayyathurai@intel.com> (raw)
In-Reply-To: <cover.1606377035.git.vijayakannan.ayyathurai@intel.com>
In-Reply-To: <cover.1606377035.git.vijayakannan.ayyathurai@intel.com>
From: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
Add Device Tree bindings for the Timer IP, which used as clocksource and
clockevent in the Intel Keem Bay SoC.
Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
Acked-by: Mark Gross <mgross@linux.intel.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
.../bindings/timer/intel,keembay-timer.yaml | 72 +++++++++++++++++++
1 file changed, 72 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
diff --git a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
new file mode 100644
index 000000000000..396a698967ca
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel Keem Bay SoC Timers
+
+maintainers:
+ - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
+
+description:
+ Intel Keem Bay SoC Timers block contains 8 32-bit general purpose timers,
+ a free running 64-bit counter, a random number generator and a watchdog
+ timer. Each gpt can generate an individual interrupt.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ enum:
+ - intel,keembay-timer
+ - intel,keembay-counter
+
+ reg:
+ maxItems: 2
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - intel,keembay-timer
+ then:
+ properties:
+ interrupts:
+ maxItems: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #define KEEM_BAY_A53_TIM
+
+ timer@20330010 {
+ compatible = "intel,keembay-timer";
+ reg = <0x20330010 0xc>,
+ <0x20331000 0xc>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+ };
+
+ counter@203300e8 {
+ compatible = "intel,keembay-counter";
+ reg = <0x203300e8 0xc>,
+ <0x20331000 0xc>;
+ clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+ };
--
2.17.1
next prev parent reply other threads:[~2020-11-26 10:37 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-26 10:34 [PATCH v1 0/2] Add drivers for Intel Keem Bay SoC timer block vijayakannan.ayyathurai
2020-11-26 10:34 ` vijayakannan.ayyathurai [this message]
2020-12-08 16:12 ` [PATCH v1 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC timer Rob Herring
2020-12-08 18:12 ` Andy Shevchenko
2020-12-16 19:16 ` Ayyathurai, Vijayakannan
2020-11-26 10:34 ` [PATCH v1 2/2] clocksource: Add Intel Keem Bay Timer Support vijayakannan.ayyathurai
2020-12-03 18:09 ` Daniel Lezcano
2020-12-03 18:09 ` Daniel Lezcano
2020-12-04 4:09 ` Ayyathurai, Vijayakannan
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