* [PATCH v10 0/2] Add PWM support for Intel Keem Bay SoC @ 2020-10-07 17:40 vijayakannan.ayyathurai 2020-10-07 17:40 ` [PATCH v10 1/2] pwm: Add PWM driver for Intel Keem Bay vijayakannan.ayyathurai 2020-10-07 17:40 ` [PATCH v10 2/2] dt-bindings: pwm: keembay: Add bindings for Intel Keem Bay PWM vijayakannan.ayyathurai 0 siblings, 2 replies; 8+ messages in thread From: vijayakannan.ayyathurai @ 2020-10-07 17:40 UTC (permalink / raw) To: thierry.reding, u.kleine-koenig, robh+dt Cc: linux-pwm, devicetree, wan.ahmad.zainie.wan.mohamad, andriy.shevchenko, mgross, lakshmi.bai.raja.subramanian, vijayakannan.ayyathurai From: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> Hi, This patch set enables the support for PWM in the Intel Keem Bay SoC. Keem Bay is an ARM based SoC, and the GPIO module allows configuration of 6 PWM outputs. Patch 1 adds the PWM driver and Patch 2 is for the required Device Tree bindings documentation. This driver was tested on the Keem Bay evaluation module board. Thank you. Regards, Vijay Changes since v9: - Remove Reported-by tag from the commit log. Changes since v8: - Fix the compilation error reported by kernel test robot. - Add the tag Reported-by: kernel test robot <lkp@intel.com> - Minor correction in the pwm low time calculation formula. - Rebase with 5.9-rc7 Changes since v7: - Change the dependency as ARCH_KEEMBAY instead of ARM64 in Kconfig. - Use DIV_ROUND_DOWN_ULL instead of DIV_ROUND_CLOSEST_ULL. - Update the right formula as per Uwe. - List the tags in chronological order. - Add clk_disable_unprepare in the error paths. Changes since v6: - Add reviewed-by tag Changes since v5: - Reorder symbols/Kconfig in drivers/pwm/Kconfig and drivers/pwm/Makefile - Use "Limitations" for consistency - Add clk_prepare_enable() - Reorder keembay_pwm_get_state() function call - Rework if conditional for channel disablement in .apply() - Remove channel disabling from .probe(), and clear LEADIN register bits in .apply instead - Update commit message for Patch 1 Changes since v4: - Add co-developed-by tag - Include mod_devicetable.h and remove of.h - Update comment with correct calulation for high/low time - Fix missing return from dev_err_probe Changes since v3: - Removed variable for address and calculate in place instead - Utilized u32_replace_bits() when updating KMB_PWM_LEADIN_OFFSET - Utilized dev_err_probe() for error reporting - Updated comments to use physical units - Updated error check for pwmchip_add() Changes since v2: - Include documentation about HW limitation/behaviour - Use hex values for KMB_PWM_COUNT_MAX - Redefine register macros - Utilize FIELD_GET/FIELD_PREP for calculating pwm_l/h_count and pwm_count - Round up duty cycle/period values - Get current hardware state in .apply instead of cached values - Do a polarity check before .enabled - Round high time/low time to closest value - Set enable bit in KMB_PWM_LEADIN_OFFSET to 0 in probe - Correct the naming for MODULE_ALIAS - Add additionalProperties: false in DT bindings Changes since v1: - Updated licensing info, "clocks" property and example in DT bindings - Updated name of DT bindings document to match compatible string - Removed 1 patch for addition of new sysfs attribute "count" - Added support for COMPILE_TEST in Kconfig - Updated naming of defines and regmap attribute - Updated calculation of waveform high time and low time - Added range checking for waveform high/low time - Implemented .get_state - Removed register writes for lead-in and count values (left to default) - Updated register access to single-access - Folded keembay_pwm_enable/disable_channel, keembay_pwm_config_period/duty_cycle, and keembay_pwm_config into keembay_pwm_apply - Updated error messages/error codes - Removed pwm_disable from keembay_pwm_remove - Removed clk_prepare/clk_enable/clk_disable from driver Lai, Poey Seng (1): pwm: Add PWM driver for Intel Keem Bay Vineetha G. Jaya Kumaran (1): dt-bindings: pwm: keembay: Add bindings for Intel Keem Bay PWM .../bindings/pwm/intel,keembay-pwm.yaml | 47 ++++ drivers/pwm/Kconfig | 9 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-keembay.c | 230 ++++++++++++++++++ 4 files changed, 287 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml create mode 100644 drivers/pwm/pwm-keembay.c base-commit: 549738f15da0e5a00275977623be199fbbf7df50 prerequisite-patch-id: 0a348762b660d0d817b8e70cc71647e83173c78c prerequisite-patch-id: 0c6072cfe492b078c44ec864b8f9d1c76eada93b prerequisite-patch-id: 12b93428ee51a3d92ca973b928c0e0989f5d585e -- 2.17.1 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v10 1/2] pwm: Add PWM driver for Intel Keem Bay 2020-10-07 17:40 [PATCH v10 0/2] Add PWM support for Intel Keem Bay SoC vijayakannan.ayyathurai @ 2020-10-07 17:40 ` vijayakannan.ayyathurai 2020-10-07 20:57 ` Uwe Kleine-König 2020-10-07 17:40 ` [PATCH v10 2/2] dt-bindings: pwm: keembay: Add bindings for Intel Keem Bay PWM vijayakannan.ayyathurai 1 sibling, 1 reply; 8+ messages in thread From: vijayakannan.ayyathurai @ 2020-10-07 17:40 UTC (permalink / raw) To: thierry.reding, u.kleine-koenig, robh+dt Cc: linux-pwm, devicetree, wan.ahmad.zainie.wan.mohamad, andriy.shevchenko, mgross, lakshmi.bai.raja.subramanian, vijayakannan.ayyathurai From: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> The Intel Keem Bay SoC requires PWM support. Add the pwm-keembay driver to enable this. Signed-off-by: Lai, Poey Seng <poey.seng.lai@intel.com> Co-developed-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com> Signed-off-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> --- drivers/pwm/Kconfig | 9 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-keembay.c | 230 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 240 insertions(+) create mode 100644 drivers/pwm/pwm-keembay.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 7dbcf6973d33..6129a9dbbfa8 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -254,6 +254,15 @@ config PWM_JZ4740 To compile this driver as a module, choose M here: the module will be called pwm-jz4740. +config PWM_KEEMBAY + tristate "Intel Keem Bay PWM driver" + depends on ARCH_KEEMBAY || COMPILE_TEST + help + The platform driver for Intel Keem Bay PWM controller. + + To compile this driver as a module, choose M here: the module + will be called pwm-keembay. + config PWM_LP3943 tristate "TI/National Semiconductor LP3943 PWM support" depends on MFD_LP3943 diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 2c2ba0a03557..a1051122eb07 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_PWM_IMX27) += pwm-imx27.o obj-$(CONFIG_PWM_IMX_TPM) += pwm-imx-tpm.o obj-$(CONFIG_PWM_IQS620A) += pwm-iqs620a.o obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o +obj-$(CONFIG_PWM_KEEMBAY) += pwm-keembay.o obj-$(CONFIG_PWM_LP3943) += pwm-lp3943.o obj-$(CONFIG_PWM_LPC18XX_SCT) += pwm-lpc18xx-sct.o obj-$(CONFIG_PWM_LPC32XX) += pwm-lpc32xx.o diff --git a/drivers/pwm/pwm-keembay.c b/drivers/pwm/pwm-keembay.c new file mode 100644 index 000000000000..ff362520d3cd --- /dev/null +++ b/drivers/pwm/pwm-keembay.c @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Intel Keem Bay PWM driver + * + * Copyright (C) 2020 Intel Corporation + * Authors: Lai Poey Seng <poey.seng.lai@intel.com> + * Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com> + * + * Limitations: + * - Upon disabling a channel, the currently running + * period will not be completed. However, upon + * reconfiguration of the duty cycle/period, the + * currently running period will be completed first. + */ + +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pwm.h> +#include <linux/regmap.h> + +#define KMB_TOTAL_PWM_CHANNELS 6 +#define KMB_PWM_COUNT_MAX U16_MAX +#define KMB_PWM_EN_BIT BIT(31) + +/* Mask */ +#define KMB_PWM_HIGH_MASK GENMASK(31, 16) +#define KMB_PWM_LOW_MASK GENMASK(15, 0) +#define KMB_PWM_LEADIN_MASK GENMASK(30, 0) + +/* PWM Register offset */ +#define KMB_PWM_LEADIN_OFFSET(ch) (0x00 + 4 * (ch)) +#define KMB_PWM_HIGHLOW_OFFSET(ch) (0x20 + 4 * (ch)) + +struct keembay_pwm { + struct pwm_chip chip; + struct device *dev; + struct clk *clk; + void __iomem *base; +}; + +static inline struct keembay_pwm *to_keembay_pwm_dev(struct pwm_chip *chip) +{ + return container_of(chip, struct keembay_pwm, chip); +} + +static inline void keembay_pwm_update_bits(struct keembay_pwm *priv, u32 mask, + u32 val, u32 offset) +{ + u32 buff = readl(priv->base + offset); + + buff = u32_replace_bits(buff, val, mask); + writel(buff, priv->base + offset); +} + +static void keembay_pwm_enable(struct keembay_pwm *priv, int ch) +{ + keembay_pwm_update_bits(priv, KMB_PWM_EN_BIT, 1, + KMB_PWM_LEADIN_OFFSET(ch)); +} + +static void keembay_pwm_disable(struct keembay_pwm *priv, int ch) +{ + keembay_pwm_update_bits(priv, KMB_PWM_EN_BIT, 0, + KMB_PWM_LEADIN_OFFSET(ch)); +} + +static void keembay_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct keembay_pwm *priv = to_keembay_pwm_dev(chip); + unsigned long long pwm_h_count, pwm_l_count; + unsigned long clk_rate; + u32 buff; + + clk_rate = clk_get_rate(priv->clk); + + /* Read channel enabled status */ + buff = readl(priv->base + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm)); + if (buff & KMB_PWM_EN_BIT) + state->enabled = true; + else + state->enabled = false; + + /* Read period and duty cycle */ + buff = readl(priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm)); + pwm_l_count = FIELD_GET(KMB_PWM_LOW_MASK, buff) * NSEC_PER_SEC; + pwm_h_count = FIELD_GET(KMB_PWM_HIGH_MASK, buff) * NSEC_PER_SEC; + state->duty_cycle = DIV_ROUND_UP_ULL(pwm_h_count, clk_rate); + state->period = DIV_ROUND_UP_ULL(pwm_h_count + pwm_l_count, clk_rate); +} + +static int keembay_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct keembay_pwm *priv = to_keembay_pwm_dev(chip); + struct pwm_state current_state; + u16 pwm_h_count, pwm_l_count; + unsigned long long div; + unsigned long clk_rate; + u32 pwm_count = 0; + + if (state->polarity != PWM_POLARITY_NORMAL) + return -ENOSYS; + + keembay_pwm_update_bits(priv, KMB_PWM_LEADIN_MASK, 0, + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm)); + + keembay_pwm_get_state(chip, pwm, ¤t_state); + + if (!state->enabled) { + if (current_state.enabled) + keembay_pwm_disable(priv, pwm->hwpwm); + return 0; + } + + /* + * The upper 16 bits of the KMB_PWM_HIGHLOW_OFFSET register contain + * the high time of the waveform, while the last 16 bits contain + * the low time of the waveform, in terms of clock cycles. + * + * high time = clock rate * duty cycle + * low time = clock rate * (period - duty cycle) + */ + + clk_rate = clk_get_rate(priv->clk); + /* Configure waveform high time */ + div = clk_rate * state->duty_cycle; + div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC); + if (div > KMB_PWM_COUNT_MAX) + return -ERANGE; + + pwm_h_count = div; + /* Configure waveform low time */ + div = clk_rate * (state->period - state->duty_cycle); + div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC - pwm_h_count); + if (div > KMB_PWM_COUNT_MAX) + return -ERANGE; + + pwm_l_count = div; + + pwm_count = FIELD_PREP(KMB_PWM_HIGH_MASK, pwm_h_count) | + FIELD_PREP(KMB_PWM_LOW_MASK, pwm_l_count); + + writel(pwm_count, priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm)); + + if (state->enabled && !current_state.enabled) + keembay_pwm_enable(priv, pwm->hwpwm); + + return 0; +} + +static const struct pwm_ops keembay_pwm_ops = { + .owner = THIS_MODULE, + .apply = keembay_pwm_apply, + .get_state = keembay_pwm_get_state, +}; + +static int keembay_pwm_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct keembay_pwm *priv; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) + return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to get clock\n"); + + ret = clk_prepare_enable(priv->clk); + if (ret) + return ret; + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) { + clk_disable_unprepare(priv->clk); + return PTR_ERR(priv->base); + } + + priv->chip.base = -1; + priv->chip.dev = dev; + priv->chip.ops = &keembay_pwm_ops; + priv->chip.npwm = KMB_TOTAL_PWM_CHANNELS; + + ret = pwmchip_add(&priv->chip); + if (ret) { + dev_err(dev, "Failed to add PWM chip: %pe\n", ERR_PTR(ret)); + clk_disable_unprepare(priv->clk); + return ret; + } + + platform_set_drvdata(pdev, priv); + + return 0; +} + +static int keembay_pwm_remove(struct platform_device *pdev) +{ + struct keembay_pwm *priv = platform_get_drvdata(pdev); + + clk_disable_unprepare(priv->clk); + + return pwmchip_remove(&priv->chip); +} + +static const struct of_device_id keembay_pwm_of_match[] = { + { .compatible = "intel,keembay-pwm" }, + { } +}; +MODULE_DEVICE_TABLE(of, keembay_pwm_of_match); + +static struct platform_driver keembay_pwm_driver = { + .probe = keembay_pwm_probe, + .remove = keembay_pwm_remove, + .driver = { + .name = "pwm-keembay", + .of_match_table = keembay_pwm_of_match, + }, +}; +module_platform_driver(keembay_pwm_driver); + +MODULE_ALIAS("platform:pwm-keembay"); +MODULE_DESCRIPTION("Intel Keem Bay PWM driver"); +MODULE_LICENSE("GPL v2"); -- 2.17.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v10 1/2] pwm: Add PWM driver for Intel Keem Bay 2020-10-07 17:40 ` [PATCH v10 1/2] pwm: Add PWM driver for Intel Keem Bay vijayakannan.ayyathurai @ 2020-10-07 20:57 ` Uwe Kleine-König 2020-10-12 20:04 ` Ayyathurai, Vijayakannan 0 siblings, 1 reply; 8+ messages in thread From: Uwe Kleine-König @ 2020-10-07 20:57 UTC (permalink / raw) To: vijayakannan.ayyathurai Cc: thierry.reding, robh+dt, linux-pwm, devicetree, wan.ahmad.zainie.wan.mohamad, andriy.shevchenko, mgross, lakshmi.bai.raja.subramanian [-- Attachment #1: Type: text/plain, Size: 4403 bytes --] Hello, On Thu, Oct 08, 2020 at 01:40:30AM +0800, vijayakannan.ayyathurai@intel.com wrote: > +static int keembay_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > + const struct pwm_state *state) > +{ > + struct keembay_pwm *priv = to_keembay_pwm_dev(chip); > + struct pwm_state current_state; > + u16 pwm_h_count, pwm_l_count; > + unsigned long long div; > + unsigned long clk_rate; > + u32 pwm_count = 0; > + > + if (state->polarity != PWM_POLARITY_NORMAL) > + return -ENOSYS; > + > + keembay_pwm_update_bits(priv, KMB_PWM_LEADIN_MASK, 0, > + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm)); > + > + keembay_pwm_get_state(chip, pwm, ¤t_state); > + > + if (!state->enabled) { > + if (current_state.enabled) > + keembay_pwm_disable(priv, pwm->hwpwm); > + return 0; > + } > + > + /* > + * The upper 16 bits of the KMB_PWM_HIGHLOW_OFFSET register contain > + * the high time of the waveform, while the last 16 bits contain > + * the low time of the waveform, in terms of clock cycles. > + * > + * high time = clock rate * duty cycle > + * low time = clock rate * (period - duty cycle) > + */ > + > + clk_rate = clk_get_rate(priv->clk); > + /* Configure waveform high time */ > + div = clk_rate * state->duty_cycle; > + div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC); > + if (div > KMB_PWM_COUNT_MAX) > + return -ERANGE; > + > + pwm_h_count = div; > + /* Configure waveform low time */ > + div = clk_rate * (state->period - state->duty_cycle); > + div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC - pwm_h_count); In reply to your v7 I suggested the example: clk_rate = 333334 [Hz] state.duty_cycle = 1000500 [ns] state.period = 2001000 [ns] where the expected outcome is pwm_h_count = 333 pwm_l_count = 334 . Please reread my feedback there. I tried to construct an example where the value is more wrong, but with the constraint that pwm_h_count must be <= KMB_PWM_COUNT_MAX this isn't easy. The best I could come up with is: clk_rate = 1000000000 state.duty_cycle = 65535 [ns] state.period = 131070 [ns] where the right value for pwm_l_count is 65535 while you calculate 65539 (and then quit with -ERANGE). > + if (div > KMB_PWM_COUNT_MAX) > + return -ERANGE; > + > + pwm_l_count = div; > + > + pwm_count = FIELD_PREP(KMB_PWM_HIGH_MASK, pwm_h_count) | > + FIELD_PREP(KMB_PWM_LOW_MASK, pwm_l_count); > + > + writel(pwm_count, priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm)); > + > + if (state->enabled && !current_state.enabled) > + keembay_pwm_enable(priv, pwm->hwpwm); > + > + return 0; > +} > + > +static const struct pwm_ops keembay_pwm_ops = { > + .owner = THIS_MODULE, > + .apply = keembay_pwm_apply, > + .get_state = keembay_pwm_get_state, > +}; > + > +static int keembay_pwm_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct keembay_pwm *priv; > + int ret; > + > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + priv->clk = devm_clk_get(dev, NULL); > + if (IS_ERR(priv->clk)) > + return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to get clock\n"); > + > + ret = clk_prepare_enable(priv->clk); > + if (ret) > + return ret; > + > + priv->base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(priv->base)) { > + clk_disable_unprepare(priv->clk); > + return PTR_ERR(priv->base); > + } > + > + priv->chip.base = -1; > + priv->chip.dev = dev; > + priv->chip.ops = &keembay_pwm_ops; > + priv->chip.npwm = KMB_TOTAL_PWM_CHANNELS; > + > + ret = pwmchip_add(&priv->chip); > + if (ret) { > + dev_err(dev, "Failed to add PWM chip: %pe\n", ERR_PTR(ret)); > + clk_disable_unprepare(priv->clk); > + return ret; > + } > + > + platform_set_drvdata(pdev, priv); > + > + return 0; > +} > + > +static int keembay_pwm_remove(struct platform_device *pdev) > +{ > + struct keembay_pwm *priv = platform_get_drvdata(pdev); > + > + clk_disable_unprepare(priv->clk); > + > + return pwmchip_remove(&priv->chip); You have to call pwmchip_remove first. Otherwise you're stopping the PWM while the framework still believes everything to be fine. > +} Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | https://www.pengutronix.de/ | [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH v10 1/2] pwm: Add PWM driver for Intel Keem Bay 2020-10-07 20:57 ` Uwe Kleine-König @ 2020-10-12 20:04 ` Ayyathurai, Vijayakannan 2020-10-12 21:01 ` Uwe Kleine-König 0 siblings, 1 reply; 8+ messages in thread From: Ayyathurai, Vijayakannan @ 2020-10-12 20:04 UTC (permalink / raw) To: Uwe Kleine-König Cc: thierry.reding, robh+dt, linux-pwm, devicetree, Wan Mohamad, Wan Ahmad Zainie, andriy.shevchenko, mgross, Raja Subramanian, Lakshmi Bai Hi Uwe, Thank you for constructing example to explain the review comment. -----Original Message----- From: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Sent: Thursday, 8 October, 2020 2:28 AM Subject: Re: [PATCH v10 1/2] pwm: Add PWM driver for Intel Keem Bay Hello, On Thu, Oct 08, 2020 at 01:40:30AM +0800, vijayakannan.ayyathurai@intel.com wrote: > +static int keembay_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > + const struct pwm_state *state) { > + struct keembay_pwm *priv = to_keembay_pwm_dev(chip); > + struct pwm_state current_state; > + u16 pwm_h_count, pwm_l_count; > + unsigned long long div; > + unsigned long clk_rate; > + u32 pwm_count = 0; > + > + if (state->polarity != PWM_POLARITY_NORMAL) > + return -ENOSYS; > + > + keembay_pwm_update_bits(priv, KMB_PWM_LEADIN_MASK, 0, > + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm)); > + > + keembay_pwm_get_state(chip, pwm, ¤t_state); > + > + if (!state->enabled) { > + if (current_state.enabled) > + keembay_pwm_disable(priv, pwm->hwpwm); > + return 0; > + } > + > + /* > + * The upper 16 bits of the KMB_PWM_HIGHLOW_OFFSET register contain > + * the high time of the waveform, while the last 16 bits contain > + * the low time of the waveform, in terms of clock cycles. > + * > + * high time = clock rate * duty cycle > + * low time = clock rate * (period - duty cycle) > + */ > + > + clk_rate = clk_get_rate(priv->clk); > + /* Configure waveform high time */ > + div = clk_rate * state->duty_cycle; > + div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC); > + if (div > KMB_PWM_COUNT_MAX) > + return -ERANGE; > + > + pwm_h_count = div; > + /* Configure waveform low time */ > + div = clk_rate * (state->period - state->duty_cycle); > + div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC - pwm_h_count); In reply to your v7 I suggested the example: clk_rate = 333334 [Hz] state.duty_cycle = 1000500 [ns] state.period = 2001000 [ns] where the expected outcome is pwm_h_count = 333 pwm_l_count = 334 . Please reread my feedback there. I tried to construct an example where the value is more wrong, but with the constraint that pwm_h_count must be <= KMB_PWM_COUNT_MAX this isn't easy. The best I could come up with is: clk_rate = 1000000000 state.duty_cycle = 65535 [ns] state.period = 131070 [ns] where the right value for pwm_l_count is 65535 while you calculate 65539 (and then quit with -ERANGE). I have applied the formula mentioned in v7 and got different duty cycle result then what was expected. Formula referred by Uwe at v7: pwm_l_count = (clk_rate * state->period) / NSEC_PER_SEC - pwm_h_count % clk_rate period duty_cycle NSEC_PER_SEC pwm_h_count pwm_l_count 50% 333334 2001000 1000500 1000000000 333 667 25% 500000000 20000 5000 1000000000 2500 10000 50% 100000000 131070 65535 1000000000 6553 13107 Whereas the below table is the result of minor modification from your formula and getting the right result. pwm_l_count = clk_rate * (state->period - state->duty_cycle) / NSEC_PER_SEC - pwm_h_count % clk_rate period duty_cycle NSEC_PER_SEC pwm_h_count pwm_l_count 50% 333334 2001000 1000500 1000000000 333 333 25% 500000000 20000 5000 1000000000 2500 7500 50% 100000000 131070 65535 1000000000 6553 6553 Please review this and confirm. > + if (div > KMB_PWM_COUNT_MAX) > + return -ERANGE; > + > + pwm_l_count = div; > + > + pwm_count = FIELD_PREP(KMB_PWM_HIGH_MASK, pwm_h_count) | > + FIELD_PREP(KMB_PWM_LOW_MASK, pwm_l_count); > + > + writel(pwm_count, priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm)); > + > + if (state->enabled && !current_state.enabled) > + keembay_pwm_enable(priv, pwm->hwpwm); > + > + return 0; > +} > + > +static const struct pwm_ops keembay_pwm_ops = { > + .owner = THIS_MODULE, > + .apply = keembay_pwm_apply, > + .get_state = keembay_pwm_get_state, > +}; > + > +static int keembay_pwm_probe(struct platform_device *pdev) { > + struct device *dev = &pdev->dev; > + struct keembay_pwm *priv; > + int ret; > + > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + priv->clk = devm_clk_get(dev, NULL); > + if (IS_ERR(priv->clk)) > + return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to get > +clock\n"); > + > + ret = clk_prepare_enable(priv->clk); > + if (ret) > + return ret; > + > + priv->base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(priv->base)) { > + clk_disable_unprepare(priv->clk); > + return PTR_ERR(priv->base); > + } > + > + priv->chip.base = -1; > + priv->chip.dev = dev; > + priv->chip.ops = &keembay_pwm_ops; > + priv->chip.npwm = KMB_TOTAL_PWM_CHANNELS; > + > + ret = pwmchip_add(&priv->chip); > + if (ret) { > + dev_err(dev, "Failed to add PWM chip: %pe\n", ERR_PTR(ret)); > + clk_disable_unprepare(priv->clk); > + return ret; > + } > + > + platform_set_drvdata(pdev, priv); > + > + return 0; > +} > + > +static int keembay_pwm_remove(struct platform_device *pdev) { > + struct keembay_pwm *priv = platform_get_drvdata(pdev); > + > + clk_disable_unprepare(priv->clk); > + > + return pwmchip_remove(&priv->chip); You have to call pwmchip_remove first. Otherwise you're stopping the PWM while the framework still believes everything to be fine. I will incorporate the change in next version. > +} Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | https://www.pengutronix.de/ | ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v10 1/2] pwm: Add PWM driver for Intel Keem Bay 2020-10-12 20:04 ` Ayyathurai, Vijayakannan @ 2020-10-12 21:01 ` Uwe Kleine-König 2020-10-13 2:54 ` Ayyathurai, Vijayakannan 0 siblings, 1 reply; 8+ messages in thread From: Uwe Kleine-König @ 2020-10-12 21:01 UTC (permalink / raw) To: Ayyathurai, Vijayakannan Cc: thierry.reding, robh+dt, linux-pwm, devicetree, Wan Mohamad, Wan Ahmad Zainie, andriy.shevchenko, mgross, Raja Subramanian, Lakshmi Bai [-- Attachment #1: Type: text/plain, Size: 4949 bytes --] Hello Ayyathurai, you're quoting style is strange. I fixed it up and hope I got it right. On Mon, Oct 12, 2020 at 08:04:47PM +0000, Ayyathurai, Vijayakannan wrote: > > On Thu, Oct 08, 2020 at 01:40:30AM +0800, vijayakannan.ayyathurai@intel.com wrote: > > > +static int keembay_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > > > + const struct pwm_state *state) { > > > + struct keembay_pwm *priv = to_keembay_pwm_dev(chip); > > > + struct pwm_state current_state; > > > + u16 pwm_h_count, pwm_l_count; > > > + unsigned long long div; > > > + unsigned long clk_rate; > > > + u32 pwm_count = 0; > > > + > > > + if (state->polarity != PWM_POLARITY_NORMAL) > > > + return -ENOSYS; > > > + > > > + keembay_pwm_update_bits(priv, KMB_PWM_LEADIN_MASK, 0, > > > + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm)); > > > + > > > + keembay_pwm_get_state(chip, pwm, ¤t_state); > > > + > > > + if (!state->enabled) { > > > + if (current_state.enabled) > > > + keembay_pwm_disable(priv, pwm->hwpwm); > > > + return 0; > > > + } > > > + > > > + /* > > > + * The upper 16 bits of the KMB_PWM_HIGHLOW_OFFSET register contain > > > + * the high time of the waveform, while the last 16 bits contain > > > + * the low time of the waveform, in terms of clock cycles. > > > + * > > > + * high time = clock rate * duty cycle > > > + * low time = clock rate * (period - duty cycle) > > > + */ > > > + > > > + clk_rate = clk_get_rate(priv->clk); > > > + /* Configure waveform high time */ > > > + div = clk_rate * state->duty_cycle; > > > + div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC); > > > + if (div > KMB_PWM_COUNT_MAX) > > > + return -ERANGE; > > > + > > > + pwm_h_count = div; > > > + /* Configure waveform low time */ > > > + div = clk_rate * (state->period - state->duty_cycle); > > > + div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC - pwm_h_count); > > > > In reply to your v7 I suggested the example: > > > > clk_rate = 333334 [Hz] > > state.duty_cycle = 1000500 [ns] > > state.period = 2001000 [ns] > > > > where the expected outcome is > > > > pwm_h_count = 333 > > pwm_l_count = 334 > > > > . Please reread my feedback there. I tried to construct an example > > where the value is more wrong, but with the constraint that > > pwm_h_count must be <= KMB_PWM_COUNT_MAX this isn't easy. The best I > > could come up with is: > > > > clk_rate = 1000000000 > > state.duty_cycle = 65535 [ns] > > state.period = 131070 [ns] > > > > where the right value for pwm_l_count is 65535 while you calculate > > 65539 (and then quit with -ERANGE). > > I have applied the formula mentioned in v7 and got different duty > cycle result then what was expected. > > Formula referred by Uwe at v7: > pwm_l_count = (clk_rate * state->period) / NSEC_PER_SEC - pwm_h_count > > % clk_rate period duty_cycle NSEC_PER_SEC pwm_h_count pwm_l_count > 50% 333334 2001000 1000500 1000000000 333 667 > 25% 500000000 20000 5000 1000000000 2500 10000 > 50% 100000000 131070 65535 1000000000 6553 13107 For the first line: (clk_rate * state->period) // NSEC_PER_SEC - pwm_h_count = (333334 * 2001000) // 1000000000 - 333 = 667.001334 - 333 = 334 This gives duty cycle = 333 * 1000000000 / 333334 = 998998.0020039959 ns and a period = (333 + 334) * 1000000000 / 333334 = 2000995.998008004 ns which is well in the limits. I guess you assumed my formula to be (clk_rate * state->period) / (NSEC_PER_SEC - pwm_h_count), but that's not what I meant. > Whereas the below table is the result of minor modification from your formula and getting the right result. > pwm_l_count = clk_rate * (state->period - state->duty_cycle) / NSEC_PER_SEC - pwm_h_count > > % clk_rate period duty_cycle NSEC_PER_SEC pwm_h_count pwm_l_count > 50% 333334 2001000 1000500 1000000000 333 333 > 25% 500000000 20000 5000 1000000000 2500 7500 > 50% 100000000 131070 65535 1000000000 6553 6553 > > Please review this and confirm. In the code you used clk_rate * (state->period - state->duty_cycle) / (NSEC_PER_SEC - pwm_h_count) which is notably different. For the example in the first line again you then get 333, which is a less optimal result than 334 I get with my (fixed) formula. I'm still convinced my formula is the right and optimal one. Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | https://www.pengutronix.de/ | [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH v10 1/2] pwm: Add PWM driver for Intel Keem Bay 2020-10-12 21:01 ` Uwe Kleine-König @ 2020-10-13 2:54 ` Ayyathurai, Vijayakannan 2020-10-13 8:32 ` Uwe Kleine-König 0 siblings, 1 reply; 8+ messages in thread From: Ayyathurai, Vijayakannan @ 2020-10-13 2:54 UTC (permalink / raw) To: Uwe Kleine-König Cc: thierry.reding, robh+dt, linux-pwm, devicetree, Wan Mohamad, Wan Ahmad Zainie, andriy.shevchenko, mgross, Raja Subramanian, Lakshmi Bai Hi Uwe, -----Original Message----- From: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Sent: Tuesday, 13 October, 2020 2:31 AM Subject: Re: [PATCH v10 1/2] pwm: Add PWM driver for Intel Keem Bay Hello Ayyathurai, you're quoting style is strange. I fixed it up and hope I got it right. On Mon, Oct 12, 2020 at 08:04:47PM +0000, Ayyathurai, Vijayakannan wrote: > > On Thu, Oct 08, 2020 at 01:40:30AM +0800, vijayakannan.ayyathurai@intel.com wrote: > > > +static int keembay_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > > > + const struct pwm_state *state) { > > > + struct keembay_pwm *priv = to_keembay_pwm_dev(chip); > > > + struct pwm_state current_state; > > > + u16 pwm_h_count, pwm_l_count; > > > + unsigned long long div; > > > + unsigned long clk_rate; > > > + u32 pwm_count = 0; > > > + > > > + if (state->polarity != PWM_POLARITY_NORMAL) > > > + return -ENOSYS; > > > + > > > + keembay_pwm_update_bits(priv, KMB_PWM_LEADIN_MASK, 0, > > > + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm)); > > > + > > > + keembay_pwm_get_state(chip, pwm, ¤t_state); > > > + > > > + if (!state->enabled) { > > > + if (current_state.enabled) > > > + keembay_pwm_disable(priv, pwm->hwpwm); > > > + return 0; > > > + } > > > + > > > + /* > > > + * The upper 16 bits of the KMB_PWM_HIGHLOW_OFFSET register contain > > > + * the high time of the waveform, while the last 16 bits contain > > > + * the low time of the waveform, in terms of clock cycles. > > > + * > > > + * high time = clock rate * duty cycle > > > + * low time = clock rate * (period - duty cycle) > > > + */ > > > + > > > + clk_rate = clk_get_rate(priv->clk); > > > + /* Configure waveform high time */ > > > + div = clk_rate * state->duty_cycle; > > > + div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC); > > > + if (div > KMB_PWM_COUNT_MAX) > > > + return -ERANGE; > > > + > > > + pwm_h_count = div; > > > + /* Configure waveform low time */ > > > + div = clk_rate * (state->period - state->duty_cycle); > > > + div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC - pwm_h_count); > > > > In reply to your v7 I suggested the example: > > > > clk_rate = 333334 [Hz] > > state.duty_cycle = 1000500 [ns] > > state.period = 2001000 [ns] > > > > where the expected outcome is > > > > pwm_h_count = 333 > > pwm_l_count = 334 > > > > . Please reread my feedback there. I tried to construct an example > > where the value is more wrong, but with the constraint that > > pwm_h_count must be <= KMB_PWM_COUNT_MAX this isn't easy. The best I > > could come up with is: > > > > clk_rate = 1000000000 > > state.duty_cycle = 65535 [ns] > > state.period = 131070 [ns] > > > > where the right value for pwm_l_count is 65535 while you calculate > > 65539 (and then quit with -ERANGE). > > I have applied the formula mentioned in v7 and got different duty > cycle result then what was expected. > > Formula referred by Uwe at v7: > pwm_l_count = (clk_rate * state->period) / NSEC_PER_SEC - pwm_h_count > > % clk_rate period duty_cycle NSEC_PER_SEC pwm_h_count pwm_l_count > 50% 333334 2001000 1000500 1000000000 333 667 > 25% 500000000 20000 5000 1000000000 2500 10000 > 50% 100000000 131070 65535 1000000000 6553 13107 For the first line: (clk_rate * state->period) // NSEC_PER_SEC - pwm_h_count = (333334 * 2001000) // 1000000000 - 333 = 667.001334 - 333 = 334 This gives duty cycle = 333 * 1000000000 / 333334 = 998998.0020039959 ns and a period = (333 + 334) * 1000000000 / 333334 = 2000995.998008004 ns which is well in the limits. Thank you for this clarification and I am clear in incorporating it in my next version. Is there any other feedback in this version v10? I guess you assumed my formula to be (clk_rate * state->period) / (NSEC_PER_SEC - pwm_h_count), but that's not what I meant. > Whereas the below table is the result of minor modification from your formula and getting the right result. > pwm_l_count = clk_rate * (state->period - state->duty_cycle) / > NSEC_PER_SEC - pwm_h_count > > % clk_rate period duty_cycle NSEC_PER_SEC pwm_h_count pwm_l_count > 50% 333334 2001000 1000500 1000000000 333 333 > 25% 500000000 20000 5000 1000000000 2500 7500 > 50% 100000000 131070 65535 1000000000 6553 6553 > > Please review this and confirm. In the code you used clk_rate * (state->period - state->duty_cycle) / (NSEC_PER_SEC - pwm_h_count) which is notably different. For the example in the first line again you then get 333, which is a less optimal result than 334 I get with my (fixed) formula. I'm still convinced my formula is the right and optimal one. Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | https://www.pengutronix.de/ | Thanks, Vijay ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v10 1/2] pwm: Add PWM driver for Intel Keem Bay 2020-10-13 2:54 ` Ayyathurai, Vijayakannan @ 2020-10-13 8:32 ` Uwe Kleine-König 0 siblings, 0 replies; 8+ messages in thread From: Uwe Kleine-König @ 2020-10-13 8:32 UTC (permalink / raw) To: Ayyathurai, Vijayakannan Cc: thierry.reding, robh+dt, linux-pwm, devicetree, Wan Mohamad, Wan Ahmad Zainie, andriy.shevchenko, mgross, Raja Subramanian, Lakshmi Bai [-- Attachment #1: Type: text/plain, Size: 594 bytes --] Hello Ayyathurai, can you please fix your mailer to quote properly? On Tue, Oct 13, 2020 at 02:54:31AM +0000, Ayyathurai, Vijayakannan wrote: > Thank you for this clarification and I am clear in incorporating it in > my next version. Is there any other feedback in this version v10? I won't promise that I will not spot something in your v11, but currently I told you about all issues I saw with v10. Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | https://www.pengutronix.de/ | [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v10 2/2] dt-bindings: pwm: keembay: Add bindings for Intel Keem Bay PWM 2020-10-07 17:40 [PATCH v10 0/2] Add PWM support for Intel Keem Bay SoC vijayakannan.ayyathurai 2020-10-07 17:40 ` [PATCH v10 1/2] pwm: Add PWM driver for Intel Keem Bay vijayakannan.ayyathurai @ 2020-10-07 17:40 ` vijayakannan.ayyathurai 1 sibling, 0 replies; 8+ messages in thread From: vijayakannan.ayyathurai @ 2020-10-07 17:40 UTC (permalink / raw) To: thierry.reding, u.kleine-koenig, robh+dt Cc: linux-pwm, devicetree, wan.ahmad.zainie.wan.mohamad, andriy.shevchenko, mgross, lakshmi.bai.raja.subramanian, vijayakannan.ayyathurai From: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> Add PWM Device Tree bindings documentation for the Intel Keem Bay SoC. Signed-off-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> --- .../bindings/pwm/intel,keembay-pwm.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml b/Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml new file mode 100644 index 000000000000..a37433487632 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Intel Corporation +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/intel,keembay-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay PWM Device Tree Bindings + +maintainers: + - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com> + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + enum: + - intel,keembay-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 2 + +required: + - compatible + - reg + - clocks + - '#pwm-cells' + +additionalProperties: false + +examples: + - | + #define KEEM_BAY_A53_GPIO + + pwm@203200a0 { + compatible = "intel,keembay-pwm"; + reg = <0x203200a0 0xe8>; + clocks = <&scmi_clk KEEM_BAY_A53_GPIO>; + #pwm-cells = <2>; + }; -- 2.17.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-10-13 8:32 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-10-07 17:40 [PATCH v10 0/2] Add PWM support for Intel Keem Bay SoC vijayakannan.ayyathurai 2020-10-07 17:40 ` [PATCH v10 1/2] pwm: Add PWM driver for Intel Keem Bay vijayakannan.ayyathurai 2020-10-07 20:57 ` Uwe Kleine-König 2020-10-12 20:04 ` Ayyathurai, Vijayakannan 2020-10-12 21:01 ` Uwe Kleine-König 2020-10-13 2:54 ` Ayyathurai, Vijayakannan 2020-10-13 8:32 ` Uwe Kleine-König 2020-10-07 17:40 ` [PATCH v10 2/2] dt-bindings: pwm: keembay: Add bindings for Intel Keem Bay PWM vijayakannan.ayyathurai
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