* [v6 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280
[not found] <1628577962-3995-1-git-send-email-okukatla@codeaurora.org>
@ 2021-08-10 6:46 ` Odelu Kukatla
2021-08-16 18:09 ` Sibi Sankar
2021-08-10 6:46 ` [v6 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla
1 sibling, 1 reply; 5+ messages in thread
From: Odelu Kukatla @ 2021-08-10 6:46 UTC (permalink / raw)
To: georgi.djakov, bjorn.andersson, evgreen, Andy Gross,
Georgi Djakov, Rob Herring, Sibi Sankar, linux-arm-msm, linux-pm,
devicetree, linux-kernel
Cc: sboyd, mdtipton, saravanak, okukatla, seansw, elder, linux-arm-msm-owner
Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280
SoCs.
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
---
.../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 9 ++++++++-
include/dt-bindings/interconnect/qcom,osm-l3.h | 10 +++++++++-
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
index e701524..919fce4 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
@@ -18,13 +18,20 @@ properties:
compatible:
enum:
- qcom,sc7180-osm-l3
+ - qcom,sc7280-epss-l3
- qcom,sc8180x-osm-l3
- qcom,sdm845-osm-l3
- qcom,sm8150-osm-l3
- qcom,sm8250-epss-l3
reg:
- maxItems: 1
+ minItems: 1
+ maxItems: 4
+ items:
+ - description: OSM clock domain-0 base address and size
+ - description: OSM clock domain-1 base address and size
+ - description: OSM clock domain-2 base address and size
+ - description: OSM clock domain-3 base address and size
clocks:
items:
diff --git a/include/dt-bindings/interconnect/qcom,osm-l3.h b/include/dt-bindings/interconnect/qcom,osm-l3.h
index 61ef649..99534a5 100644
--- a/include/dt-bindings/interconnect/qcom,osm-l3.h
+++ b/include/dt-bindings/interconnect/qcom,osm-l3.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2019 The Linux Foundation. All rights reserved.
+ * Copyright (C) 2019, 2021 The Linux Foundation. All rights reserved.
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H
@@ -11,5 +11,13 @@
#define MASTER_EPSS_L3_APPS 0
#define SLAVE_EPSS_L3_SHARED 1
+#define SLAVE_EPSS_L3_CPU0 2
+#define SLAVE_EPSS_L3_CPU1 3
+#define SLAVE_EPSS_L3_CPU2 4
+#define SLAVE_EPSS_L3_CPU3 5
+#define SLAVE_EPSS_L3_CPU4 6
+#define SLAVE_EPSS_L3_CPU5 7
+#define SLAVE_EPSS_L3_CPU6 8
+#define SLAVE_EPSS_L3_CPU7 9
#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [v6 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider
[not found] <1628577962-3995-1-git-send-email-okukatla@codeaurora.org>
2021-08-10 6:46 ` [v6 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla
@ 2021-08-10 6:46 ` Odelu Kukatla
2021-08-10 12:33 ` Georgi Djakov
1 sibling, 1 reply; 5+ messages in thread
From: Odelu Kukatla @ 2021-08-10 6:46 UTC (permalink / raw)
To: georgi.djakov, bjorn.andersson, evgreen, Andy Gross, Rob Herring,
linux-arm-msm, devicetree, linux-kernel
Cc: sboyd, mdtipton, sibis, saravanak, okukatla, seansw, elder,
linux-pm, linux-arm-msm-owner
Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
SoCs.
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 53a21d0..e78f055 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -586,6 +586,15 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ epss_l3: interconnect@18590000 {
+ compatible = "qcom,sc7280-epss-l3";
+ reg = <0 0x18590000 0 1000>, <0 0x18591000 0 0x100>,
+ <0 0x18592000 0 0x100>, <0 0x18593000 0 0x100>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+ #interconnect-cells = <1>;
+ };
+
ipa: ipa@1e40000 {
compatible = "qcom,sc7280-ipa";
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [v6 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider
2021-08-10 6:46 ` [v6 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla
@ 2021-08-10 12:33 ` Georgi Djakov
2021-08-16 17:44 ` okukatla
0 siblings, 1 reply; 5+ messages in thread
From: Georgi Djakov @ 2021-08-10 12:33 UTC (permalink / raw)
To: Odelu Kukatla, georgi.djakov, bjorn.andersson, evgreen,
Andy Gross, Rob Herring, linux-arm-msm, devicetree, linux-kernel
Cc: sboyd, mdtipton, sibis, saravanak, seansw, elder, linux-pm,
linux-arm-msm-owner
Hi Odelu,
On 10.08.21 9:46, Odelu Kukatla wrote:
> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
> SoCs.
>
> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 53a21d0..e78f055 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -586,6 +586,15 @@
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> + epss_l3: interconnect@18590000 {
This DT node should be moved after apps_rsc: rsc@18200000
and before cpufreq@18591000
> + compatible = "qcom,sc7280-epss-l3";
> + reg = <0 0x18590000 0 1000>, <0 0x18591000 0 0x100>,
> + <0 0x18592000 0 0x100>, <0 0x18593000 0 0x100>;
Please align to the open parenthesis, to be consistent with the rest of
the file.
> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
> + clock-names = "xo", "alternate";
> + #interconnect-cells = <1>;
> + };
> +
> ipa: ipa@1e40000 {
> compatible = "qcom,sc7280-ipa";
Thanks,
Georgi
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [v6 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider
2021-08-10 12:33 ` Georgi Djakov
@ 2021-08-16 17:44 ` okukatla
0 siblings, 0 replies; 5+ messages in thread
From: okukatla @ 2021-08-16 17:44 UTC (permalink / raw)
To: Georgi Djakov
Cc: georgi.djakov, bjorn.andersson, evgreen, Andy Gross, Rob Herring,
linux-arm-msm, devicetree, linux-kernel, sboyd, mdtipton, sibis,
saravanak, seansw, elder, linux-pm, linux-arm-msm-owner
On 2021-08-10 18:03, Georgi Djakov wrote:
> Hi Odelu,
>
> On 10.08.21 9:46, Odelu Kukatla wrote:
>> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
>> SoCs.
>>
>> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
>> ---
>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++++
>> 1 file changed, 9 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 53a21d0..e78f055 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -586,6 +586,15 @@
>> qcom,bcm-voters = <&apps_bcm_voter>;
>> };
>> + epss_l3: interconnect@18590000 {
>
> This DT node should be moved after apps_rsc: rsc@18200000
> and before cpufreq@18591000
>
Thanks for review! will address this in next revision.
>> + compatible = "qcom,sc7280-epss-l3";
>> + reg = <0 0x18590000 0 1000>, <0 0x18591000 0 0x100>,
>> + <0 0x18592000 0 0x100>, <0 0x18593000 0 0x100>;
>
> Please align to the open parenthesis, to be consistent with the rest of
> the file.
>
will address this in next revision.
>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
>> + clock-names = "xo", "alternate";
>> + #interconnect-cells = <1>;
>> + };
>> +
>> ipa: ipa@1e40000 {
>> compatible = "qcom,sc7280-ipa";
>
> Thanks,
> Georgi
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [v6 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280
2021-08-10 6:46 ` [v6 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla
@ 2021-08-16 18:09 ` Sibi Sankar
0 siblings, 0 replies; 5+ messages in thread
From: Sibi Sankar @ 2021-08-16 18:09 UTC (permalink / raw)
To: Odelu Kukatla
Cc: georgi.djakov, bjorn.andersson, evgreen, Andy Gross,
Georgi Djakov, Rob Herring, linux-arm-msm, linux-pm, devicetree,
linux-kernel, sboyd, mdtipton, saravanak, seansw, elder,
linux-arm-msm-owner
Hey Odelu,
Thanks for the patch.
On 2021-08-10 12:16, Odelu Kukatla wrote:
> Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280
> SoCs.
>
> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
> ---
> .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 9
> ++++++++-
> include/dt-bindings/interconnect/qcom,osm-l3.h | 10
> +++++++++-
> 2 files changed, 17 insertions(+), 2 deletions(-)
>
> diff --git
> a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> index e701524..919fce4 100644
> --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
> @@ -18,13 +18,20 @@ properties:
> compatible:
> enum:
> - qcom,sc7180-osm-l3
> + - qcom,sc7280-epss-l3
> - qcom,sc8180x-osm-l3
> - qcom,sdm845-osm-l3
> - qcom,sm8150-osm-l3
> - qcom,sm8250-epss-l3
>
> reg:
> - maxItems: 1
> + minItems: 1
> + maxItems: 4
> + items:
> + - description: OSM clock domain-0 base address and size
> + - description: OSM clock domain-1 base address and size
> + - description: OSM clock domain-2 base address and size
> + - description: OSM clock domain-3 base address and size
Looks like you missed addressing
Stephen's comment from v4 i.e.
having descriptions based on
compatibles.
>
> clocks:
> items:
> diff --git a/include/dt-bindings/interconnect/qcom,osm-l3.h
> b/include/dt-bindings/interconnect/qcom,osm-l3.h
> index 61ef649..99534a5 100644
> --- a/include/dt-bindings/interconnect/qcom,osm-l3.h
> +++ b/include/dt-bindings/interconnect/qcom,osm-l3.h
> @@ -1,6 +1,6 @@
> /* SPDX-License-Identifier: GPL-2.0 */
> /*
> - * Copyright (C) 2019 The Linux Foundation. All rights reserved.
> + * Copyright (C) 2019, 2021 The Linux Foundation. All rights reserved.
> */
>
> #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H
> @@ -11,5 +11,13 @@
>
> #define MASTER_EPSS_L3_APPS 0
> #define SLAVE_EPSS_L3_SHARED 1
> +#define SLAVE_EPSS_L3_CPU0 2
> +#define SLAVE_EPSS_L3_CPU1 3
> +#define SLAVE_EPSS_L3_CPU2 4
> +#define SLAVE_EPSS_L3_CPU3 5
> +#define SLAVE_EPSS_L3_CPU4 6
> +#define SLAVE_EPSS_L3_CPU5 7
> +#define SLAVE_EPSS_L3_CPU6 8
> +#define SLAVE_EPSS_L3_CPU7 9
>
> #endif
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [flat|nested] 5+ messages in thread
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[not found] <1628577962-3995-1-git-send-email-okukatla@codeaurora.org>
2021-08-10 6:46 ` [v6 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla
2021-08-16 18:09 ` Sibi Sankar
2021-08-10 6:46 ` [v6 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla
2021-08-10 12:33 ` Georgi Djakov
2021-08-16 17:44 ` okukatla
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