From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
To: Arnd Bergmann <arnd@arndb.de>
Cc: "Conor Dooley" <conor@kernel.org>,
"Geert Uytterhoeven" <geert+renesas@glider.be>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Rob Herring" <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Magnus Damm" <magnus.damm@gmail.com>,
"Heiko Stübner" <heiko@sntech.de>, guoren <guoren@kernel.org>,
"Conor.Dooley" <conor.dooley@microchip.com>,
"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
"Nathan Chancellor" <nathan@kernel.org>,
"Atish Patra" <atishp@rivosinc.com>,
"Anup Patel" <apatel@ventanamicro.com>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org,
"Biju Das" <biju.das.jz@bp.renesas.com>,
"Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [RFC PATCH v2 2/2] soc: renesas: Add L2 cache management for RZ/Five SoC
Date: Wed, 5 Oct 2022 11:14:22 +0100 [thread overview]
Message-ID: <CA+V-a8uxuMPr+Jwizn13FjGYtnStG7Nw_MCRkdSz6y9HoEeA=Q@mail.gmail.com> (raw)
In-Reply-To: <e7340230-9a5b-4caf-a7b0-d048cc335994@app.fastmail.com>
Hi Arnd,
On Wed, Oct 5, 2022 at 10:58 AM Arnd Bergmann <arnd@arndb.de> wrote:
>
> On Tue, Oct 4, 2022, at 7:42 PM, Conor Dooley wrote:
> > On Mon, Oct 03, 2022 at 11:32:22PM +0100, Prabhakar wrote:
> >>
> >> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >> ---
> >> arch/riscv/include/asm/cacheflush.h | 8 +
> >> arch/riscv/include/asm/errata_list.h | 2 +
> >> arch/riscv/include/asm/sbi.h | 1 +
> >> arch/riscv/mm/dma-noncoherent.c | 20 ++
> >
> > Stupid question maybe, but I assume you mixed the driver addition and
> > the changes to arch/riscv for the sake of easily creating the RFC?
> >
> >> drivers/soc/renesas/Makefile | 4 +
> >> drivers/soc/renesas/rzf/Makefile | 3 +
> >> drivers/soc/renesas/rzf/ax45mp_cache.c | 365 +++++++++++++++++++++++++
> >> drivers/soc/renesas/rzf/rzf_sbi.h | 27 ++
>
> My feeling is that L2 cache behavior should live in arch/riscv
> rather than drivers/soc/, since this is not specific to a SoC
> family but rather the CPU core. I would also expect that the
> actual implementation and DT binding can be shared with
> non-renesas SoCs using the same CPU core.
>
Totally agree it is related to the CPU core and not the SoC. During
the BoF session it was agreed that unratified extensions code shouldnt
go under the arch/riscv. Since the code has vendor specific SBI calls
RISC-V maintainers asked to move it SoC specific so that maintenance
of the code falls under SoC vendors.
Cheers,
Prabhakar
next prev parent reply other threads:[~2022-10-05 10:15 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-03 22:32 [RFC PATCH v2 0/2] AX45MP: Add support to non-coherent DMA Prabhakar
2022-10-03 22:32 ` [RFC PATCH v2 1/2] dt-bindings: soc: renesas: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar
2022-10-04 6:41 ` Geert Uytterhoeven
2022-10-04 7:26 ` Lad, Prabhakar
2022-10-04 7:31 ` Conor Dooley
2022-10-04 7:59 ` Lad, Prabhakar
2022-10-04 9:12 ` Geert Uytterhoeven
2022-10-04 9:31 ` Lad, Prabhakar
2022-10-04 7:33 ` Conor Dooley
2022-10-03 22:32 ` [RFC PATCH v2 2/2] soc: renesas: Add L2 cache management for RZ/Five SoC Prabhakar
2022-10-04 17:42 ` Conor Dooley
2022-10-05 8:44 ` Lad, Prabhakar
2022-10-05 8:58 ` Conor Dooley
2022-10-05 9:17 ` Conor.Dooley
2022-10-05 10:20 ` Lad, Prabhakar
2022-10-05 10:29 ` Conor Dooley
2022-10-05 9:57 ` Arnd Bergmann
2022-10-05 10:14 ` Lad, Prabhakar [this message]
2022-10-05 1:28 ` Guo Ren
2022-10-05 12:53 ` Lad, Prabhakar
2022-10-05 14:23 ` Guo Ren
2022-10-05 15:02 ` Lad, Prabhakar
2022-10-06 0:59 ` Guo Ren
2022-10-06 15:36 ` Lad, Prabhakar
2022-10-11 9:38 ` Lad, Prabhakar
2022-10-11 13:10 ` Guo Ren
2022-10-17 9:39 ` Lad, Prabhakar
2022-10-17 12:36 ` Guo Ren
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