From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Magnus Damm <magnus.damm@gmail.com>,
Heiko Stuebner <heiko@sntech.de>, Guo Ren <guoren@kernel.org>,
Conor Dooley <conor.dooley@microchip.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Nathan Chancellor <nathan@kernel.org>,
Atish Patra <atishp@rivosinc.com>,
Anup Patel <apatel@ventanamicro.com>,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [RFC PATCH v2 1/2] dt-bindings: soc: renesas: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller
Date: Tue, 4 Oct 2022 08:41:53 +0200 [thread overview]
Message-ID: <CAMuHMdX1BuvHz46QWd+ajEcwmWMeSmvN4AtODuFEysRk14ArZQ@mail.gmail.com> (raw)
In-Reply-To: <20221003223222.448551-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi Prabhakar,
On Tue, Oct 4, 2022 at 12:32 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add DT binding documentation for L2 cache controller found on RZ/Five SoC.
>
> The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
> Single) from Andes. The AX45MP core has an L2 cache controller, this patch
> describes the L2 cache block.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/renesas/r9a07g043f-l2-cache.yaml
Not andestech,ax45mp-cache.yaml?
> @@ -0,0 +1,82 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright (C) 2022 Renesas Electronics Corp.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/renesas/r9a07g043f-l2-cache.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SiFive L2 Cache Controller
Andestech AX45MP?
> +
> +maintainers:
> + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> +
> +description:
> + A level-2 cache (L2C) is used to improve the system performance by providing
> + a larger amount of cache line entries and reasonable access delays. The L2C
> + is shared between cores, and a non-inclusive non-exclusive policy is used.
> +
> +properties:
> + compatible:
> + items:
> + - const: andestech,ax45mp-cache
> + - const: cache
This makes the schema apply to any node which is compatible with
"cache", cfr. the report from Rob's bot.
You need a select block to avoid that, cfr.
Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
next prev parent reply other threads:[~2022-10-04 6:42 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-03 22:32 [RFC PATCH v2 0/2] AX45MP: Add support to non-coherent DMA Prabhakar
2022-10-03 22:32 ` [RFC PATCH v2 1/2] dt-bindings: soc: renesas: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar
2022-10-04 6:41 ` Geert Uytterhoeven [this message]
2022-10-04 7:26 ` Lad, Prabhakar
2022-10-04 7:31 ` Conor Dooley
2022-10-04 7:59 ` Lad, Prabhakar
2022-10-04 9:12 ` Geert Uytterhoeven
2022-10-04 9:31 ` Lad, Prabhakar
2022-10-04 7:33 ` Conor Dooley
2022-10-03 22:32 ` [RFC PATCH v2 2/2] soc: renesas: Add L2 cache management for RZ/Five SoC Prabhakar
2022-10-04 17:42 ` Conor Dooley
2022-10-05 8:44 ` Lad, Prabhakar
2022-10-05 8:58 ` Conor Dooley
2022-10-05 9:17 ` Conor.Dooley
2022-10-05 10:20 ` Lad, Prabhakar
2022-10-05 10:29 ` Conor Dooley
2022-10-05 9:57 ` Arnd Bergmann
2022-10-05 10:14 ` Lad, Prabhakar
2022-10-05 1:28 ` Guo Ren
2022-10-05 12:53 ` Lad, Prabhakar
2022-10-05 14:23 ` Guo Ren
2022-10-05 15:02 ` Lad, Prabhakar
2022-10-06 0:59 ` Guo Ren
2022-10-06 15:36 ` Lad, Prabhakar
2022-10-11 9:38 ` Lad, Prabhakar
2022-10-11 13:10 ` Guo Ren
2022-10-17 9:39 ` Lad, Prabhakar
2022-10-17 12:36 ` Guo Ren
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