Re: [PATCH 12/13] riscv: icicle-kit: update microchip icicle kit device tree

From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Conor Dooley <conor.dooley@microchip.com>
Cc: Linus Walleij <linus.walleij@linaro.org>,
	Bartosz Golaszewski <bgolaszewski@baylibre.com>,
	Rob Herring <robh+dt@kernel.org>,
	Jassi Brar <jassisinghbrar@gmail.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alessandro Zummo <a.zummo@towertech.it>,
	Alexandre Belloni <alexandre.belloni@bootlin.com>,
	Mark Brown <broonie@kernel.org>,
	Greg KH <gregkh@linuxfoundation.org>,
	Lewis Hanly <lewis.hanly@microchip.com>,
	daire.mcnamara@microchip.com, Atish Patra <atish.patra@wdc.com>,
	ivan.griffin@microchip.com,
	"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
	<devicetree@vger.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Linux I2C <linux-i2c@vger.kernel.org>,
	linux-riscv <linux-riscv@lists.infradead.org>,
	Linux Crypto Mailing List <linux-crypto@vger.kernel.org>,
	linux-rtc@vger.kernel.org, linux-spi <linux-spi@vger.kernel.org>,
	USB list <linux-usb@vger.kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
	Bin Meng <bin.meng@windriver.com>
Subject: Re: [PATCH 12/13] riscv: icicle-kit: update microchip icicle kit device tree
Date: Tue, 9 Nov 2021 10:04:51 +0100	[thread overview]
Message-ID: <CAMuHMdWEhJj0Cqt3sgGvgZe7JSFqBmTgtZRkom30NKqEW27NvQ@mail.gmail.com> (raw)
In-Reply-To: <20211108150554.4457-13-conor.dooley@microchip.com>

Hi Conor,

On Mon, Nov 8, 2021 at 4:07 PM <conor.dooley@microchip.com> wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Update the device tree for the icicle kit by splitting it into a third part,
> which contains peripherals in the fpga fabric, add new peripherals
> (spi, qspi, gpio, rtc, pcie, system services, i2c), update parts of the memory
> map which have been changed.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

Thanks for your patch!

Please split it into logical separated parts.

> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
> @@ -0,0 +1,21 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2020-2021 Microchip Technology Inc */
> +
> +/ {
> +       fpgadma: fpgadma@60020000 {
> +               compatible = "microchip,mpfs-fpga-dma-uio";
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               reg = <0x0 0x60020000 0x0 0x1000>;
> +               interrupt-parent = <&plic>;
> +               interrupts = <PLIC_INT_FABRIC_F2H_2>;
> +               status = "okay";
> +       };
> +
> +       fpgalsram: fpga_lsram@61000000 {
> +               compatible = "generic-uio";
> +               reg = <0x0 0x61000000 0x0 0x0001000
> +                       0x14 0x00000000 0x0 0x00010000>;

Please group by angular brackets, to increase readability, and support
automatic validation:

<0x0 0x61000000 0x0 0x0001000>, <0x14 0x00000000 0x0 0x00010000>

> +               status = "okay";
> +       };

Do we really want UIO nodes in upstream DT?

> +};
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> index fc1e5869df1b..4212129fcdf1 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> @@ -1,5 +1,5 @@
>  // SPDX-License-Identifier: (GPL-2.0 OR MIT)
> -/* Copyright (c) 2020 Microchip Technology Inc */
> +/* Copyright (c) 2020-2021 Microchip Technology Inc */
>
>  /dts-v1/;
>
> @@ -13,72 +13,187 @@ / {
>         compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
>
>         aliases {
> -               ethernet0 = &emac1;
> -               serial0 = &serial0;
> -               serial1 = &serial1;
> -               serial2 = &serial2;
> -               serial3 = &serial3;
> +               mmuart0 = &mmuart0;
> +               mmuart1 = &mmuart1;
> +               mmuart2 = &mmuart2;
> +               mmuart3 = &mmuart3;
> +               mmuart4 = &mmuart4;

Why? SerialN is the standard alias name.

>         };

>
> -&emac0 {
> +&spi0 {
> +       status = "okay";
> +       spidev@0 {
> +               compatible = "spidev";

Please don't use "spidev", but a proper compatible value describing
what is really connected.  If you want to use it with spidev (which
is software policy, not hardware description), add that compatible
value to drivers/spi/spidev.c:spidev_dt_ids[], or use driver_override
in sysfs at runtime.

> +               reg = <0>; /* CS 0 */
> +               spi-max-frequency = <10000000>;
> +               status = "okay";
> +       };
> +};
> +
> +&spi1 {
> +       status = "okay";

No slave devices specified?

> +};
> +
> +&qspi {
> +       status = "okay";
> +};
> +
> +&i2c0 {
> +       status = "okay";
> +};
> +
> +&i2c1 {
> +       status = "okay";
> +       pac193x: pac193x@10 {

adc@, I guess?

> +               compatible = "microchip,pac1934";
> +               reg = <0x10>;
> +               samp-rate = <64>;
> +               status = "okay";
> +               ch0: channel0 {
> +                       uohms-shunt-res = <10000>;
> +                       rail-name = "VDDREG";
> +                       channel_enabled;
> +               };
> +               ch1: channel1 {
> +                       uohms-shunt-res = <10000>;
> +                       rail-name = "VDDA25";
> +                       channel_enabled;
> +               };
> +               ch2: channel2 {
> +                       uohms-shunt-res = <10000>;
> +                       rail-name = "VDD25";
> +                       channel_enabled;
> +               };
> +               ch3: channel3 {
> +                       uohms-shunt-res = <10000>;
> +                       rail-name = "VDDA_REG";
> +                       channel_enabled;
> +               };
> +       };
> +};

> +&gpio2 {
> +       interrupts = <PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT
> +               PLIC_INT_GPIO2_NON_DIRECT>;

Why override interrupts in the board .dts file?
Doesn't this belong in the SoC .dtsi file?
Please group using angular brackets.

> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi

> @@ -145,49 +149,55 @@ cpu4_intc: interrupt-controller {
>         soc {
>                 #address-cells = <2>;
>                 #size-cells = <2>;
> -               compatible = "simple-bus";
> +               compatible = "microchip,mpfs-soc", "simple-bus";
>                 ranges;
>
> -               cache-controller@2010000 {
> +               cctrllr: cache-controller@2010000 {
>                         compatible = "sifive,fu540-c000-ccache", "cache";
> +                       reg = <0x0 0x2010000 0x0 0x1000>;
> +                       interrupt-parent = <&plic>;
> +                       interrupts = <PLIC_INT_L2_METADATA_CORR
> +                               PLIC_INT_L2_METADAT_UNCORR
> +                               PLIC_INT_L2_DATA_CORR>;