[PATCH 00/14] treewide: add initial support for R-Car V3U

[PATCH 00/14] treewide: add initial support for R-Car V3U

[Yoshihiro Shimoda]

This patch series adds initial support for R-Car V3U (r8a779a0).

Yoshihiro Shimoda (14):
  dt-bindings: arm: renesas: Document R-Car V3U SoC DT bindings
  dt-bindings: arm: renesas: Document Renesas Falcon boards
  dt-bindings: power: renesas,rcar-sysc: Document r8a779a0 SYSC binding
  dt-bindings: power: Add r8a779a0 SYSC power domain definitions
  dt-bindings: reset: renesas,rst: Document r8a779a0 reset module
  dt-bindings: clock: renesas,cpg-mssr: Document r8a779a0
  dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions
  dt-bindings: serial: renesas,scif: Document r8a779a0 bindings
  soc: renesas: identify R-Car V3U
  soc: renesas: r8a779a0-sysc: Add r8a779a0 support
  soc: renesas: rcar-rst: Add support for R-Car V3U
  clk: renesas: cpg-mssr: Add support for R-Car V3U
  arm64: dts: renesas: Add Renesas R8A779A0 SoC support
  arm64: dts: renesas: Add Renesas Falcon boards support

 Documentation/devicetree/bindings/arm/renesas.yaml |   7 +
 .../bindings/clock/renesas,cpg-mssr.yaml           |   1 +
 .../bindings/power/renesas,rcar-sysc.yaml          |   1 +
 .../devicetree/bindings/reset/renesas,rst.yaml     |   1 +
 .../devicetree/bindings/serial/renesas,scif.yaml   |   1 +
 arch/arm64/boot/dts/renesas/Makefile               |   2 +
 arch/arm64/boot/dts/renesas/falcon-cpu.dtsi        |  44 ++
 arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts    |  23 +
 arch/arm64/boot/dts/renesas/r8a779a0.dtsi          | 132 ++++++
 drivers/clk/renesas/Kconfig                        |   4 +
 drivers/clk/renesas/Makefile                       |   1 +
 drivers/clk/renesas/r8a779a0-cpg-mssr.c            | 479 +++++++++++++++++++++
 drivers/clk/renesas/renesas-cpg-mssr.c             |  20 +-
 drivers/clk/renesas/renesas-cpg-mssr.h             |   2 +
 drivers/soc/renesas/Kconfig                        |  10 +
 drivers/soc/renesas/Makefile                       |   1 +
 drivers/soc/renesas/r8a779a0-sysc.c                | 460 ++++++++++++++++++++
 drivers/soc/renesas/rcar-rst.c                     |   6 +
 drivers/soc/renesas/renesas-soc.c                  |   8 +
 include/dt-bindings/clock/r8a779a0-cpg-mssr.h      |  63 +++
 include/dt-bindings/power/r8a779a0-sysc.h          |  61 +++
 21 files changed, 1324 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/falcon-cpu.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
 create mode 100644 arch/arm64/boot/dts/renesas/r8a779a0.dtsi
 create mode 100644 drivers/clk/renesas/r8a779a0-cpg-mssr.c
 create mode 100644 drivers/soc/renesas/r8a779a0-sysc.c
 create mode 100644 include/dt-bindings/clock/r8a779a0-cpg-mssr.h
 create mode 100644 include/dt-bindings/power/r8a779a0-sysc.h

-- 
2.7.4

[PATCH 01/14] dt-bindings: arm: renesas: Document R-Car V3U SoC DT bindings

[Yoshihiro Shimoda]

Add device tree bindings documentation for Renesas R-Car V3U
(r8a779a0).

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 Documentation/devicetree/bindings/arm/renesas.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
index 0d4dabb..9f8c3353 100644
--- a/Documentation/devicetree/bindings/arm/renesas.yaml
+++ b/Documentation/devicetree/bindings/arm/renesas.yaml
@@ -281,6 +281,10 @@ properties:
               - renesas,draak # Draak (RTP0RC77995SEB0010S)
           - const: renesas,r8a77995
 
+      - description: R-Car V3U (R8A779A0)
+        items:
+          - const: renesas,r8a779a0
+
       - description: RZ/N1D (R9A06G032)
         items:
           - enum:
-- 
2.7.4

[PATCH 02/14] dt-bindings: arm: renesas: Document Renesas Falcon boards

[Yoshihiro Shimoda]

Add device tree bindings documentation for Renesas R-Car V3U
Falcon CPU and BreakOut boards.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 Documentation/devicetree/bindings/arm/renesas.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
index 9f8c3353..f1008d3 100644
--- a/Documentation/devicetree/bindings/arm/renesas.yaml
+++ b/Documentation/devicetree/bindings/arm/renesas.yaml
@@ -283,6 +283,9 @@ properties:
 
       - description: R-Car V3U (R8A779A0)
         items:
+          - enum:
+              - renesas,falcon-cpu # Falcon CPU board (RTP0RC779A0CPB0010S)
+              - renesas,falcon-breakout # Falcon BreakOut board (RTP0RC779A0BOB0010S)
           - const: renesas,r8a779a0
 
       - description: RZ/N1D (R9A06G032)
-- 
2.7.4

[PATCH 03/14] dt-bindings: power: renesas,rcar-sysc: Document r8a779a0 SYSC binding

[Yoshihiro Shimoda]

Document bindings for the R-Car V3U (aka R8A779A0) SYSC block.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml
index ec2aaee..99e8042 100644
--- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml
+++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml
@@ -40,6 +40,7 @@ properties:
       - renesas,r8a77980-sysc # R-Car V3H
       - renesas,r8a77990-sysc # R-Car E3
       - renesas,r8a77995-sysc # R-Car D3
+      - renesas,r8a779a0-sysc # R-Car V3U
 
   reg:
     maxItems: 1
-- 
2.7.4

[PATCH 04/14] dt-bindings: power: Add r8a779a0 SYSC power domain definitions

[Yoshihiro Shimoda]

Adds power domain indices fpr R-Car V3U (r8a779a0).

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 include/dt-bindings/power/r8a779a0-sysc.h | 61 +++++++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)
 create mode 100644 include/dt-bindings/power/r8a779a0-sysc.h

diff --git a/include/dt-bindings/power/r8a779a0-sysc.h b/include/dt-bindings/power/r8a779a0-sysc.h
new file mode 100644
index 0000000..e7e9e89
--- /dev/null
+++ b/include/dt-bindings/power/r8a779a0-sysc.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A779A0_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A779A0_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISCR0, Interrupt Status/Clear Register 0)
+ */
+
+#define R8A779A0_PD_A1E0D0C0		0
+#define R8A779A0_PD_A1E0D0C1		1
+#define R8A779A0_PD_A1E0D1C0		2
+#define R8A779A0_PD_A1E0D1C1		3
+#define R8A779A0_PD_A1E1D0C0		4
+#define R8A779A0_PD_A1E1D0C1		5
+#define R8A779A0_PD_A1E1D1C0		6
+#define R8A779A0_PD_A1E1D1C1		7
+#define R8A779A0_PD_A2E0D0		16
+#define R8A779A0_PD_A2E0D1		17
+#define R8A779A0_PD_A2E1D0		18
+#define R8A779A0_PD_A2E1D1		19
+#define R8A779A0_PD_A3E0		20
+#define R8A779A0_PD_A3E1		21
+#define R8A779A0_PD_3DG_A		24
+#define R8A779A0_PD_3DG_B		25
+#define R8A779A0_PD_A1CNN2		32
+#define R8A779A0_PD_A1DSP0		33
+#define R8A779A0_PD_A2IMP01		34
+#define R8A779A0_PD_A2DP0		35
+#define R8A779A0_PD_A2CV0		36
+#define R8A779A0_PD_A2CV1		37
+#define R8A779A0_PD_A2CV4		38
+#define R8A779A0_PD_A2CV6		39
+#define R8A779A0_PD_A2CN2		40
+#define R8A779A0_PD_A1CNN0		41
+#define R8A779A0_PD_A2CN0		42
+#define R8A779A0_PD_A3IR		43
+#define R8A779A0_PD_A1CNN1		44
+#define R8A779A0_PD_A1DSP1		45
+#define R8A779A0_PD_A2IMP23		46
+#define R8A779A0_PD_A2DP1		47
+#define R8A779A0_PD_A2CV2		48
+#define R8A779A0_PD_A2CV3		49
+#define R8A779A0_PD_A2CV5		50
+#define R8A779A0_PD_A2CV7		51
+#define R8A779A0_PD_A2CN1		52
+#define R8A779A0_PD_A3VIP0		56
+#define R8A779A0_PD_A3VIP1		57
+#define R8A779A0_PD_A3VIP2		58
+#define R8A779A0_PD_A3VIP3		59
+#define R8A779A0_PD_A3ISP01		60
+#define R8A779A0_PD_A3ISP23		61
+
+/* Always-on power area */
+#define R8A779A0_PD_ALWAYS_ON		64
+
+#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__ */
-- 
2.7.4

[PATCH 05/14] dt-bindings: reset: renesas,rst: Document r8a779a0 reset module

[Yoshihiro Shimoda]

Document bindings for the R-Car V3U (R8A779A0) reset module.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 Documentation/devicetree/bindings/reset/renesas,rst.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.yaml b/Documentation/devicetree/bindings/reset/renesas,rst.yaml
index 2849ce4..620cd05 100644
--- a/Documentation/devicetree/bindings/reset/renesas,rst.yaml
+++ b/Documentation/devicetree/bindings/reset/renesas,rst.yaml
@@ -47,6 +47,7 @@ properties:
       - renesas,r8a77980-rst      # R-Car V3H
       - renesas,r8a77990-rst      # R-Car E3
       - renesas,r8a77995-rst      # R-Car D3
+      - renesas,r8a779a0-rst      # R-Car V3U
 
   reg:
     maxItems: 1
-- 
2.7.4

[PATCH 06/14] dt-bindings: clock: renesas,cpg-mssr: Document r8a779a0

[Yoshihiro Shimoda]

Add binding documentation for the R-Car V3U (R8A779A0) Clock Pulse
Generator.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
index e13aee8..9b414fb 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
@@ -47,6 +47,7 @@ properties:
       - renesas,r8a77980-cpg-mssr # R-Car V3H
       - renesas,r8a77990-cpg-mssr # R-Car E3
       - renesas,r8a77995-cpg-mssr # R-Car D3
+      - renesas,r8a779a0-cpg-mssr # R-Car V3U
 
   reg:
     maxItems: 1
-- 
2.7.4

[PATCH 07/14] dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions

[Yoshihiro Shimoda]

Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
V3U (R8A779A0) SoC.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 include/dt-bindings/clock/r8a779a0-cpg-mssr.h | 63 +++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)
 create mode 100644 include/dt-bindings/clock/r8a779a0-cpg-mssr.h

diff --git a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
new file mode 100644
index 0000000..9ed14ea
--- /dev/null
+++ b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a779A0 CPG Core Clocks */
+#define R8A779A0_CLK_Z0			0
+#define R8A779A0_CLK_ZX			1
+#define R8A779A0_CLK_Z1			2
+#define R8A779A0_CLK_ZR			3
+#define R8A779A0_CLK_ZS			4
+#define R8A779A0_CLK_ZT			5
+#define R8A779A0_CLK_ZTR		6
+#define R8A779A0_CLK_S1			7
+#define R8A779A0_CLK_S3			8
+#define R8A779A0_CLK_S1D1		9
+#define R8A779A0_CLK_S1D2		10
+#define R8A779A0_CLK_S1D4		11
+#define R8A779A0_CLK_S1D8		12
+#define R8A779A0_CLK_S1D12		13
+#define R8A779A0_CLK_S2D1		14
+#define R8A779A0_CLK_S2D2		15
+#define R8A779A0_CLK_S2D4		16
+#define R8A779A0_CLK_S3D1		17
+#define R8A779A0_CLK_S3D2		18
+#define R8A779A0_CLK_S3D4		19
+#define R8A779A0_CLK_LB			20
+#define R8A779A0_CLK_CP			21
+#define R8A779A0_CLK_CL			22
+#define R8A779A0_CLK_CL16MCK		23
+#define R8A779A0_CLK_ZB30		24
+#define R8A779A0_CLK_ZB30D2		25
+#define R8A779A0_CLK_ZB30D4		26
+#define R8A779A0_CLK_ZB31		27
+#define R8A779A0_CLK_ZB31D2		28
+#define R8A779A0_CLK_ZB31D4		29
+#define R8A779A0_CLK_SD0H		30
+#define R8A779A0_CLK_SD0		31
+#define R8A779A0_CLK_RPC		32
+#define R8A779A0_CLK_RPCD2		33
+#define R8A779A0_CLK_MSO		34
+#define R8A779A0_CLK_CANFD		35
+#define R8A779A0_CLK_CSI0		36
+#define R8A779A0_CLK_FRAY		37
+#define R8A779A0_CLK_POST		38
+#define R8A779A0_CLK_POST2		39
+#define R8A779A0_CLK_POST3		40
+#define R8A779A0_CLK_DSI		41
+#define R8A779A0_CLK_VIP		42
+#define R8A779A0_CLK_ADGH		43
+#define R8A779A0_CLK_CNNDSP		44
+#define R8A779A0_CLK_ICU		45
+#define R8A779A0_CLK_ICUD2		46
+#define R8A779A0_CLK_VCBUS		47
+#define R8A779A0_CLK_CBFUSA		48
+#define R8A779A0_CLK_RCLK		49
+#define R8A779A0_CLK_OSCCLK		50
+
+#endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */
-- 
2.7.4

[PATCH 08/14] dt-bindings: serial: renesas,scif: Document r8a779a0 bindings

[Yoshihiro Shimoda]

R-Car V3U (R8A779A0) SoC also has the R-Car Gen3 compatible
SCIF ports, so document the SoC specific bindings.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 Documentation/devicetree/bindings/serial/renesas,scif.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
index 570b379..1c15621 100644
--- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
@@ -59,6 +59,7 @@ properties:
               - renesas,scif-r8a77980     # R-Car V3H
               - renesas,scif-r8a77990     # R-Car E3
               - renesas,scif-r8a77995     # R-Car D3
+              - renesas,scif-r8a779a0     # R-Car V3U
           - const: renesas,rcar-gen3-scif # R-Car Gen3 and RZ/G2
           - const: renesas,scif           # generic SCIF compatible UART
 
-- 
2.7.4

[PATCH 09/14] soc: renesas: identify R-Car V3U

[Yoshihiro Shimoda]

Add support for identifying the R-Car V3U (R8A779A0) SoC.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 drivers/soc/renesas/Kconfig       | 6 ++++++
 drivers/soc/renesas/renesas-soc.c | 8 ++++++++
 2 files changed, 14 insertions(+)

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 7d63a13..e0c39efd 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -272,6 +272,12 @@ config ARCH_R8A77995
 	help
 	  This enables support for the Renesas R-Car D3 SoC.
 
+config ARCH_R8A779A0
+	bool "Renesas R-Car V3U SoC Platform"
+	select ARCH_RCAR_GEN3
+	help
+	  This enables support for the Renesas R-Car V3U SoC.
+
 endif # ARM64
 
 # SoC
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index f815a6a..0f8eff4 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -200,6 +200,11 @@ static const struct renesas_soc soc_rcar_d3 __initconst __maybe_unused = {
 	.id	= 0x58,
 };
 
+static const struct renesas_soc soc_rcar_v3u __initconst __maybe_unused = {
+	.family	= &fam_rcar_gen3,
+	.id	= 0x59,
+};
+
 static const struct renesas_soc soc_shmobile_ag5 __initconst __maybe_unused = {
 	.family	= &fam_shmobile,
 	.id	= 0x37,
@@ -291,6 +296,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
 #ifdef CONFIG_ARCH_R8A77995
 	{ .compatible = "renesas,r8a77995",	.data = &soc_rcar_d3 },
 #endif
+#ifdef CONFIG_ARCH_R8A779A0
+	{ .compatible = "renesas,r8a779a0",	.data = &soc_rcar_v3u },
+#endif
 #ifdef CONFIG_ARCH_SH73A0
 	{ .compatible = "renesas,sh73a0",	.data = &soc_shmobile_ag5 },
 #endif
-- 
2.7.4

[PATCH 10/14] soc: renesas: r8a779a0-sysc: Add r8a779a0 support

[Yoshihiro Shimoda]

Add support for R-Car V3U (R8A779A0) SoC power areas and
register access, because register specification differs
than R-Car Gen2/3.

Inspired by patches in the BSP by Tho Vu.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 drivers/soc/renesas/Kconfig         |   4 +
 drivers/soc/renesas/Makefile        |   1 +
 drivers/soc/renesas/r8a779a0-sysc.c | 460 ++++++++++++++++++++++++++++++++++++
 3 files changed, 465 insertions(+)
 create mode 100644 drivers/soc/renesas/r8a779a0-sysc.c

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index e0c39efd..8fd5525 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -275,6 +275,7 @@ config ARCH_R8A77995
 config ARCH_R8A779A0
 	bool "Renesas R-Car V3U SoC Platform"
 	select ARCH_RCAR_GEN3
+	select SYSC_R8A779A0
 	help
 	  This enables support for the Renesas R-Car V3U SoC.
 
@@ -365,6 +366,9 @@ config SYSC_R8A77995
 	bool "System Controller support for R-Car D3" if COMPILE_TEST
 	select SYSC_RCAR
 
+config SYSC_R8A779A0
+	bool "R-Car V3U System Controller support" if COMPILE_TEST
+
 # Family
 config RST_RCAR
 	bool "Reset Controller support for R-Car" if COMPILE_TEST
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index 10a399f..9b29bed 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_SYSC_R8A77970)	+= r8a77970-sysc.o
 obj-$(CONFIG_SYSC_R8A77980)	+= r8a77980-sysc.o
 obj-$(CONFIG_SYSC_R8A77990)	+= r8a77990-sysc.o
 obj-$(CONFIG_SYSC_R8A77995)	+= r8a77995-sysc.o
+obj-$(CONFIG_SYSC_R8A779A0)	+= r8a779a0-sysc.o
 ifdef CONFIG_SMP
 obj-$(CONFIG_ARCH_R9A06G032)	+= r9a06g032-smp.o
 endif
diff --git a/drivers/soc/renesas/r8a779a0-sysc.c b/drivers/soc/renesas/r8a779a0-sysc.c
new file mode 100644
index 0000000..bb442c1
--- /dev/null
+++ b/drivers/soc/renesas/r8a779a0-sysc.c
@@ -0,0 +1,460 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas R-Car V3U System Controller
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include <linux/bits.h>
+#include <linux/clk/renesas.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/of_address.h>
+#include <linux/pm_domain.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/soc/renesas/rcar-sysc.h>
+#include <linux/sys_soc.h>
+#include <linux/syscore_ops.h>
+
+#include <dt-bindings/power/r8a779a0-sysc.h>
+
+#include "rcar-sysc.h"
+
+static struct rcar_sysc_area r8a779a0_areas[] __initdata = {
+	{ "always-on",	     0, 0, R8A779A0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
+	{ "a3e0",	0x1500, 0, R8A779A0_PD_A3E0, R8A779A0_PD_ALWAYS_ON, PD_SCU },
+	{ "a3e1",	0x1540, 0, R8A779A0_PD_A3E1, R8A779A0_PD_ALWAYS_ON, PD_SCU },
+	{ "a2e0d0",	0x1400, 0, R8A779A0_PD_A2E0D0, R8A779A0_PD_A3E0, PD_SCU },
+	{ "a2e0d1",	0x1440, 0, R8A779A0_PD_A2E0D1, R8A779A0_PD_A3E0, PD_SCU },
+	{ "a2e1d0",	0x1480, 0, R8A779A0_PD_A2E1D0, R8A779A0_PD_A3E1, PD_SCU },
+	{ "a2e1d1",	0x14c0, 0, R8A779A0_PD_A2E1D1, R8A779A0_PD_A3E1, PD_SCU },
+	{ "a1e0d0c0",	0x1000, 0, R8A779A0_PD_A1E0D0C0, R8A779A0_PD_A2E0D0, PD_CPU_NOCR },
+	{ "a1e0d0c1",	0x1040, 0, R8A779A0_PD_A1E0D0C1, R8A779A0_PD_A2E0D0, PD_CPU_NOCR },
+	{ "a1e0d1c0",	0x1080, 0, R8A779A0_PD_A1E0D1C0, R8A779A0_PD_A2E0D1, PD_CPU_NOCR },
+	{ "a1e0d1c1",	0x10c0, 0, R8A779A0_PD_A1E0D1C1, R8A779A0_PD_A2E0D1, PD_CPU_NOCR },
+	{ "a1e1d0c0",	0x1100, 0, R8A779A0_PD_A1E1D0C0, R8A779A0_PD_A2E1D0, PD_CPU_NOCR },
+	{ "a1e1d0c1",	0x1140, 0, R8A779A0_PD_A1E1D0C1, R8A779A0_PD_A2E1D0, PD_CPU_NOCR },
+	{ "a1e1d1c0",	0x1180, 0, R8A779A0_PD_A1E1D1C0, R8A779A0_PD_A2E1D1, PD_CPU_NOCR },
+	{ "a1e1d1c1",	0x11c0, 0, R8A779A0_PD_A1E1D1C1, R8A779A0_PD_A2E1D1, PD_CPU_NOCR },
+	{ "3dg-a",	0x1600, 0, R8A779A0_PD_3DG_A, R8A779A0_PD_ALWAYS_ON },
+	{ "3dg-b",	0x1640, 0, R8A779A0_PD_3DG_B, R8A779A0_PD_3DG_A },
+	{ "a3vip0",	0x1e00, 0, R8A779A0_PD_A3VIP0, R8A779A0_PD_ALWAYS_ON },
+	{ "a3vip1",	0x1e40, 0, R8A779A0_PD_A3VIP1, R8A779A0_PD_ALWAYS_ON },
+	{ "a3vip3",	0x1ec0, 0, R8A779A0_PD_A3VIP3, R8A779A0_PD_ALWAYS_ON },
+	{ "a3vip2",	0x1e80, 0, R8A779A0_PD_A3VIP2, R8A779A0_PD_ALWAYS_ON },
+	{ "a3isp01",	0x1f00, 0, R8A779A0_PD_A3ISP01, R8A779A0_PD_ALWAYS_ON },
+	{ "a3isp23",	0x1f40, 0, R8A779A0_PD_A3ISP23, R8A779A0_PD_ALWAYS_ON },
+	{ "a3ir",	0x1ac0, 0, R8A779A0_PD_A3IR, R8A779A0_PD_ALWAYS_ON },
+	{ "a2cn0",	0x1a80, 0, R8A779A0_PD_A2CN0, R8A779A0_PD_A3IR },
+	{ "a2imp01",	0x1880, 0, R8A779A0_PD_A2IMP01, R8A779A0_PD_A3IR },
+	{ "a2dp0",	0x18c0, 0, R8A779A0_PD_A2DP0, R8A779A0_PD_A3IR },
+	{ "a2cv0",	0x1900, 0, R8A779A0_PD_A2CV0, R8A779A0_PD_A3IR },
+	{ "a2cv1",	0x1940, 0, R8A779A0_PD_A2CV1, R8A779A0_PD_A3IR },
+	{ "a2cv4",	0x1980, 0, R8A779A0_PD_A2CV4, R8A779A0_PD_A3IR },
+	{ "a2cv6",	0x19c0, 0, R8A779A0_PD_A2CV6, R8A779A0_PD_A3IR },
+	{ "a2cn2",	0x1a00, 0, R8A779A0_PD_A2CN2, R8A779A0_PD_A3IR },
+	{ "a2imp23",	0x1b80, 0, R8A779A0_PD_A2IMP23, R8A779A0_PD_A3IR },
+	{ "a2dp1",	0x1bc0, 0, R8A779A0_PD_A2DP0, R8A779A0_PD_A3IR },
+	{ "a2cv2",	0x1c00, 0, R8A779A0_PD_A2CV0, R8A779A0_PD_A3IR },
+	{ "a2cv3",	0x1c40, 0, R8A779A0_PD_A2CV1, R8A779A0_PD_A3IR },
+	{ "a2cv5",	0x1c80, 0, R8A779A0_PD_A2CV4, R8A779A0_PD_A3IR },
+	{ "a2cv7",	0x1cc0, 0, R8A779A0_PD_A2CV6, R8A779A0_PD_A3IR },
+	{ "a2cn1",	0x1d00, 0, R8A779A0_PD_A2CN1, R8A779A0_PD_A3IR },
+	{ "a1cnn0",	0x1b00, 0, R8A779A0_PD_A1CNN0, R8A779A0_PD_A2CN0 },
+	{ "a1cnn2",	0x1800, 0, R8A779A0_PD_A1CNN2, R8A779A0_PD_A2CN2 },
+	{ "a1dsp0",	0x1840, 0, R8A779A0_PD_A1DSP0, R8A779A0_PD_A2CN2 },
+	{ "a1cnn1",	0x1b00, 0, R8A779A0_PD_A1CNN1, R8A779A0_PD_A2CN1 },
+	{ "a1dsp1",	0x1b40, 0, R8A779A0_PD_A1DSP1, R8A779A0_PD_A2CN1 },
+};
+
+const struct rcar_sysc_info r8a779a0_sysc_info __initconst = {
+	.areas = r8a779a0_areas,
+	.num_areas = ARRAY_SIZE(r8a779a0_areas),
+};
+
+/* SYSC Common */
+#define SYSCSR		0x000	/* SYSC Status Register */
+#define SYSCPONSR(x)	(0x800 + ((x) * 0x4)) /* Power-ON Status Register 0 */
+#define SYSCPOFFSR(x)	(0x808 + ((x) * 0x4)) /* Power-OFF Status Register */
+#define SYSCISCR(x)	(0x810 + ((x) * 0x4)) /* Interrupt Status/Clear Register */
+#define SYSCIER(x)	(0x820 + ((x) * 0x4)) /* Interrupt Enable Register */
+#define SYSCIMR(x)	(0x830 + ((x) * 0x4)) /* Interrupt Mask Register */
+
+/* Power Domain Registers */
+#define PDRSR(n)	(0x1000 + ((n) * 0x40))
+#define PDRONCR(n)	(0x1004 + ((n) * 0x40))
+#define PDROFFCR(n)	(0x1008 + ((n) * 0x40))
+#define PDRESR(n)	(0x100C + ((n) * 0x40))
+
+/* Power State */
+#define PW_ACTIVE	1	/* Active setting */
+
+/* PDRSR */
+#define PDRSR_OFF		BIT(0)	/* Power-OFF state */
+#define PDRSR_ON		BIT(4)	/* Power-ON state */
+#define PDRSR_OFF_STATE		BIT(8)  /* Processing Power-OFF sequence */
+#define PDRSR_ON_STATE		BIT(12) /* Processing Power-ON sequence */
+
+#define SYSCSR_PONENB		1	/* Ready for power resume requests */
+#define SYSCSR_POFFENB		0	/* Ready for power shutoff requests */
+
+#define SYSCSR_RETRIES		1000
+#define SYSCSR_DELAY_US		10
+
+#define PDRESR_RETRIES		1000
+#define PDRESR_DELAY_US		10
+
+#define SYSCISR_RETRIES		1000
+#define SYSCISR_DELAY_US	10
+
+#define R8A779A0_NUM_PD_ALWAYS_ON	64	/* Always-on power area */
+
+#define NUM_DOMAINS_EACH_REG	32
+
+struct rcar_sysc_ch {
+	u16 chan_offs;
+	u8 chan_bit;
+	u8 isr_bit;
+};
+
+static void __iomem *rcar_sysc_base;
+static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
+
+static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on)
+{
+	unsigned int sr_bit, reg_offs;
+	int k;
+
+	if (on) {
+		sr_bit = SYSCSR_PONENB;
+		reg_offs = PDRONCR(sysc_ch->isr_bit);
+	} else {
+		sr_bit = SYSCSR_POFFENB;
+		reg_offs = PDROFFCR(sysc_ch->isr_bit);
+	}
+
+	/* Wait until SYSC is ready to accept a power request */
+	for (k = 0; k < SYSCSR_RETRIES; k++) {
+		if (ioread32(rcar_sysc_base + SYSCSR) & BIT(sr_bit))
+			break;
+		udelay(SYSCSR_DELAY_US);
+	}
+
+	if (k == SYSCSR_RETRIES)
+		return -EAGAIN;
+
+	/* Submit power shutoff or power resume request */
+	iowrite32(PW_ACTIVE, rcar_sysc_base + reg_offs);
+
+	return 0;
+}
+
+static int clear_irq_flags(unsigned int reg_idx, unsigned int isr_mask)
+{
+	int k = 0;
+
+	iowrite32(isr_mask, rcar_sysc_base + SYSCISCR(reg_idx));
+
+	for (k = 0; k < SYSCISR_RETRIES; k++) {
+		if ((ioread32(rcar_sysc_base + SYSCISCR(reg_idx)) & isr_mask) == 0)
+			break;
+
+		udelay(SYSCISR_DELAY_US);
+	}
+
+	if (k == SYSCISR_RETRIES) {
+		pr_err("\n %s : Can not clear IRQ flags in SYSCISCR", __func__);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on)
+{
+	unsigned int isr_mask, chan_mask;
+	unsigned int reg_idx, bit_idx;
+	unsigned int status;
+	unsigned long flags;
+	int ret = 0;
+	int k;
+
+	spin_lock_irqsave(&rcar_sysc_lock, flags);
+
+	reg_idx = sysc_ch->isr_bit / NUM_DOMAINS_EACH_REG;
+	bit_idx = sysc_ch->isr_bit % NUM_DOMAINS_EACH_REG;
+
+	chan_mask = BIT(sysc_ch->chan_bit);
+	isr_mask = BIT(bit_idx);
+
+	/*
+	 * The interrupt source needs to be enabled, but masked, to prevent the
+	 * CPU from receiving it.
+	 */
+	iowrite32(ioread32(rcar_sysc_base + SYSCIER(reg_idx)) | isr_mask,
+		  rcar_sysc_base + SYSCIER(reg_idx));
+	iowrite32(ioread32(rcar_sysc_base + SYSCIMR(reg_idx)) | isr_mask,
+		  rcar_sysc_base + SYSCIMR(reg_idx));
+
+	ret = clear_irq_flags(reg_idx, isr_mask);
+	if (ret)
+		goto out;
+
+	/* Submit power shutoff or resume request until it was accepted */
+	for (k = 0; k < PDRESR_RETRIES; k++) {
+		ret = rcar_sysc_pwr_on_off(sysc_ch, on);
+		if (ret)
+			goto out;
+
+		status = ioread32(rcar_sysc_base + PDRESR(sysc_ch->isr_bit));
+		if (!(status & chan_mask))
+			break;
+
+		udelay(PDRESR_DELAY_US);
+	}
+
+	if (k == PDRESR_RETRIES) {
+		ret = -EIO;
+		goto out;
+	}
+
+	/* Wait until the power shutoff or resume request has completed * */
+	for (k = 0; k < SYSCISR_RETRIES; k++) {
+		if (ioread32(rcar_sysc_base + SYSCISCR(reg_idx)) & isr_mask)
+			break;
+		udelay(SYSCISR_DELAY_US);
+	}
+
+	if (k == SYSCISR_RETRIES) {
+		ret = -EIO;
+		goto out;
+	}
+
+	/* Clear interrupt flags */
+	ret = clear_irq_flags(reg_idx, isr_mask);
+	if (ret)
+		goto out;
+
+ out:
+	spin_unlock_irqrestore(&rcar_sysc_lock, flags);
+
+	pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off",
+		 sysc_ch->isr_bit, ioread32(rcar_sysc_base + SYSCISCR(reg_idx)), ret);
+	return ret;
+}
+
+static bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch)
+{
+	unsigned int st;
+
+	st = ioread32(rcar_sysc_base + PDRSR(sysc_ch->isr_bit));
+
+	if (st & PDRSR_OFF)
+		return true;
+
+	return false;
+}
+
+struct rcar_sysc_pd {
+	struct generic_pm_domain genpd;
+	struct rcar_sysc_ch ch;
+	unsigned int flags;
+	char name[];
+};
+
+static inline struct rcar_sysc_pd *to_rcar_pd(struct generic_pm_domain *d)
+{
+	return container_of(d, struct rcar_sysc_pd, genpd);
+}
+
+static int rcar_sysc_pd_power_off(struct generic_pm_domain *genpd)
+{
+	struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
+
+	pr_debug("%s: %s\n", __func__, genpd->name);
+	return rcar_sysc_power(&pd->ch, false);
+}
+
+static int rcar_sysc_pd_power_on(struct generic_pm_domain *genpd)
+{
+	struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
+
+	pr_debug("%s: %s\n", __func__, genpd->name);
+	return rcar_sysc_power(&pd->ch, true);
+}
+
+static bool has_cpg_mstp;
+
+static int __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
+{
+	struct generic_pm_domain *genpd = &pd->genpd;
+	const char *name = pd->genpd.name;
+	int error;
+
+	if (pd->flags & PD_CPU) {
+		/*
+		 * This domain contains a CPU core and therefore it should
+		 * only be turned off if the CPU is not in use.
+		 */
+		pr_debug("PM domain %s contains %s\n", name, "CPU");
+		genpd->flags |= GENPD_FLAG_ALWAYS_ON;
+	} else if (pd->flags & PD_SCU) {
+		/*
+		 * This domain contains an SCU and cache-controller, and
+		 * therefore it should only be turned off if the CPU cores are
+		 * not in use.
+		 */
+		pr_debug("PM domain %s contains %s\n", name, "SCU");
+		genpd->flags |= GENPD_FLAG_ALWAYS_ON;
+	} else if (pd->flags & PD_NO_CR) {
+		/*
+		 * This domain cannot be turned off.
+		 */
+		genpd->flags |= GENPD_FLAG_ALWAYS_ON;
+	}
+
+	if (!(pd->flags & (PD_CPU | PD_SCU))) {
+		/* Enable Clock Domain for I/O devices */
+		genpd->flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
+		if (has_cpg_mstp) {
+			genpd->attach_dev = cpg_mstp_attach_dev;
+			genpd->detach_dev = cpg_mstp_detach_dev;
+		} else {
+			genpd->attach_dev = cpg_mssr_attach_dev;
+			genpd->detach_dev = cpg_mssr_detach_dev;
+		}
+	}
+
+	genpd->power_off = rcar_sysc_pd_power_off;
+	genpd->power_on = rcar_sysc_pd_power_on;
+
+	if (pd->flags & (PD_CPU | PD_NO_CR)) {
+		/* Skip CPUs (handled by SMP code) and areas without control */
+		pr_debug("%s: Not touching %s\n", __func__, genpd->name);
+		goto finalize;
+	}
+
+	if (!rcar_sysc_power_is_off(&pd->ch)) {
+		pr_debug("%s: %s is already powered\n", __func__, genpd->name);
+		goto finalize;
+	}
+
+	rcar_sysc_power(&pd->ch, true);
+
+finalize:
+	error = pm_genpd_init(genpd, &simple_qos_governor, false);
+	if (error)
+		pr_err("Failed to init PM domain %s: %d\n", name, error);
+
+	return error;
+}
+
+static const struct of_device_id rcar_sysc_matches[] __initconst = {
+#ifdef CONFIG_SYSC_R8A779A0
+	{ .compatible = "renesas,r8a779a0-sysc", .data = &r8a779a0_sysc_info },
+#endif
+	{ /* sentinel */ }
+};
+
+struct rcar_pm_domains {
+	struct genpd_onecell_data onecell_data;
+	struct generic_pm_domain *domains[R8A779A0_NUM_PD_ALWAYS_ON + 1];
+};
+
+static struct genpd_onecell_data *rcar_sysc_onecell_data;
+
+static int __init r8a779a0_sysc_pd_init(void)
+{
+	const struct rcar_sysc_info *info;
+	const struct of_device_id *match;
+	struct rcar_pm_domains *domains;
+	struct device_node *np;
+	void __iomem *base;
+	unsigned int i;
+	int error;
+
+	np = of_find_matching_node_and_match(NULL, rcar_sysc_matches, &match);
+	if (!np)
+		return -ENODEV;
+
+	info = match->data;
+
+	if (info->init) {
+		error = info->init();
+		if (error)
+			goto out_put;
+	}
+
+	has_cpg_mstp = of_find_compatible_node(NULL, NULL,
+					       "renesas,cpg-mstp-clocks");
+
+	base = of_iomap(np, 0);
+	if (!base) {
+		pr_warn("%pOF: Cannot map regs\n", np);
+		error = -ENOMEM;
+		goto out_put;
+	}
+
+	rcar_sysc_base = base;
+
+	domains = kzalloc(sizeof(*domains), GFP_KERNEL);
+	if (!domains) {
+		error = -ENOMEM;
+		goto out_put;
+	}
+
+	domains->onecell_data.domains = domains->domains;
+	domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains);
+	rcar_sysc_onecell_data = &domains->onecell_data;
+
+	for (i = 0; i < info->num_areas; i++) {
+		const struct rcar_sysc_area *area = &info->areas[i];
+		struct rcar_sysc_pd *pd;
+
+		if (!area->name) {
+			/* Skip NULLified area */
+			continue;
+		}
+
+		pd = kzalloc(sizeof(*pd) + strlen(area->name) + 1, GFP_KERNEL);
+		if (!pd) {
+			error = -ENOMEM;
+			goto out_put;
+		}
+
+		strcpy(pd->name, area->name);
+		pd->genpd.name = pd->name;
+		pd->ch.chan_offs = area->chan_offs;
+		pd->ch.chan_bit = area->chan_bit;
+		pd->ch.isr_bit = area->isr_bit;
+		pd->flags = area->flags;
+
+		error = rcar_sysc_pd_setup(pd);
+		if (error)
+			goto out_put;
+
+		domains->domains[area->isr_bit] = &pd->genpd;
+
+		if (area->parent < 0)
+			continue;
+
+		error = pm_genpd_add_subdomain(domains->domains[area->parent],
+					       &pd->genpd);
+		if (error) {
+			pr_warn("Failed to add PM subdomain %s to parent %u\n",
+				area->name, area->parent);
+			goto out_put;
+		}
+	}
+
+	error = of_genpd_add_provider_onecell(np, &domains->onecell_data);
+
+out_put:
+	of_node_put(np);
+	return error;
+}
+early_initcall(r8a779a0_sysc_pd_init);
-- 
2.7.4

[PATCH 11/14] soc: renesas: rcar-rst: Add support for R-Car V3U

[Yoshihiro Shimoda]

Add support for R-Car V3U (R8A779A0) to the R-Car RST driver.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 drivers/soc/renesas/rcar-rst.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
index a932015..8a1e402 100644
--- a/drivers/soc/renesas/rcar-rst.c
+++ b/drivers/soc/renesas/rcar-rst.c
@@ -37,6 +37,10 @@ static const struct rst_config rcar_rst_gen3 __initconst = {
 	.modemr = 0x60,
 };
 
+static const struct rst_config rcar_rst_r8a779a0 __initconst = {
+	.modemr = 0x00,		/* MODEMR0 and it has CPG related bits */
+};
+
 static const struct of_device_id rcar_rst_matches[] __initconst = {
 	/* RZ/G1 is handled like R-Car Gen2 */
 	{ .compatible = "renesas,r8a7742-rst", .data = &rcar_rst_gen2 },
@@ -67,6 +71,8 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
 	{ .compatible = "renesas,r8a77980-rst", .data = &rcar_rst_gen3 },
 	{ .compatible = "renesas,r8a77990-rst", .data = &rcar_rst_gen3 },
 	{ .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen3 },
+	/* R-Car V3U */
+	{ .compatible = "renesas,r8a779a0-rst", .data = &rcar_rst_r8a779a0 },
 	{ /* sentinel */ }
 };
 
-- 
2.7.4

[PATCH 12/14] clk: renesas: cpg-mssr: Add support for R-Car V3U

[Yoshihiro Shimoda]

Initial support for R-Car V3U (r8a779a0), including core, module
clocks and register access, because register specification differs
than R-Car Gen2/3.

Inspired by patches in the BSP by LUU HOAI.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 drivers/clk/renesas/Kconfig             |   4 +
 drivers/clk/renesas/Makefile            |   1 +
 drivers/clk/renesas/r8a779a0-cpg-mssr.c | 479 ++++++++++++++++++++++++++++++++
 drivers/clk/renesas/renesas-cpg-mssr.c  |  20 +-
 drivers/clk/renesas/renesas-cpg-mssr.h  |   2 +
 5 files changed, 503 insertions(+), 3 deletions(-)
 create mode 100644 drivers/clk/renesas/r8a779a0-cpg-mssr.c

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 28e8730..b2126fa 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -30,6 +30,7 @@ config CLK_RENESAS
 	select CLK_R8A77980 if ARCH_R8A77980
 	select CLK_R8A77990 if ARCH_R8A77990
 	select CLK_R8A77995 if ARCH_R8A77995
+	select CLK_R8A779A0 if ARCH_R8A779A0
 	select CLK_R9A06G032 if ARCH_R9A06G032
 	select CLK_SH73A0 if ARCH_SH73A0
 
@@ -145,6 +146,9 @@ config CLK_R8A77995
 	bool "R-Car D3 clock support" if COMPILE_TEST
 	select CLK_RCAR_GEN3_CPG
 
+config CLK_R8A779A0
+	bool "R-Car V3U clock support" if COMPILE_TEST
+
 config CLK_R9A06G032
 	bool "Renesas R9A06G032 clock driver"
 	help
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index c7c03ab..c803912 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_CLK_R8A77970)		+= r8a77970-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77980)		+= r8a77980-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77990)		+= r8a77990-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77995)		+= r8a77995-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A779A0)		+= r8a779a0-cpg-mssr.o
 obj-$(CONFIG_CLK_R9A06G032)		+= r9a06g032-clocks.o
 obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o
 
diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
new file mode 100644
index 0000000..2e1f579
--- /dev/null
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -0,0 +1,479 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a779a0 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ *
+ * Based on r8a7795-cpg-mssr.c
+ *
+ * Copyright (C) 2015 Glider bvba
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ */
+
+#include <linux/bug.h>
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/pm.h>
+#include <linux/slab.h>
+#include <linux/soc/renesas/rcar-rst.h>
+#include <linux/sys_soc.h>
+
+#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+
+enum rcar_r8a779a0_clk_types {
+	CLK_TYPE_R8A779A0_MAIN = CLK_TYPE_CUSTOM,
+	CLK_TYPE_R8A779A0_PLL1,
+	CLK_TYPE_R8A779A0_PLL20,
+	CLK_TYPE_R8A779A0_PLL21,
+	CLK_TYPE_R8A779A0_PLL30,
+	CLK_TYPE_R8A779A0_PLL31,
+	CLK_TYPE_R8A779A0_PLL5,
+	CLK_TYPE_R8A779A0_MDSEL,	/* Select parent/divider using mode pin */
+	CLK_TYPE_R8A779A0_Z,
+	CLK_TYPE_R8A779A0_OSC,	/* OSC EXTAL predivider and fixed divider */
+
+	/* SoC specific definitions start here */
+	CLK_TYPE_R8A779A0_SOC_BASE,
+};
+
+#define DEF_R8A779A0_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
+	DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL,	\
+		 (_parent0) << 16 | (_parent1),		\
+		 .div = (_div0) << 16 | (_div1), .offset = _md)
+
+#define DEF_R8A779A0_OSC(_name, _id, _parent, _div)		\
+	DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_OSC, _parent, .div = _div)
+
+struct rcar_r8a779a0_cpg_pll_config {
+	u8 extal_div;
+	u8 pll1_mult;
+	u8 pll1_div;
+	u8 pll5_mult;
+	u8 pll5_div;
+	u8 osc_prediv;
+};
+
+enum clk_ids {
+	/* Core Clock Outputs exported to DT */
+	LAST_DT_CORE_CLK = R8A779A0_CLK_OSCCLK,
+
+	/* External Input Clocks */
+	CLK_EXTAL,
+	CLK_EXTALR,
+
+	/* Internal Core Clocks */
+	CLK_MAIN,
+	CLK_PLL1,
+	CLK_PLL20,
+	CLK_PLL21,
+	CLK_PLL30,
+	CLK_PLL31,
+	CLK_PLL5,
+	CLK_PLL1_DIV2,
+	CLK_PLL20_DIV2,
+	CLK_PLL21_DIV2,
+	CLK_PLL30_DIV2,
+	CLK_PLL31_DIV2,
+	CLK_PLL5_DIV2,
+	CLK_PLL5_DIV4,
+	CLK_S1,
+	CLK_S2,
+	CLK_S3,
+	CLK_SDSRC,
+	CLK_RPCSRC,
+	CLK_OCO,
+
+	/* Module Clocks */
+	MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
+	/* External Clock Inputs */
+	DEF_INPUT("extal",  CLK_EXTAL),
+	DEF_INPUT("extalr", CLK_EXTALR),
+
+	/* Internal Core Clocks */
+	DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL),
+	DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN),
+	DEF_BASE(".pll20",      CLK_PLL20, CLK_TYPE_R8A779A0_PLL20, CLK_MAIN),
+	DEF_BASE(".pll21",      CLK_PLL21, CLK_TYPE_R8A779A0_PLL21, CLK_MAIN),
+	DEF_BASE(".pll30",      CLK_PLL30, CLK_TYPE_R8A779A0_PLL30, CLK_MAIN),
+	DEF_BASE(".pll31",      CLK_PLL31, CLK_TYPE_R8A779A0_PLL31, CLK_MAIN),
+	DEF_BASE(".pll5",       CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN),
+
+	DEF_FIXED(".pll1_div2",	 CLK_PLL1_DIV2,	   CLK_PLL1,   2, 1),
+	DEF_FIXED(".pll20_div2", CLK_PLL20_DIV2,   CLK_PLL20,  2, 1),
+	DEF_FIXED(".pll21_div2", CLK_PLL21_DIV2,   CLK_PLL21,  2, 1),
+	DEF_FIXED(".pll30_div2", CLK_PLL30_DIV2,   CLK_PLL30,  2, 1),
+	DEF_FIXED(".pll31_div2", CLK_PLL31_DIV2,   CLK_PLL31,  2, 1),
+	DEF_FIXED(".pll5_div2",	 CLK_PLL5_DIV2,	   CLK_PLL5,   2, 1),
+	DEF_FIXED(".pll5_div4",  CLK_PLL5_DIV4,    CLK_PLL5_DIV2,   2, 1),
+	DEF_FIXED(".s1",	CLK_S1,		   CLK_PLL1_DIV2,   2, 1),
+	DEF_FIXED(".s2",	CLK_S2,		   CLK_PLL1_DIV2,   133, 50),
+	DEF_FIXED(".s3",	CLK_S3,		   CLK_PLL1_DIV2,   4, 1),
+	DEF_RATE(".oco",	CLK_OCO,           32768),
+
+	/* Core Clock Outputs */
+	DEF_FIXED("zx",		R8A779A0_CLK_ZX,     CLK_PLL20_DIV2,  2, 1),
+	DEF_FIXED("s1d1",	R8A779A0_CLK_S1D1,   CLK_S1, 1, 1),
+	DEF_FIXED("s1d2",	R8A779A0_CLK_S1D2,   CLK_S1, 2, 1),
+	DEF_FIXED("s1d4",	R8A779A0_CLK_S1D4,   CLK_S1, 4, 1),
+	DEF_FIXED("s1d8",	R8A779A0_CLK_S1D8,   CLK_S1, 8, 1),
+	DEF_FIXED("s1d12",	R8A779A0_CLK_S1D12,  CLK_S1, 12, 1),
+	DEF_FIXED("s2d1",	R8A779A0_CLK_S2D1,   CLK_S2, 1, 1),
+	DEF_FIXED("s2d2",	R8A779A0_CLK_S2D2,   CLK_S2, 2, 1),
+	DEF_FIXED("s2d4",	R8A779A0_CLK_S2D4,   CLK_S2, 4, 1),
+	DEF_FIXED("s3d1",	R8A779A0_CLK_S3D1,   CLK_S3, 1, 1),
+	DEF_FIXED("s3d2",	R8A779A0_CLK_S3D2,   CLK_S3, 2, 1),
+	DEF_FIXED("s3d4",	R8A779A0_CLK_S3D4,   CLK_S3, 4, 1),
+	DEF_FIXED("zs",		R8A779A0_CLK_ZS,     CLK_PLL1_DIV2,   4, 1),
+	DEF_FIXED("zt",		R8A779A0_CLK_ZT,     CLK_PLL1_DIV2,   2, 1),
+	DEF_FIXED("ztr",	R8A779A0_CLK_ZTR,    CLK_PLL1_DIV2,   2, 1),
+	DEF_FIXED("zr",		R8A779A0_CLK_ZR,     CLK_PLL1_DIV2,   1, 1),
+	DEF_FIXED("dsi",	R8A779A0_CLK_DSI,    CLK_PLL5_DIV4,   1, 1),
+	DEF_FIXED("cnndsp",	R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4,   1, 1),
+	DEF_FIXED("vip",	R8A779A0_CLK_VIP,    CLK_PLL5,        5, 1),
+	DEF_FIXED("adgh",	R8A779A0_CLK_ADGH,   CLK_PLL5_DIV4,   1, 1),
+	DEF_FIXED("icu",	R8A779A0_CLK_ICU,    CLK_PLL5_DIV4,   2, 1),
+	DEF_FIXED("icud2",	R8A779A0_CLK_ICUD2,  CLK_PLL5_DIV4,   4, 1),
+	DEF_FIXED("vcbus",	R8A779A0_CLK_VCBUS,  CLK_PLL5_DIV4,   1, 1),
+
+	DEF_FIXED("cbfusa",	R8A779A0_CLK_CBFUSA, CLK_MAIN,	 2, 1),
+
+	DEF_DIV6P1("mso",	R8A779A0_CLK_MSO,    CLK_PLL5_DIV4, 0x87c),
+	DEF_DIV6P1("canfd",	R8A779A0_CLK_CANFD,  CLK_PLL5_DIV4, 0x878),
+	DEF_DIV6P1("csi0",	R8A779A0_CLK_CSI0,   CLK_PLL5_DIV4, 0x880),
+	DEF_DIV6P1("fray",	R8A779A0_CLK_FRAY,   CLK_PLL5_DIV4, 0x88c),
+	DEF_DIV6P1("post",	R8A779A0_CLK_POST,   CLK_PLL5_DIV4, 0x890),
+	DEF_DIV6P1("post2",	R8A779A0_CLK_POST2,  CLK_PLL5_DIV4, 0x894),
+	DEF_DIV6P1("post3",	R8A779A0_CLK_POST3,  CLK_PLL5_DIV4, 0x898),
+
+	DEF_R8A779A0_OSC("osc",	R8A779A0_CLK_OSCCLK, CLK_EXTAL,     8),
+	DEF_R8A779A0_MDSEL("r",	R8A779A0_CLK_RCLK, 29, CLK_EXTALR, 1, CLK_OCO, 1),
+};
+
+static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
+	DEF_MOD("scif0",	702,	R8A779A0_CLK_S1D8),
+	DEF_MOD("scif1",	703,	R8A779A0_CLK_S1D8),
+	DEF_MOD("scif3",	704,	R8A779A0_CLK_S1D8),
+	DEF_MOD("scif4",	705,	R8A779A0_CLK_S1D8),
+};
+
+static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {
+	MOD_CLK_ID(408),	/* INTC-AP (GIC) */
+};
+
+#define CPG_PLL20CR		0x0834
+#define CPG_PLL21CR		0x0838
+#define CPG_PLL30CR		0x083c
+#define CPG_PLL31CR		0x0840
+
+static spinlock_t cpg_lock;
+
+static void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set)
+{
+	unsigned long flags;
+	u32 val;
+
+	spin_lock_irqsave(&cpg_lock, flags);
+	val = readl(reg);
+	val &= ~clear;
+	val |= set;
+	writel(val, reg);
+	spin_unlock_irqrestore(&cpg_lock, flags);
+};
+
+/*
+ * Z Clock & Z2 Clock
+ *
+ * Traits of this clock:
+ * prepare - clk_prepare only ensures that parents are prepared
+ * enable - clk_enable only ensures that parents are enabled
+ * rate - rate is adjustable.  clk->rate = (parent->rate * mult / 32 ) / 2
+ * parent - fixed parent.  No clk_set_parent support
+ */
+#define CPG_FRQCRB			0x00000804
+#define CPG_FRQCRB_KICK			BIT(31)
+#define CPG_FRQCRC			0x00000808
+
+struct cpg_z_clk {
+	struct clk_hw hw;
+	void __iomem *reg;
+	void __iomem *kick_reg;
+	unsigned long mask;
+	unsigned int fixed_div;
+};
+
+#define to_z_clk(_hw)	container_of(_hw, struct cpg_z_clk, hw)
+
+static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
+					   unsigned long parent_rate)
+{
+	struct cpg_z_clk *zclk = to_z_clk(hw);
+	unsigned int mult;
+	u32 val;
+
+	val = readl(zclk->reg) & zclk->mask;
+	mult = 32 - (val >> __ffs(zclk->mask));
+
+	return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,
+				     32 * zclk->fixed_div);
+}
+
+static int cpg_z_clk_determine_rate(struct clk_hw *hw,
+				    struct clk_rate_request *req)
+{
+	struct cpg_z_clk *zclk = to_z_clk(hw);
+	unsigned int min_mult, max_mult, mult;
+	unsigned long prate;
+
+	prate = req->best_parent_rate / zclk->fixed_div;
+	min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
+	max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);
+	if (max_mult < min_mult)
+		return -EINVAL;
+
+	mult = div64_ul(req->rate * 32ULL, prate);
+	mult = clamp(mult, min_mult, max_mult);
+
+	req->rate = div_u64((u64)prate * mult, 32);
+	return 0;
+}
+
+static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+			      unsigned long parent_rate)
+{
+	struct cpg_z_clk *zclk = to_z_clk(hw);
+	unsigned int mult;
+	unsigned int i;
+
+	mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,
+				       parent_rate);
+	mult = clamp(mult, 1U, 32U);
+
+	if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
+		return -EBUSY;
+
+	cpg_reg_modify(zclk->reg, zclk->mask,
+		       ((32 - mult) << __ffs(zclk->mask)) & zclk->mask);
+
+	/*
+	 * Set KICK bit in FRQCRB to update hardware setting and wait for
+	 * clock change completion.
+	 */
+	cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK);
+
+	/*
+	 * Note: There is no HW information about the worst case latency.
+	 *
+	 * Using experimental measurements, it seems that no more than
+	 * ~10 iterations are needed, independently of the CPU rate.
+	 * Since this value might be dependent of external xtal rate, pll1
+	 * rate or even the other emulation clocks rate, use 1000 as a
+	 * "super" safe value.
+	 */
+	for (i = 1000; i; i--) {
+		if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
+			return 0;
+
+		cpu_relax();
+	}
+
+	return -ETIMEDOUT;
+}
+
+static const struct clk_ops cpg_z_clk_ops = {
+	.recalc_rate = cpg_z_clk_recalc_rate,
+	.determine_rate = cpg_z_clk_determine_rate,
+	.set_rate = cpg_z_clk_set_rate,
+};
+
+static struct clk * __init cpg_z_clk_register(const char *name,
+					      const char *parent_name,
+					      void __iomem *reg,
+					      unsigned int div,
+					      unsigned int offset)
+{
+	struct clk_init_data init;
+	struct cpg_z_clk *zclk;
+	struct clk *clk;
+
+	zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
+	if (!zclk)
+		return ERR_PTR(-ENOMEM);
+
+	init.name = name;
+	init.ops = &cpg_z_clk_ops;
+	init.flags = 0;
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	zclk->reg = reg + CPG_FRQCRC;
+	zclk->kick_reg = reg + CPG_FRQCRB;
+	zclk->hw.init = &init;
+	zclk->mask = GENMASK(offset + 4, offset);
+	zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */
+	clk = clk_register(NULL, &zclk->hw);
+	if (IS_ERR(clk))
+		kfree(zclk);
+
+	return clk;
+}
+
+static const struct rcar_r8a779a0_cpg_pll_config *cpg_pll_config __initdata;
+static unsigned int cpg_clk_extalr __initdata;
+static u32 cpg_mode __initdata;
+
+struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
+	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
+	struct clk **clks, void __iomem *base,
+	struct raw_notifier_head *notifiers)
+{
+	const struct clk *parent;
+	unsigned int mult = 1;
+	unsigned int div = 1;
+	u32 value;
+
+	parent = clks[core->parent & 0xffff];	/* some types use high bits */
+	if (IS_ERR(parent))
+		return ERR_CAST(parent);
+
+	switch (core->type) {
+	case CLK_TYPE_R8A779A0_MAIN:
+		div = cpg_pll_config->extal_div;
+		break;
+
+	case CLK_TYPE_R8A779A0_PLL1:
+		mult = cpg_pll_config->pll1_mult;
+		div = cpg_pll_config->pll1_div;
+		break;
+
+	case CLK_TYPE_R8A779A0_PLL20:
+		value = readl(base + CPG_PLL20CR);
+		mult = (((value >> 24) & 0x7f) + 1) * 2;
+		break;
+
+	case CLK_TYPE_R8A779A0_PLL21:
+		value = readl(base + CPG_PLL21CR);
+		mult = (((value >> 24) & 0x7f) + 1) * 2;
+		break;
+
+	case CLK_TYPE_R8A779A0_PLL30:
+		value = readl(base + CPG_PLL30CR);
+		mult = (((value >> 24) & 0x7f) + 1) * 2;
+		break;
+
+	case CLK_TYPE_R8A779A0_PLL31:
+		value = readl(base + CPG_PLL31CR);
+		mult = (((value >> 24) & 0x7f) + 1) * 2;
+		break;
+
+	case CLK_TYPE_R8A779A0_PLL5:
+		mult = cpg_pll_config->pll5_mult;
+		div = cpg_pll_config->pll5_div;
+		break;
+
+	case CLK_TYPE_R8A779A0_MDSEL:
+		/*
+		 * Clock selectable between two parents and two fixed dividers
+		 * using a mode pin
+		 */
+		if (cpg_mode & BIT(core->offset)) {
+			div = core->div & 0xffff;
+		} else {
+			parent = clks[core->parent >> 16];
+			if (IS_ERR(parent))
+				return ERR_CAST(parent);
+			div = core->div >> 16;
+		}
+		mult = 1;
+		break;
+
+	case CLK_TYPE_R8A779A0_Z:
+		return cpg_z_clk_register(core->name, __clk_get_name(parent),
+					  base, core->div, core->offset);
+
+	case CLK_TYPE_R8A779A0_OSC:
+		/*
+		 * Clock combining OSC EXTAL predivider and a fixed divider
+		 */
+		div = cpg_pll_config->osc_prediv * core->div;
+		break;
+
+	default:
+		return ERR_PTR(-EINVAL);
+	}
+
+	return clk_register_fixed_factor(NULL, core->name,
+					 __clk_get_name(parent), 0, mult, div);
+}
+
+/*
+ * CPG Clock Data
+ */
+/*
+ *   MD	 EXTAL		PLL1	PLL20	PLL30	PLL4	PLL5	PLL6	OSC
+ * 14 13 (MHz)			   21	   31
+ * --------------------------------------------------------
+ * 0  0	 16.66 x 1	x128	x216	x128	x144	x192	x128	/16
+ * 0  1	 20    x 1	x106	x180	x106	x120	x160	x106	/19
+ * 1  0	 Prohibited setting
+ * 1  1	 33.33 / 2	x128	x216	x128	x144	x192	x128	/32
+ */
+#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 13) | \
+					 (((md) & BIT(13)) >> 13))
+
+static const struct rcar_r8a779a0_cpg_pll_config cpg_pll_configs[4] = {
+	/* EXTAL div	PLL1 mult/div	PLL5 mult/div	OSC prediv */
+	{ 1,		128,	1,	192,	1,	16,	},
+	{ 1,		106,	1,	160,	1,	19,	},
+	{ 0,		0,	0,	0,	0,	0,	},
+	{ 2,		128,	1,	192,	1,	32,	},
+};
+
+static int __init r8a779a0_cpg_mssr_init(struct device *dev)
+{
+	int error;
+
+	error = rcar_rst_read_mode_pins(&cpg_mode);
+	if (error)
+		return error;
+
+	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+	cpg_clk_extalr = CLK_EXTALR;
+	spin_lock_init(&cpg_lock);
+
+	return 0;
+}
+
+const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = {
+	/* Core Clocks */
+	.core_clks = r8a779a0_core_clks,
+	.num_core_clks = ARRAY_SIZE(r8a779a0_core_clks),
+	.last_dt_core_clk = LAST_DT_CORE_CLK,
+	.num_total_core_clks = MOD_CLK_BASE,
+
+	/* Module Clocks */
+	.mod_clks = r8a779a0_mod_clks,
+	.num_mod_clks = ARRAY_SIZE(r8a779a0_mod_clks),
+	.num_hw_mod_clks = 12 * 32,
+
+	/* Critical Module Clocks */
+	.crit_mod_clks = r8a779a0_crit_mod_clks,
+	.num_crit_mod_clks = ARRAY_SIZE(r8a779a0_crit_mod_clks),
+
+	/* Callbacks */
+	.init = r8a779a0_cpg_mssr_init,
+	.cpg_clk_register = rcar_r8a779a0_cpg_clk_register,
+
+	/* The device has only MSTP Control Register */
+	.mstpctrl = true,
+};
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 5a306d2..c259e05 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -57,8 +57,14 @@ static const u16 mstpsr[] = {
 	0x9A0, 0x9A4, 0x9A8, 0x9AC,
 };
 
-#define	MSTPSR(i)	mstpsr[i]
+static const u16 mstpsr_mstpcr_only[] = {
+	0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
+	0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38,
+};
+
+static bool mstpcr_only;
 
+#define	MSTPSR(i)	(mstpcr_only ? mstpsr_mstpcr_only[i] : mstpsr[i])
 
 /*
  * System Module Stop Control Register offsets
@@ -69,7 +75,8 @@ static const u16 smstpcr[] = {
 	0x990, 0x994, 0x998, 0x99C,
 };
 
-#define	SMSTPCR(i)	smstpcr[i]
+#define	SMSTPCR(i)	(mstpcr_only ? (mstpsr_mstpcr_only[i] - 0x100) : \
+			 smstpcr[i])
 
 /*
  * Standby Control Register offsets (RZ/A)
@@ -140,7 +147,7 @@ struct cpg_mssr_priv {
 	struct {
 		u32 mask;
 		u32 val;
-	} smstpcr_saved[ARRAY_SIZE(smstpcr)];
+	} smstpcr_saved[ARRAY_SIZE(mstpsr_mstpcr_only)];
 
 	struct clk *clks[];
 };
@@ -804,6 +811,12 @@ static const struct of_device_id cpg_mssr_match[] = {
 		.data = &r8a77995_cpg_mssr_info,
 	},
 #endif
+#ifdef CONFIG_CLK_R8A779A0
+	{
+		.compatible = "renesas,r8a779a0-cpg-mssr",
+		.data = &r8a779a0_cpg_mssr_info,
+	},
+#endif
 	{ /* sentinel */ }
 };
 
@@ -938,6 +951,7 @@ static int __init cpg_mssr_common_init(struct device *dev,
 	priv->last_dt_core_clk = info->last_dt_core_clk;
 	RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
 	priv->stbyctrl = info->stbyctrl;
+	mstpcr_only = info->mstpctrl;
 
 	for (i = 0; i < nclks; i++)
 		priv->clks[i] = ERR_PTR(-ENOENT);
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index 1cc5694..061eb83 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -131,6 +131,7 @@ struct cpg_mssr_info {
 	unsigned int last_dt_core_clk;
 	unsigned int num_total_core_clks;
 	bool stbyctrl;
+	bool mstpctrl;
 
 	/* Module Clocks */
 	const struct mssr_mod_clk *mod_clks;
@@ -174,6 +175,7 @@ extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a77990_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
+extern const struct cpg_mssr_info r8a779a0_cpg_mssr_info;
 
 void __init cpg_mssr_early_init(struct device_node *np,
 				const struct cpg_mssr_info *info);
-- 
2.7.4

[PATCH 13/14] arm64: dts: renesas: Add Renesas R8A779A0 SoC support

[Yoshihiro Shimoda]

Add initial support for the Renesas R8A77990 (R-Car V3U) support.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 132 ++++++++++++++++++++++++++++++
 1 file changed, 132 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a779a0.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
new file mode 100644
index 0000000..265937a
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the R-Car V3U (R8A779A0) SoC
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/r8a779a0-sysc.h>
+
+/ {
+	compatible = "renesas,r8a779a0";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		a76_0: cpu@0 {
+			compatible = "arm,cortex-a76";
+			reg = <0>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A779A0_PD_A1E0D0C0>;
+			next-level-cache = <&L3_CA76_0>;
+		};
+
+		L3_CA76_0: cache-controller-0 {
+			compatible = "cache";
+			power-domains = <&sysc R8A779A0_PD_A2E0D0>;
+			cache-unified;
+			cache-level = <3>;
+		};
+	};
+
+	extal_clk: extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	extalr_clk: extalr {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	pmu_a76 {
+		compatible = "arm,cortex-a76-pmu";
+		interrupts-extended = <&gic GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+				      <&gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+				      <&gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+				      <&gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	/* External SCIF clock - to be overridden by boards that provide it */
+	scif_clk: scif {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cpg: clock-controller@e6150000 {
+			compatible = "renesas,r8a779a0-cpg-mssr";
+			reg = <0 0xe6150000 0 0x4000>;
+			clocks = <&extal_clk>, <&extalr_clk>;
+			clock-names = "extal", "extalr";
+			#clock-cells = <2>;
+			#power-domain-cells = <0>;
+			#reset-cells = <1>;
+		};
+
+		rst: reset-controller@e6160000 {
+			compatible = "renesas,r8a779a0-rst";
+			reg = <0 0xe6160000 0 0x4000>;
+		};
+
+		sysc: system-controller@e6180000 {
+			compatible = "renesas,r8a779a0-sysc";
+			reg = <0 0xe6180000 0 0x3078>;
+			#power-domain-cells = <1>;
+		};
+
+		scif0: serial@e6e60000 {
+			compatible = "renesas,scif-r8a779a0",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6e60000 0 64>;
+			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 702>,
+				 <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+			status = "disabled";
+		};
+
+		gic: interrupt-controller@f1000000 {
+			compatible = "arm,gic-v3";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0x0 0xf1000000 0 0x20000>,
+			      <0x0 0xf1060000 0 0x110000>;
+			interrupts = <GIC_PPI 9
+				      (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+		};
+
+		prr: chipid@fff00044 {
+			compatible = "renesas,prr";
+			reg = <0 0xfff00044 0 4>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+};
-- 
2.7.4

[PATCH 14/14] arm64: dts: renesas: Add Renesas Falcon boards support

[Yoshihiro Shimoda]

Initial support for the Renesas Falcon CPU and BreakOut boards
support.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 arch/arm64/boot/dts/renesas/Makefile            |  2 ++
 arch/arm64/boot/dts/renesas/falcon-cpu.dtsi     | 44 +++++++++++++++++++++++++
 arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts | 23 +++++++++++++
 3 files changed, 69 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/falcon-cpu.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index d790229..6757d66 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -53,3 +53,5 @@ dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-v3hsk.dtb
 dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb
 
 dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
+
+dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb
diff --git a/arch/arm64/boot/dts/renesas/falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/falcon-cpu.dtsi
new file mode 100644
index 0000000..0286279
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/falcon-cpu.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Falcon CPU board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+/ {
+	model = "Renesas Falcon CPU board";
+	compatible = "renesas,falcon-cpu";
+
+	memory@48000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x0 0x78000000>;
+	};
+
+	memory@500000000 {
+		device_type = "memory";
+		reg = <0x5 0x00000000 0x0 0x80000000>;
+	};
+
+	memory@600000000 {
+		device_type = "memory";
+		reg = <0x6 0x00000000 0x0 0x80000000>;
+	};
+
+	memory@700000000 {
+		device_type = "memory";
+		reg = <0x7 0x00000000 0x0 0x80000000>;
+	};
+};
+
+&extal_clk {
+	clock-frequency = <16666666>;
+};
+
+&extalr_clk {
+	clock-frequency = <32768>;
+};
+
+&scif0 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
new file mode 100644
index 0000000..56c0e5f
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Falcon board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a779a0.dtsi"
+#include "falcon-cpu.dtsi"
+
+/ {
+	model = "Renesas Falcon board based on r8a779a0";
+	compatible = "renesas,falcon-cpu", "renesas,r8a779a0";
+
+	aliases {
+		serial0 = &scif0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
-- 
2.7.4

Re: [PATCH 01/14] dt-bindings: arm: renesas: Document R-Car V3U SoC DT bindings

[Geert Uytterhoeven]

On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Add device tree bindings documentation for Renesas R-Car V3U
> (r8a779a0).
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.10.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 02/14] dt-bindings: arm: renesas: Document Renesas Falcon boards

[Geert Uytterhoeven]

Hi Shimoda-san,

On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Add device tree bindings documentation for Renesas R-Car V3U
> Falcon CPU and BreakOut boards.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Thanks for your patch!

> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> @@ -283,6 +283,9 @@ properties:
>
>        - description: R-Car V3U (R8A779A0)
>          items:
> +          - enum:
> +              - renesas,falcon-cpu # Falcon CPU board (RTP0RC779A0CPB0010S)
> +              - renesas,falcon-breakout # Falcon BreakOut board (RTP0RC779A0BOB0010S)
>            - const: renesas,r8a779a0

How is this intended to be used?

The above means its users should declare either

    compatible = "renesas,falcon-cpu", "renesas,r8a779a0";

or

    compatible = "renesas,falcon-breakout", "renesas,r8a779a0";

However, falcon-cpu.dtsi has just

    compatible = "renesas,falcon-cpu";

Who will use "renesas,falcon-breakout"?

>
>        - description: RZ/N1D (R9A06G032)

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 02/14] dt-bindings: arm: renesas: Document Renesas Falcon boards

[Yoshihiro Shimoda]

Hi Geert-san,

Thank you for your review!

> From: Geert Uytterhoeven, Sent: Tuesday, September 8, 2020 12:31 AM
> 
> Hi Shimoda-san,
> 
> On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > Add device tree bindings documentation for Renesas R-Car V3U
> > Falcon CPU and BreakOut boards.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> 
> Thanks for your patch!
> 
> > --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> > @@ -283,6 +283,9 @@ properties:
> >
> >        - description: R-Car V3U (R8A779A0)
> >          items:
> > +          - enum:
> > +              - renesas,falcon-cpu # Falcon CPU board (RTP0RC779A0CPB0010S)
> > +              - renesas,falcon-breakout # Falcon BreakOut board (RTP0RC779A0BOB0010S)
> >            - const: renesas,r8a779a0
> 
> How is this intended to be used?

I intended to use "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0"
in the future. However, if so, I should fix the description like Kingfisher.

> The above means its users should declare either
> 
>     compatible = "renesas,falcon-cpu", "renesas,r8a779a0";
> 
> or
> 
>     compatible = "renesas,falcon-breakout", "renesas,r8a779a0";

I understood it. I mistook the description...

> However, falcon-cpu.dtsi has just
> 
>     compatible = "renesas,falcon-cpu";
> 
> Who will use "renesas,falcon-breakout"?

I intended to add falcon-breakout.dtsi and the file intended to use
"renesas,falcon-breakout" like Kingfisher + ULCB in the future.

However, I realized a combination between the cpu board and
the breakout board differs than ULCB + Kingfisher like below:

- The ULCB without the Kingfisher can work.
-- So, some .dts files exist like r8a77951-ulcb.dts.
-- And, r8a77951-ulcb-kf.dts includes r8a77951-ulcb.dts for ULCB + Kingfisher.

- The Falcon CPU board without the breakout board cannot work actually.
-- But, on this initial patch series enables the CPU board hardware (memory nodes & SCIF0) only.
-- The breakout board has some hardware like Ethernet and CAN.
-- The breakout board also has some connectors for sub boards.
-- So, I intended to add falcon-breakout.dtsi to support Ethernet in the future.

In this case, I wonder if we should describe just "renesas,falcon" only
because we will not have r8a779a0-falcon-{cpu,breakout}.dts files.
But, what do you think?

Best regards,
Yoshihiro Shimoda

Re: [PATCH 02/14] dt-bindings: arm: renesas: Document Renesas Falcon boards

[Geert Uytterhoeven]

Hi Shimoda-san,

On Tue, Sep 8, 2020 at 3:01 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> > From: Geert Uytterhoeven, Sent: Tuesday, September 8, 2020 12:31 AM
> > On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
> > <yoshihiro.shimoda.uh@renesas.com> wrote:
> > > Add device tree bindings documentation for Renesas R-Car V3U
> > > Falcon CPU and BreakOut boards.
> > >
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> > > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> > > @@ -283,6 +283,9 @@ properties:
> > >
> > >        - description: R-Car V3U (R8A779A0)
> > >          items:
> > > +          - enum:
> > > +              - renesas,falcon-cpu # Falcon CPU board (RTP0RC779A0CPB0010S)
> > > +              - renesas,falcon-breakout # Falcon BreakOut board (RTP0RC779A0BOB0010S)
> > >            - const: renesas,r8a779a0
> >
> > How is this intended to be used?
>
> I intended to use "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0"
> in the future. However, if so, I should fix the description like Kingfisher.
>
> > The above means its users should declare either
> >
> >     compatible = "renesas,falcon-cpu", "renesas,r8a779a0";
> >
> > or
> >
> >     compatible = "renesas,falcon-breakout", "renesas,r8a779a0";
>
> I understood it. I mistook the description...
>
> > However, falcon-cpu.dtsi has just
> >
> >     compatible = "renesas,falcon-cpu";
> >
> > Who will use "renesas,falcon-breakout"?
>
> I intended to add falcon-breakout.dtsi and the file intended to use
> "renesas,falcon-breakout" like Kingfisher + ULCB in the future.
>
> However, I realized a combination between the cpu board and
> the breakout board differs than ULCB + Kingfisher like below:
>
> - The ULCB without the Kingfisher can work.
> -- So, some .dts files exist like r8a77951-ulcb.dts.
> -- And, r8a77951-ulcb-kf.dts includes r8a77951-ulcb.dts for ULCB + Kingfisher.
>
> - The Falcon CPU board without the breakout board cannot work actually.
> -- But, on this initial patch series enables the CPU board hardware (memory nodes & SCIF0) only.
> -- The breakout board has some hardware like Ethernet and CAN.
> -- The breakout board also has some connectors for sub boards.
> -- So, I intended to add falcon-breakout.dtsi to support Ethernet in the future.
>
> In this case, I wonder if we should describe just "renesas,falcon" only
> because we will not have r8a779a0-falcon-{cpu,breakout}.dts files.
> But, what do you think?

What kind of connector does the Falcon CPU board have?
Perhaps it can be plugged into another base board, too?

What about modelling it like the iwave,g22m SoM, and the iwave,g22d
SODIMM board?
arch/arm/boot/dts/r8a7745-iwg*

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 03/14] dt-bindings: power: renesas,rcar-sysc: Document r8a779a0 SYSC binding

[Geert Uytterhoeven]

On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Document bindings for the R-Car V3U (aka R8A779A0) SYSC block.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.10.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 04/14] dt-bindings: power: Add r8a779a0 SYSC power domain definitions

[Geert Uytterhoeven]

Hi Shimoda-san,

Thanks for your patch!

On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Adds power domain indices fpr R-Car V3U (r8a779a0).

Add ... for

> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

> --- /dev/null
> +++ b/include/dt-bindings/power/r8a779a0-sysc.h
> @@ -0,0 +1,61 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2020 Renesas Electronics Corp.
> + */
> +#ifndef __DT_BINDINGS_POWER_R8A779A0_SYSC_H__
> +#define __DT_BINDINGS_POWER_R8A779A0_SYSC_H__
> +
> +/*
> + * These power domain indices match the numbers of the interrupt bits
> + * representing the power areas in the various Interrupt Registers
> + * (e.g. SYSCISCR0, Interrupt Status/Clear Register 0)

... match the Power Domain Register Numbers (PDR)?

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in for v5.10, in a branch shared by driver and DT.

If you agree, I can fix the above while applying.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 02/14] dt-bindings: arm: renesas: Document Renesas Falcon boards

[Yoshihiro Shimoda]

Hi Geert-san,

> From: Geert Uytterhoeven, Sent: Tuesday, September 8, 2020 4:12 PM
> 
> Hi Shimoda-san,
> 
> On Tue, Sep 8, 2020 at 3:01 AM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > > From: Geert Uytterhoeven, Sent: Tuesday, September 8, 2020 12:31 AM
> > > On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
> > > <yoshihiro.shimoda.uh@renesas.com> wrote:
> > > > Add device tree bindings documentation for Renesas R-Car V3U
> > > > Falcon CPU and BreakOut boards.
> > > >
> > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > >
> > > Thanks for your patch!
> > >
> > > > --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> > > > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> > > > @@ -283,6 +283,9 @@ properties:
> > > >
> > > >        - description: R-Car V3U (R8A779A0)
> > > >          items:
> > > > +          - enum:
> > > > +              - renesas,falcon-cpu # Falcon CPU board (RTP0RC779A0CPB0010S)
> > > > +              - renesas,falcon-breakout # Falcon BreakOut board (RTP0RC779A0BOB0010S)
> > > >            - const: renesas,r8a779a0
> > >
> > > How is this intended to be used?
> >
> > I intended to use "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0"
> > in the future. However, if so, I should fix the description like Kingfisher.
> >
> > > The above means its users should declare either
> > >
> > >     compatible = "renesas,falcon-cpu", "renesas,r8a779a0";
> > >
> > > or
> > >
> > >     compatible = "renesas,falcon-breakout", "renesas,r8a779a0";
> >
> > I understood it. I mistook the description...
> >
> > > However, falcon-cpu.dtsi has just
> > >
> > >     compatible = "renesas,falcon-cpu";
> > >
> > > Who will use "renesas,falcon-breakout"?
> >
> > I intended to add falcon-breakout.dtsi and the file intended to use
> > "renesas,falcon-breakout" like Kingfisher + ULCB in the future.
> >
> > However, I realized a combination between the cpu board and
> > the breakout board differs than ULCB + Kingfisher like below:
> >
> > - The ULCB without the Kingfisher can work.
> > -- So, some .dts files exist like r8a77951-ulcb.dts.
> > -- And, r8a77951-ulcb-kf.dts includes r8a77951-ulcb.dts for ULCB + Kingfisher.
> >
> > - The Falcon CPU board without the breakout board cannot work actually.
> > -- But, on this initial patch series enables the CPU board hardware (memory nodes & SCIF0) only.
> > -- The breakout board has some hardware like Ethernet and CAN.
> > -- The breakout board also has some connectors for sub boards.
> > -- So, I intended to add falcon-breakout.dtsi to support Ethernet in the future.
> >
> > In this case, I wonder if we should describe just "renesas,falcon" only
> > because we will not have r8a779a0-falcon-{cpu,breakout}.dts files.
> > But, what do you think?
> 
> What kind of connector does the Falcon CPU board have?
> Perhaps it can be plugged into another base board, too?

The Falcon CPU board has 2 EXIO connectors. The EXIO connector
has 400 pins. So, I think it can be plugged into another base board.

> What about modelling it like the iwave,g22m SoM, and the iwave,g22d
> SODIMM board?
> arch/arm/boot/dts/r8a7745-iwg*

Thank you for the suggestion. So, I'll fix the patch like below.
---

       - description: R-Car V3U (R8A779A0)
         items:
+          - enum:
+              - renesas,r8a779a0-cpu # Falcon CPU board (RTP0RC779A0CPB0010S
+          - const: renesas,r8a779a0
+
+      - items:
+          - enum:
+              - renesas,r8a779a0-breakout # Falcon BreakOut board (RTP0RC779A0BOB0010S)
+          - const: renesas,r8a779a0-cpu
           - const: renesas,r8a779a0

       - description: RZ/N1D (R9A06G032)
---

And, I will fix the compatible of r8a779a0-falcon.dts in the patch 14/14 like below.
---
+	compatible = "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0";
---

But, what do you think?

Best regards,
Yoshihiro Shimoda

Re: [PATCH 05/14] dt-bindings: reset: renesas,rst: Document r8a779a0 reset module

[Geert Uytterhoeven]

On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Document bindings for the R-Car V3U (R8A779A0) reset module.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.10.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 04/14] dt-bindings: power: Add r8a779a0 SYSC power domain definitions

[Yoshihiro Shimoda]

Hi Geert-san,

> From: Geert Uytterhoeven, Sent: Tuesday, September 8, 2020 5:39 PM
> 
> Hi Shimoda-san,
> 
> Thanks for your patch!
> 
> On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > Adds power domain indices fpr R-Car V3U (r8a779a0).
> 
> Add ... for
> 
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> 
> > --- /dev/null
> > +++ b/include/dt-bindings/power/r8a779a0-sysc.h
> > @@ -0,0 +1,61 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (C) 2020 Renesas Electronics Corp.
> > + */
> > +#ifndef __DT_BINDINGS_POWER_R8A779A0_SYSC_H__
> > +#define __DT_BINDINGS_POWER_R8A779A0_SYSC_H__
> > +
> > +/*
> > + * These power domain indices match the numbers of the interrupt bits
> > + * representing the power areas in the various Interrupt Registers
> > + * (e.g. SYSCISCR0, Interrupt Status/Clear Register 0)
> 
> ... match the Power Domain Register Numbers (PDR)?
> 
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> i.e. will queue in for v5.10, in a branch shared by driver and DT.
> 
> If you agree, I can fix the above while applying.

Thank you for pointed it out! I agree about fixing these.

Best regards,
Yoshihiro Shimoda

Re: [PATCH 06/14] dt-bindings: clock: renesas,cpg-mssr: Document r8a779a0

[Geert Uytterhoeven]

On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Add binding documentation for the R-Car V3U (R8A779A0) Clock Pulse
> Generator.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

> --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
> +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
> @@ -47,6 +47,7 @@ properties:
>        - renesas,r8a77980-cpg-mssr # R-Car V3H
>        - renesas,r8a77990-cpg-mssr # R-Car E3
>        - renesas,r8a77995-cpg-mssr # R-Car D3
> +      - renesas,r8a779a0-cpg-mssr # R-Car V3U
>
>    reg:
>      maxItems: 1
> --
> 2.7.4
>

FIXME check clock-names


--
Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 07/14] dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions

[Geert Uytterhoeven]

Hi Shimoda-san,

Thanks for your patch!

On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
> V3U (R8A779A0) SoC.

So obviously s/61/a0/ in the patch subject ;-)

> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
> @@ -0,0 +1,63 @@
> +/* SPDX-License-Identifier: GPL-2.0 */

GPL-2.0-only?

> +/*
> + * Copyright (C) 2020 Renesas Electronics Corp.
> + */
> +#ifndef __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
> +#define __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* r8a779A0 CPG Core Clocks */
> +#define R8A779A0_CLK_Z0                        0
> +#define R8A779A0_CLK_ZX                        1
> +#define R8A779A0_CLK_Z1                        2
> +#define R8A779A0_CLK_ZR                        3
> +#define R8A779A0_CLK_ZS                        4
> +#define R8A779A0_CLK_ZT                        5
> +#define R8A779A0_CLK_ZTR               6
> +#define R8A779A0_CLK_S1                        7
> +#define R8A779A0_CLK_S3                        8

On other SoCs, we didn't include S1 and S3, as they are internal clocks.

> +#define R8A779A0_CLK_S1D1              9
> +#define R8A779A0_CLK_S1D2              10
> +#define R8A779A0_CLK_S1D4              11
> +#define R8A779A0_CLK_S1D8              12
> +#define R8A779A0_CLK_S1D12             13

No S1D8 nor S1D12 in the table in Section 8.1.4 ("List of Clock Out")?

> +#define R8A779A0_CLK_S2D1              14
> +#define R8A779A0_CLK_S2D2              15
> +#define R8A779A0_CLK_S2D4              16

Given the table has no S2 parent clock, and there are no other
references to any of the S2D* clocks, I wonder if they exist at all?

As this file will become stable DT ABI, it would be good to have a
definitive answer.

> +#define R8A779A0_CLK_S3D1              17
> +#define R8A779A0_CLK_S3D2              18
> +#define R8A779A0_CLK_S3D4              19
> +#define R8A779A0_CLK_LB                        20
> +#define R8A779A0_CLK_CP                        21
> +#define R8A779A0_CLK_CL                        22
> +#define R8A779A0_CLK_CL16MCK           23
> +#define R8A779A0_CLK_ZB30              24
> +#define R8A779A0_CLK_ZB30D2            25
> +#define R8A779A0_CLK_ZB30D4            26
> +#define R8A779A0_CLK_ZB31              27
> +#define R8A779A0_CLK_ZB31D2            28
> +#define R8A779A0_CLK_ZB31D4            29
> +#define R8A779A0_CLK_SD0H              30
> +#define R8A779A0_CLK_SD0               31
> +#define R8A779A0_CLK_RPC               32
> +#define R8A779A0_CLK_RPCD2             33
> +#define R8A779A0_CLK_MSO               34
> +#define R8A779A0_CLK_CANFD             35
> +#define R8A779A0_CLK_CSI0              36
> +#define R8A779A0_CLK_FRAY              37
> +#define R8A779A0_CLK_POST              38
> +#define R8A779A0_CLK_POST2             39
> +#define R8A779A0_CLK_POST3             40

Do we need the POST clocks (BTW, POST4 is missing)?
On other SoCs, we didn't include them.

> +#define R8A779A0_CLK_DSI               41
> +#define R8A779A0_CLK_VIP               42
> +#define R8A779A0_CLK_ADGH              43
> +#define R8A779A0_CLK_CNNDSP            44
> +#define R8A779A0_CLK_ICU               45
> +#define R8A779A0_CLK_ICUD2             46
> +#define R8A779A0_CLK_VCBUS             47
> +#define R8A779A0_CLK_CBFUSA            48
> +#define R8A779A0_CLK_RCLK              49
> +#define R8A779A0_CLK_OSCCLK            50

On other SoCs, we called them <SOC>_CLK_R and <SOC>_CLK_OSC.

> +
> +#endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */

Thanks!

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 07/14] dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions

[Geert Uytterhoeven]

On Tue, Sep 8, 2020 at 11:23 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h

> > +#define R8A779A0_CLK_S1D1              9
> > +#define R8A779A0_CLK_S1D2              10
> > +#define R8A779A0_CLK_S1D4              11
> > +#define R8A779A0_CLK_S1D8              12
> > +#define R8A779A0_CLK_S1D12             13
>
> No S1D8 nor S1D12 in the table in Section 8.1.4 ("List of Clock Out")?

But it is listed as a child of S1...

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 08/14] dt-bindings: serial: renesas,scif: Document r8a779a0 bindings

[Geert Uytterhoeven]

On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> R-Car V3U (R8A779A0) SoC also has the R-Car Gen3 compatible
> SCIF ports, so document the SoC specific bindings.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 09/14] soc: renesas: identify R-Car V3U

[Geert Uytterhoeven]

On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Add support for identifying the R-Car V3U (R8A779A0) SoC.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

> --- a/drivers/soc/renesas/Kconfig
> +++ b/drivers/soc/renesas/Kconfig
> @@ -272,6 +272,12 @@ config ARCH_R8A77995
>         help
>           This enables support for the Renesas R-Car D3 SoC.
>
> +config ARCH_R8A779A0
> +       bool "Renesas R-Car V3U SoC Platform"

Will update while applying to match Morimoto-san's Kconfig rework.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.10.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 10/14] soc: renesas: r8a779a0-sysc: Add r8a779a0 support

[Geert Uytterhoeven]

 nHi Shimoda-san,

On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Add support for R-Car V3U (R8A779A0) SoC power areas and
> register access, because register specification differs
> than R-Car Gen2/3.
>
> Inspired by patches in the BSP by Tho Vu.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/drivers/soc/renesas/r8a779a0-sysc.c
> @@ -0,0 +1,460 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Renesas R-Car V3U System Controller
> + *
> + * Copyright (C) 2020 Renesas Electronics Corp.
> + */
> +
> +#include <linux/bits.h>
> +#include <linux/clk/renesas.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/kernel.h>
> +#include <linux/mm.h>
> +#include <linux/of_address.h>
> +#include <linux/pm_domain.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +#include <linux/io.h>
> +#include <linux/soc/renesas/rcar-sysc.h>
> +#include <linux/sys_soc.h>
> +#include <linux/syscore_ops.h>

The above 3 includes are not needed.

> +
> +#include <dt-bindings/power/r8a779a0-sysc.h>
> +
> +#include "rcar-sysc.h"

You don't reuse the rcar-sysc driver itself, but you do reuse its header
file.  As the comments in rcar-sysc.h refer to registers that have been
renamed (e.g. PWR*), and SYSCEXTMASK no longer exists, it might be
easier for the casual reader to drop the include, copy the PD_*
definitions, and define new r8a779a0_sysc_area and r8a779a0_sysc_info
structures instead, using the new naming.

> +
> +static struct rcar_sysc_area r8a779a0_areas[] __initdata = {
> +       { "always-on",       0, 0, R8A779A0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
> +       { "a3e0",       0x1500, 0, R8A779A0_PD_A3E0, R8A779A0_PD_ALWAYS_ON, PD_SCU },

I think you can drop:
  - chan_offs: it's always 0x1000 + pdr * 64,
  - chan_bit: it's always zero,

> +/* SYSC Common */
> +#define SYSCSR         0x000   /* SYSC Status Register */
> +#define SYSCPONSR(x)   (0x800 + ((x) * 0x4)) /* Power-ON Status Register 0 */
> +#define SYSCPOFFSR(x)  (0x808 + ((x) * 0x4)) /* Power-OFF Status Register */
> +#define SYSCISCR(x)    (0x810 + ((x) * 0x4)) /* Interrupt Status/Clear Register */
> +#define SYSCIER(x)     (0x820 + ((x) * 0x4)) /* Interrupt Enable Register */
> +#define SYSCIMR(x)     (0x830 + ((x) * 0x4)) /* Interrupt Mask Register */
> +
> +/* Power Domain Registers */
> +#define PDRSR(n)       (0x1000 + ((n) * 0x40))
> +#define PDRONCR(n)     (0x1004 + ((n) * 0x40))
> +#define PDROFFCR(n)    (0x1008 + ((n) * 0x40))
> +#define PDRESR(n)      (0x100C + ((n) * 0x40))

While PDRESRn is described, and shown in a figure, it was forgotten in
the Table 9.2 ("List of Registers (Power Domain Registers for each power
domain)").

> +
> +/* Power State */
> +#define PW_ACTIVE      1       /* Active setting */

"/* PWRON/PWROFF */"?

> +
> +/* PDRSR */
> +#define PDRSR_OFF              BIT(0)  /* Power-OFF state */
> +#define PDRSR_ON               BIT(4)  /* Power-ON state */
> +#define PDRSR_OFF_STATE                BIT(8)  /* Processing Power-OFF sequence */
> +#define PDRSR_ON_STATE         BIT(12) /* Processing Power-ON sequence */
> +
> +#define SYSCSR_PONENB          1       /* Ready for power resume requests */
> +#define SYSCSR_POFFENB         0       /* Ready for power shutoff requests */

These two bits are now combined into a single BUSY bit mask:
(doh, all bits sets is not busy?!?)

#define SYSCSR_BUSY    GENMASK(1, 0)    /* All bit sets is not busy */


> +
> +#define SYSCSR_RETRIES         1000
> +#define SYSCSR_DELAY_US                10
> +
> +#define PDRESR_RETRIES         1000
> +#define PDRESR_DELAY_US                10
> +
> +#define SYSCISR_RETRIES                1000
> +#define SYSCISR_DELAY_US       10
> +
> +#define R8A779A0_NUM_PD_ALWAYS_ON      64      /* Always-on power area */

Just use R8A779A0_PD_ALWAYS_ON instead?

> +
> +#define NUM_DOMAINS_EACH_REG   32

BITS_PER_TYPE(u32)?


> +
> +struct rcar_sysc_ch {
> +       u16 chan_offs;
> +       u8 chan_bit;
> +       u8 isr_bit;
> +};

As chan_offs is unused, and chan_bit is always zero, I think all use of
this struct can just be replaced by "unsigned int pdr"?

> +
> +static void __iomem *rcar_sysc_base;

s/rcar/r8a779a0/ everywhere?

> +static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
> +
> +static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on)
> +{
> +       unsigned int sr_bit, reg_offs;

sr_bit is no longer needed.

> +       int k;
> +
> +       if (on) {
> +               sr_bit = SYSCSR_PONENB;
> +               reg_offs = PDRONCR(sysc_ch->isr_bit);
> +       } else {
> +               sr_bit = SYSCSR_POFFENB;
> +               reg_offs = PDROFFCR(sysc_ch->isr_bit);
> +       }
> +
> +       /* Wait until SYSC is ready to accept a power request */
> +       for (k = 0; k < SYSCSR_RETRIES; k++) {
> +               if (ioread32(rcar_sysc_base + SYSCSR) & BIT(sr_bit))

    if ((ioread32(rcar_sysc_base + SYSCSR) & SYSCSR_BUSY) == SYSCSR_BUSY)

> +                       break;
> +               udelay(SYSCSR_DELAY_US);
> +       }

Perhaps you can use readl_poll_timeout()?

> +
> +       if (k == SYSCSR_RETRIES)
> +               return -EAGAIN;
> +
> +       /* Submit power shutoff or power resume request */
> +       iowrite32(PW_ACTIVE, rcar_sysc_base + reg_offs);
> +
> +       return 0;
> +}
> +
> +static int clear_irq_flags(unsigned int reg_idx, unsigned int isr_mask)
> +{
> +       int k = 0;
> +
> +       iowrite32(isr_mask, rcar_sysc_base + SYSCISCR(reg_idx));
> +
> +       for (k = 0; k < SYSCISR_RETRIES; k++) {
> +               if ((ioread32(rcar_sysc_base + SYSCISCR(reg_idx)) & isr_mask) == 0)
> +                       break;
> +
> +               udelay(SYSCISR_DELAY_US);
> +       }

readl_poll_timeout()?

> +
> +       if (k == SYSCISR_RETRIES) {
> +               pr_err("\n %s : Can not clear IRQ flags in SYSCISCR", __func__);
> +               return -EIO;
> +       }
> +
> +       return 0;
> +}

> +static bool has_cpg_mstp;

Please drop this and all related code, R-Car V3U does not use the legacy
CPG/MSSR PM Domain.

> +static const struct of_device_id rcar_sysc_matches[] __initconst = {
> +#ifdef CONFIG_SYSC_R8A779A0

Please drop the #ifdef, as compilation of this file already depends on
this symbol.

> +       { .compatible = "renesas,r8a779a0-sysc", .data = &r8a779a0_sysc_info },
> +#endif
> +       { /* sentinel */ }
> +};

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 11/14] soc: renesas: rcar-rst: Add support for R-Car V3U

[Geert Uytterhoeven]

Hi Shimoda-san,

On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Add support for R-Car V3U (R8A779A0) to the R-Car RST driver.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Thanks for your patch!

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

> --- a/drivers/soc/renesas/rcar-rst.c
> +++ b/drivers/soc/renesas/rcar-rst.c
> @@ -37,6 +37,10 @@ static const struct rst_config rcar_rst_gen3 __initconst = {
>         .modemr = 0x60,
>  };
>
> +static const struct rst_config rcar_rst_r8a779a0 __initconst = {
> +       .modemr = 0x00,         /* MODEMR0 and it has CPG related bits */

Do you need the bits from MODEMR1, too?
Perhaps the time is ripe to add rcar_rst_read_mode_pins64(),
so users can access more than 32 bits on SoCs that provide it (R-Car
V3H and V3U)?

At least the numbering is sane on R-Car V3U. On R-Car V3H, MD29 and
higher are stored starting at bit 1 of the second MODEMR register...

> +};


Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 12/14] clk: renesas: cpg-mssr: Add support for R-Car V3U

[Geert Uytterhoeven]

Hi Shimoda-san,

Thanks for your patch!

On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Initial support for R-Car V3U (r8a779a0), including core, module
> clocks and register access, because register specification differs
> than R-Car Gen2/3.

differs from

> Inspired by patches in the BSP by LUU HOAI.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

> --- a/drivers/clk/renesas/Kconfig
> +++ b/drivers/clk/renesas/Kconfig
> @@ -30,6 +30,7 @@ config CLK_RENESAS
>         select CLK_R8A77980 if ARCH_R8A77980
>         select CLK_R8A77990 if ARCH_R8A77990
>         select CLK_R8A77995 if ARCH_R8A77995
> +       select CLK_R8A779A0 if ARCH_R8A779A0
>         select CLK_R9A06G032 if ARCH_R9A06G032
>         select CLK_SH73A0 if ARCH_SH73A0
>
> @@ -145,6 +146,9 @@ config CLK_R8A77995
>         bool "R-Car D3 clock support" if COMPILE_TEST
>         select CLK_RCAR_GEN3_CPG
>
> +config CLK_R8A779A0
> +       bool "R-Car V3U clock support" if COMPILE_TEST

Missing "select CLK_RENESAS_CPG_MSSR"

> +
>  config CLK_R9A06G032
>         bool "Renesas R9A06G032 clock driver"
>         help

> --- /dev/null
> +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
> @@ -0,0 +1,479 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * r8a779a0 Clock Pulse Generator / Module Standby and Software Reset
> + *
> + * Copyright (C) 2020 Renesas Electronics Corp.
> + *
> + * Based on r8a7795-cpg-mssr.c
> + *
> + * Copyright (C) 2015 Glider bvba
> + * Copyright (C) 2015 Renesas Electronics Corp.
> + */
> +
> +#include <linux/bug.h>
> +#include <linux/bitfield.h>
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/pm.h>
> +#include <linux/slab.h>
> +#include <linux/soc/renesas/rcar-rst.h>
> +#include <linux/sys_soc.h>

This include is not needed.

> +
> +#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
> +
> +#include "renesas-cpg-mssr.h"
> +
> +enum rcar_r8a779a0_clk_types {
> +       CLK_TYPE_R8A779A0_MAIN = CLK_TYPE_CUSTOM,
> +       CLK_TYPE_R8A779A0_PLL1,
> +       CLK_TYPE_R8A779A0_PLL20,
> +       CLK_TYPE_R8A779A0_PLL21,
> +       CLK_TYPE_R8A779A0_PLL30,
> +       CLK_TYPE_R8A779A0_PLL31,
> +       CLK_TYPE_R8A779A0_PLL5,
> +       CLK_TYPE_R8A779A0_MDSEL,        /* Select parent/divider using mode pin */
> +       CLK_TYPE_R8A779A0_Z,
> +       CLK_TYPE_R8A779A0_OSC,  /* OSC EXTAL predivider and fixed divider */
> +
> +       /* SoC specific definitions start here */
> +       CLK_TYPE_R8A779A0_SOC_BASE,

This last definition is not needed.

> +};
> +
> +#define DEF_R8A779A0_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
> +       DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL,   \
> +                (_parent0) << 16 | (_parent1),         \
> +                .div = (_div0) << 16 | (_div1), .offset = _md)
> +
> +#define DEF_R8A779A0_OSC(_name, _id, _parent, _div)            \
> +       DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_OSC, _parent, .div = _div)

Perhaps you can just include "rcar-gen3-cpg.h", so you can use the
DEF_GEN3_MDSEL() and DEF_GEN3_OSC() definitions now (and probably
DEF_GEN3_SD later)?


> +
> +struct rcar_r8a779a0_cpg_pll_config {
> +       u8 extal_div;
> +       u8 pll1_mult;
> +       u8 pll1_div;
> +       u8 pll5_mult;
> +       u8 pll5_div;
> +       u8 osc_prediv;
> +};
> +
> +enum clk_ids {
> +       /* Core Clock Outputs exported to DT */
> +       LAST_DT_CORE_CLK = R8A779A0_CLK_OSCCLK,
> +
> +       /* External Input Clocks */
> +       CLK_EXTAL,
> +       CLK_EXTALR,
> +
> +       /* Internal Core Clocks */
> +       CLK_MAIN,
> +       CLK_PLL1,
> +       CLK_PLL20,
> +       CLK_PLL21,
> +       CLK_PLL30,
> +       CLK_PLL31,
> +       CLK_PLL5,
> +       CLK_PLL1_DIV2,
> +       CLK_PLL20_DIV2,
> +       CLK_PLL21_DIV2,
> +       CLK_PLL30_DIV2,
> +       CLK_PLL31_DIV2,
> +       CLK_PLL5_DIV2,
> +       CLK_PLL5_DIV4,
> +       CLK_S1,
> +       CLK_S2,
> +       CLK_S3,
> +       CLK_SDSRC,
> +       CLK_RPCSRC,
> +       CLK_OCO,
> +
> +       /* Module Clocks */
> +       MOD_CLK_BASE
> +};
> +
> +static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
> +       /* External Clock Inputs */
> +       DEF_INPUT("extal",  CLK_EXTAL),
> +       DEF_INPUT("extalr", CLK_EXTALR),
> +
> +       /* Internal Core Clocks */
> +       DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL),
> +       DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN),
> +       DEF_BASE(".pll20",      CLK_PLL20, CLK_TYPE_R8A779A0_PLL20, CLK_MAIN),
> +       DEF_BASE(".pll21",      CLK_PLL21, CLK_TYPE_R8A779A0_PLL21, CLK_MAIN),
> +       DEF_BASE(".pll30",      CLK_PLL30, CLK_TYPE_R8A779A0_PLL30, CLK_MAIN),
> +       DEF_BASE(".pll31",      CLK_PLL31, CLK_TYPE_R8A779A0_PLL31, CLK_MAIN),
> +       DEF_BASE(".pll5",       CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN),
> +
> +       DEF_FIXED(".pll1_div2",  CLK_PLL1_DIV2,    CLK_PLL1,   2, 1),
> +       DEF_FIXED(".pll20_div2", CLK_PLL20_DIV2,   CLK_PLL20,  2, 1),
> +       DEF_FIXED(".pll21_div2", CLK_PLL21_DIV2,   CLK_PLL21,  2, 1),
> +       DEF_FIXED(".pll30_div2", CLK_PLL30_DIV2,   CLK_PLL30,  2, 1),
> +       DEF_FIXED(".pll31_div2", CLK_PLL31_DIV2,   CLK_PLL31,  2, 1),
> +       DEF_FIXED(".pll5_div2",  CLK_PLL5_DIV2,    CLK_PLL5,   2, 1),

Please align the values in the last column.

> +       DEF_FIXED(".pll5_div4",  CLK_PLL5_DIV4,    CLK_PLL5_DIV2,   2, 1),
> +       DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,   2, 1),
> +       DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,   133, 50),

div = 8, mul = 3 sounds more likely.
Or perhaps S2 is derived from PLL5, which runs at a multiple of 400 MHz?
Or perhaps S2 does not exist...

> +       DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,   4, 1),
> +       DEF_RATE(".oco",        CLK_OCO,           32768),
> +
> +       /* Core Clock Outputs */
> +       DEF_FIXED("zx",         R8A779A0_CLK_ZX,     CLK_PLL20_DIV2,  2, 1),
> +       DEF_FIXED("s1d1",       R8A779A0_CLK_S1D1,   CLK_S1, 1, 1),
> +       DEF_FIXED("s1d2",       R8A779A0_CLK_S1D2,   CLK_S1, 2, 1),
> +       DEF_FIXED("s1d4",       R8A779A0_CLK_S1D4,   CLK_S1, 4, 1),
> +       DEF_FIXED("s1d8",       R8A779A0_CLK_S1D8,   CLK_S1, 8, 1),
> +       DEF_FIXED("s1d12",      R8A779A0_CLK_S1D12,  CLK_S1, 12, 1),
> +       DEF_FIXED("s2d1",       R8A779A0_CLK_S2D1,   CLK_S2, 1, 1),
> +       DEF_FIXED("s2d2",       R8A779A0_CLK_S2D2,   CLK_S2, 2, 1),
> +       DEF_FIXED("s2d4",       R8A779A0_CLK_S2D4,   CLK_S2, 4, 1),
> +       DEF_FIXED("s3d1",       R8A779A0_CLK_S3D1,   CLK_S3, 1, 1),
> +       DEF_FIXED("s3d2",       R8A779A0_CLK_S3D2,   CLK_S3, 2, 1),
> +       DEF_FIXED("s3d4",       R8A779A0_CLK_S3D4,   CLK_S3, 4, 1),

Please align the values in the last column.

> +       DEF_FIXED("zs",         R8A779A0_CLK_ZS,     CLK_PLL1_DIV2,   4, 1),
> +       DEF_FIXED("zt",         R8A779A0_CLK_ZT,     CLK_PLL1_DIV2,   2, 1),
> +       DEF_FIXED("ztr",        R8A779A0_CLK_ZTR,    CLK_PLL1_DIV2,   2, 1),
> +       DEF_FIXED("zr",         R8A779A0_CLK_ZR,     CLK_PLL1_DIV2,   1, 1),

ZR = PLL6 / 4.
Is PLL6 the same as PLL1, they always run at the same rate?
There don't seem to be any registers documented to control PLL6VCO.

> +       DEF_FIXED("dsi",        R8A779A0_CLK_DSI,    CLK_PLL5_DIV4,   1, 1),
> +       DEF_FIXED("cnndsp",     R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4,   1, 1),
> +       DEF_FIXED("vip",        R8A779A0_CLK_VIP,    CLK_PLL5,        5, 1),
> +       DEF_FIXED("adgh",       R8A779A0_CLK_ADGH,   CLK_PLL5_DIV4,   1, 1),
> +       DEF_FIXED("icu",        R8A779A0_CLK_ICU,    CLK_PLL5_DIV4,   2, 1),
> +       DEF_FIXED("icud2",      R8A779A0_CLK_ICUD2,  CLK_PLL5_DIV4,   4, 1),
> +       DEF_FIXED("vcbus",      R8A779A0_CLK_VCBUS,  CLK_PLL5_DIV4,   1, 1),
> +
> +       DEF_FIXED("cbfusa",     R8A779A0_CLK_CBFUSA, CLK_MAIN,   2, 1),
> +
> +       DEF_DIV6P1("mso",       R8A779A0_CLK_MSO,    CLK_PLL5_DIV4, 0x87c),
> +       DEF_DIV6P1("canfd",     R8A779A0_CLK_CANFD,  CLK_PLL5_DIV4, 0x878),
> +       DEF_DIV6P1("csi0",      R8A779A0_CLK_CSI0,   CLK_PLL5_DIV4, 0x880),
> +       DEF_DIV6P1("fray",      R8A779A0_CLK_FRAY,   CLK_PLL5_DIV4, 0x88c),

The FRAY register doesn't seem to be documented?

> +       DEF_DIV6P1("post",      R8A779A0_CLK_POST,   CLK_PLL5_DIV4, 0x890),
> +       DEF_DIV6P1("post2",     R8A779A0_CLK_POST2,  CLK_PLL5_DIV4, 0x894),
> +       DEF_DIV6P1("post3",     R8A779A0_CLK_POST3,  CLK_PLL5_DIV4, 0x898),
> +
> +       DEF_R8A779A0_OSC("osc", R8A779A0_CLK_OSCCLK, CLK_EXTAL,     8),
> +       DEF_R8A779A0_MDSEL("r", R8A779A0_CLK_RCLK, 29, CLK_EXTALR, 1, CLK_OCO, 1),
> +};
> +
> +static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
> +       DEF_MOD("scif0",        702,    R8A779A0_CLK_S1D8),
> +       DEF_MOD("scif1",        703,    R8A779A0_CLK_S1D8),
> +       DEF_MOD("scif3",        704,    R8A779A0_CLK_S1D8),
> +       DEF_MOD("scif4",        705,    R8A779A0_CLK_S1D8),
> +};
> +
> +static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {
> +       MOD_CLK_ID(408),        /* INTC-AP (GIC) */

There's no entry for this clock in r8a779a0_mod_clks[] above, so please
drop this.
Also, the INTC-AP clock is not documented, unfortunately.

> +};
> +
> +#define CPG_PLL20CR            0x0834
> +#define CPG_PLL21CR            0x0838
> +#define CPG_PLL30CR            0x083c
> +#define CPG_PLL31CR            0x0840
> +
> +static spinlock_t cpg_lock;
> +
> +static void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set)
> +{
> +       unsigned long flags;
> +       u32 val;
> +
> +       spin_lock_irqsave(&cpg_lock, flags);
> +       val = readl(reg);
> +       val &= ~clear;
> +       val |= set;
> +       writel(val, reg);
> +       spin_unlock_irqrestore(&cpg_lock, flags);
> +};
> +
> +/*
> + * Z Clock & Z2 Clock

All the Z clock code is currently unused.

> +struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
> +       const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
> +       struct clk **clks, void __iomem *base,
> +       struct raw_notifier_head *notifiers)
> +{

> +       case CLK_TYPE_R8A779A0_PLL20:
> +               value = readl(base + CPG_PLL20CR);
> +               mult = (((value >> 24) & 0x7f) + 1) * 2;
> +               break;
> +
> +       case CLK_TYPE_R8A779A0_PLL21:
> +               value = readl(base + CPG_PLL21CR);
> +               mult = (((value >> 24) & 0x7f) + 1) * 2;
> +               break;
> +
> +       case CLK_TYPE_R8A779A0_PLL30:
> +               value = readl(base + CPG_PLL30CR);
> +               mult = (((value >> 24) & 0x7f) + 1) * 2;
> +               break;
> +
> +       case CLK_TYPE_R8A779A0_PLL31:
> +               value = readl(base + CPG_PLL31CR);
> +               mult = (((value >> 24) & 0x7f) + 1) * 2;
> +               break;

Perhaps CLK_TYPE_R8A779A0_PLL[23][01] can share a common type, encoding
the register offset in cpg_core_clk.offset?

> +const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = {
> +       /* Core Clocks */
> +       .core_clks = r8a779a0_core_clks,
> +       .num_core_clks = ARRAY_SIZE(r8a779a0_core_clks),
> +       .last_dt_core_clk = LAST_DT_CORE_CLK,
> +       .num_total_core_clks = MOD_CLK_BASE,
> +
> +       /* Module Clocks */
> +       .mod_clks = r8a779a0_mod_clks,
> +       .num_mod_clks = ARRAY_SIZE(r8a779a0_mod_clks),
> +       .num_hw_mod_clks = 12 * 32,

15 * 32

> +
> +       /* Critical Module Clocks */
> +       .crit_mod_clks = r8a779a0_crit_mod_clks,
> +       .num_crit_mod_clks = ARRAY_SIZE(r8a779a0_crit_mod_clks),
> +
> +       /* Callbacks */
> +       .init = r8a779a0_cpg_mssr_init,
> +       .cpg_clk_register = rcar_r8a779a0_cpg_clk_register,
> +
> +       /* The device has only MSTP Control Register */
> +       .mstpctrl = true,
> +};
> diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
> index 5a306d2..c259e05 100644
> --- a/drivers/clk/renesas/renesas-cpg-mssr.c
> +++ b/drivers/clk/renesas/renesas-cpg-mssr.c
> @@ -57,8 +57,14 @@ static const u16 mstpsr[] = {
>         0x9A0, 0x9A4, 0x9A8, 0x9AC,
>  };
>
> -#define        MSTPSR(i)       mstpsr[i]
> +static const u16 mstpsr_mstpcr_only[] = {
> +       0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
> +       0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38,
> +};
> +
> +static bool mstpcr_only;
>
> +#define        MSTPSR(i)       (mstpcr_only ? mstpsr_mstpcr_only[i] : mstpsr[i])

IMHO, ugly macro handling...

>
>  /*
>   * System Module Stop Control Register offsets
> @@ -69,7 +75,8 @@ static const u16 smstpcr[] = {
>         0x990, 0x994, 0x998, 0x99C,
>  };
>
> -#define        SMSTPCR(i)      smstpcr[i]
> +#define        SMSTPCR(i)      (mstpcr_only ? (mstpsr_mstpcr_only[i] - 0x100) : \
> +                        smstpcr[i])

.. more ugly macro handling.
Still, it doesn't handle the Software Reset and Clearing registers.

> @@ -140,7 +147,7 @@ struct cpg_mssr_priv {
>         struct {
>                 u32 mask;
>                 u32 val;
> -       } smstpcr_saved[ARRAY_SIZE(smstpcr)];
> +       } smstpcr_saved[ARRAY_SIZE(mstpsr_mstpcr_only)];

Basically the maximum number of registers to save.

> @@ -938,6 +951,7 @@ static int __init cpg_mssr_common_init(struct device *dev,
>         priv->last_dt_core_clk = info->last_dt_core_clk;
>         RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
>         priv->stbyctrl = info->stbyctrl;
> +       mstpcr_only = info->mstpctrl;
>
>         for (i = 0; i < nclks; i++)
>                 priv->clks[i] = ERR_PTR(-ENOENT);
> diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
> index 1cc5694..061eb83 100644
> --- a/drivers/clk/renesas/renesas-cpg-mssr.h
> +++ b/drivers/clk/renesas/renesas-cpg-mssr.h
> @@ -131,6 +131,7 @@ struct cpg_mssr_info {
>         unsigned int last_dt_core_clk;
>         unsigned int num_total_core_clks;
>         bool stbyctrl;
> +       bool mstpctrl;

Personally, I don't like adding a second boolean flag, to be checked in
multiple places, hidden inside macros.

I think this can be handled better by defining multiple registers layout
variants using an enum, for
  1. R-Car Gen2/3-style register layouts,
  2. RZ/A-style register layouts,
  3. R-Car V3U-style register layout.
Then register tables pointers can be set up based on the enum value, and
code can check the enum value where needed.

Note that layout 1 can also be used for SH/R-Mobile, and we could easily
add a 4th layout for R-Car Gen1, if we ever migrate SH/R-Mobile and/or
R-Car Gen1 to CPG/MSSR.

What do you think?

>
>         /* Module Clocks */
>         const struct mssr_mod_clk *mod_clks;

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 13/14] arm64: dts: renesas: Add Renesas R8A779A0 SoC support

[Geert Uytterhoeven]

Hi Shimoda-san,

On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Add initial support for the Renesas R8A77990 (R-Car V3U) support.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi

> +       soc: soc {

> +
> +               sysc: system-controller@e6180000 {
> +                       compatible = "renesas,r8a779a0-sysc";
> +                       reg = <0 0xe6180000 0 0x3078>;

Length 0x4000?

> +                       #power-domain-cells = <1>;
> +               };
> +
> +               scif0: serial@e6e60000 {
> +                       compatible = "renesas,scif-r8a779a0",
> +                                    "renesas,rcar-gen3-scif", "renesas,scif";
> +                       reg = <0 0xe6e60000 0 64>;
> +                       interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&cpg CPG_MOD 702>,
> +                                <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
> +                                <&scif_clk>;
> +                       clock-names = "fck", "brg_int", "scif_clk";
> +                       power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

Missing resets property.

> +                       status = "disabled";
> +               };
> +
> +               gic: interrupt-controller@f1000000 {
> +                       compatible = "arm,gic-v3";
> +                       #interrupt-cells = <3>;
> +                       #address-cells = <0>;
> +                       interrupt-controller;
> +                       reg = <0x0 0xf1000000 0 0x20000>,
> +                             <0x0 0xf1060000 0 0x110000>;
> +                       interrupts = <GIC_PPI 9
> +                                     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;

"GIC_CPU_MASK_SIMPLE(1)", as currently only one CPU core is used.

> +                       power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
> +               };
> +
> +               prr: chipid@fff00044 {
> +                       compatible = "renesas,prr";
> +                       reg = <0 0xfff00044 0 4>;
> +               };
> +       };
> +
> +       timer {
> +               compatible = "arm,armv8-timer";
> +               interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +                                     <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +                                     <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +                                     <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;

"GIC_CPU_MASK_SIMPLE(1)" for all 4 interrupts (and in the future "8",
not "2").

> +       };
> +};
> --
> 2.7.4
>



--
Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 06/14] dt-bindings: clock: renesas,cpg-mssr: Document r8a779a0

[Geert Uytterhoeven]

On Tue, Sep 8, 2020 at 11:23 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > Add binding documentation for the R-Car V3U (R8A779A0) Clock Pulse
> > Generator.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> > --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
> > +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
> > @@ -47,6 +47,7 @@ properties:
> >        - renesas,r8a77980-cpg-mssr # R-Car V3H
> >        - renesas,r8a77990-cpg-mssr # R-Car E3
> >        - renesas,r8a77995-cpg-mssr # R-Car D3
> > +      - renesas,r8a779a0-cpg-mssr # R-Car V3U
> >
> >    reg:
> >      maxItems: 1
> > --
> > 2.7.4
> >
>
> FIXME check clock-names

Please ignore the FIXME (checked).

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 14/14] arm64: dts: renesas: Add Renesas Falcon boards support

[Geert Uytterhoeven]

Hi Shimoda-san,

On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Initial support for the Renesas Falcon CPU and BreakOut boards
> support.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/falcon-cpu.dtsi
> @@ -0,0 +1,44 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the Falcon CPU board
> + *
> + * Copyright (C) 2020 Renesas Electronics Corp.
> + */

As this board contains the CPU, I had expected

    #include "r8a779a0.dtsi"

here.

> +
> +/ {
> +       model = "Renesas Falcon CPU board";
> +       compatible = "renesas,falcon-cpu";

+ renesas,r8a779a0.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 07/14] dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions

[Yoshihiro Shimoda]

Hi Geert-san,

Thank you for your review!

> From: Geert Uytterhoeven, Sent: Tuesday, September 8, 2020 6:24 PM
> 
> Hi Shimoda-san,
> 
> Thanks for your patch!
> 
> On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
> > V3U (R8A779A0) SoC.
> 
> So obviously s/61/a0/ in the patch subject ;-)

Oops. You're correct :)

> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> 
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
> > @@ -0,0 +1,63 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> 
> GPL-2.0-only?

I'll fix it.

> > +/*
> > + * Copyright (C) 2020 Renesas Electronics Corp.
> > + */
> > +#ifndef __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
> > +#define __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
> > +
> > +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> > +
> > +/* r8a779A0 CPG Core Clocks */
> > +#define R8A779A0_CLK_Z0                        0
> > +#define R8A779A0_CLK_ZX                        1
> > +#define R8A779A0_CLK_Z1                        2
> > +#define R8A779A0_CLK_ZR                        3
> > +#define R8A779A0_CLK_ZS                        4
> > +#define R8A779A0_CLK_ZT                        5
> > +#define R8A779A0_CLK_ZTR               6
> > +#define R8A779A0_CLK_S1                        7
> > +#define R8A779A0_CLK_S3                        8
> 
> On other SoCs, we didn't include S1 and S3, as they are internal clocks.

I got it. I'll drop S1 and S3.

> > +#define R8A779A0_CLK_S1D1              9
> > +#define R8A779A0_CLK_S1D2              10
> > +#define R8A779A0_CLK_S1D4              11
> > +#define R8A779A0_CLK_S1D8              12
> > +#define R8A779A0_CLK_S1D12             13
> 
> No S1D8 nor S1D12 in the table in Section 8.1.4 ("List of Clock Out")?

As you mentioned other email thread, it is listed as a child of S1.
And, I checked an internal material and then S1D8 and S1D12 exist.

> > +#define R8A779A0_CLK_S2D1              14
> > +#define R8A779A0_CLK_S2D2              15
> > +#define R8A779A0_CLK_S2D4              16
> 
> Given the table has no S2 parent clock, and there are no other
> references to any of the S2D* clocks, I wonder if they exist at all?

I also checked the material, and then, V3U doesn't have any S2*.
So, I'll drop these S2*.

> As this file will become stable DT ABI, it would be good to have a
> definitive answer.

I got it.

> > +#define R8A779A0_CLK_S3D1              17
> > +#define R8A779A0_CLK_S3D2              18
> > +#define R8A779A0_CLK_S3D4              19
> > +#define R8A779A0_CLK_LB                        20
> > +#define R8A779A0_CLK_CP                        21
> > +#define R8A779A0_CLK_CL                        22
> > +#define R8A779A0_CLK_CL16MCK           23
> > +#define R8A779A0_CLK_ZB30              24
> > +#define R8A779A0_CLK_ZB30D2            25
> > +#define R8A779A0_CLK_ZB30D4            26
> > +#define R8A779A0_CLK_ZB31              27
> > +#define R8A779A0_CLK_ZB31D2            28
> > +#define R8A779A0_CLK_ZB31D4            29
> > +#define R8A779A0_CLK_SD0H              30
> > +#define R8A779A0_CLK_SD0               31
> > +#define R8A779A0_CLK_RPC               32
> > +#define R8A779A0_CLK_RPCD2             33
> > +#define R8A779A0_CLK_MSO               34
> > +#define R8A779A0_CLK_CANFD             35
> > +#define R8A779A0_CLK_CSI0              36
> > +#define R8A779A0_CLK_FRAY              37
> > +#define R8A779A0_CLK_POST              38
> > +#define R8A779A0_CLK_POST2             39
> > +#define R8A779A0_CLK_POST3             40
> 
> Do we need the POST clocks (BTW, POST4 is missing)?
> On other SoCs, we didn't include them.

I see. So, I'll drop POST*.

> > +#define R8A779A0_CLK_DSI               41
> > +#define R8A779A0_CLK_VIP               42
> > +#define R8A779A0_CLK_ADGH              43
> > +#define R8A779A0_CLK_CNNDSP            44
> > +#define R8A779A0_CLK_ICU               45
> > +#define R8A779A0_CLK_ICUD2             46
> > +#define R8A779A0_CLK_VCBUS             47
> > +#define R8A779A0_CLK_CBFUSA            48
> > +#define R8A779A0_CLK_RCLK              49
> > +#define R8A779A0_CLK_OSCCLK            50
> 
> On other SoCs, we called them <SOC>_CLK_R and <SOC>_CLK_OSC.

I'll fix these definitions.

Best regards,
Yoshihiro Shimoda

RE: [PATCH 12/14] clk: renesas: cpg-mssr: Add support for R-Car V3U

[Yoshihiro Shimoda]

Hi Geert-san,

Thank you for your review!

> From: Geert Uytterhoeven, Sent: Wednesday, September 9, 2020 12:22 AM
> 
> Hi Shimoda-san,
> 
> Thanks for your patch!
> 
> On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > Initial support for R-Car V3U (r8a779a0), including core, module
> > clocks and register access, because register specification differs
> > than R-Car Gen2/3.
> 
> differs from

Oops. I'll fix it.

> > Inspired by patches in the BSP by LUU HOAI.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> 
> > --- a/drivers/clk/renesas/Kconfig
> > +++ b/drivers/clk/renesas/Kconfig
> > @@ -30,6 +30,7 @@ config CLK_RENESAS
> >         select CLK_R8A77980 if ARCH_R8A77980
> >         select CLK_R8A77990 if ARCH_R8A77990
> >         select CLK_R8A77995 if ARCH_R8A77995
> > +       select CLK_R8A779A0 if ARCH_R8A779A0
> >         select CLK_R9A06G032 if ARCH_R9A06G032
> >         select CLK_SH73A0 if ARCH_SH73A0
> >
> > @@ -145,6 +146,9 @@ config CLK_R8A77995
> >         bool "R-Car D3 clock support" if COMPILE_TEST
> >         select CLK_RCAR_GEN3_CPG
> >
> > +config CLK_R8A779A0
> > +       bool "R-Car V3U clock support" if COMPILE_TEST
> 
> Missing "select CLK_RENESAS_CPG_MSSR"

I got it. I'll add this.

> > +
> >  config CLK_R9A06G032
> >         bool "Renesas R9A06G032 clock driver"
> >         help
> 
> > --- /dev/null
> > +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
> > @@ -0,0 +1,479 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * r8a779a0 Clock Pulse Generator / Module Standby and Software Reset
> > + *
> > + * Copyright (C) 2020 Renesas Electronics Corp.
> > + *
> > + * Based on r8a7795-cpg-mssr.c
> > + *
> > + * Copyright (C) 2015 Glider bvba
> > + * Copyright (C) 2015 Renesas Electronics Corp.
> > + */
> > +
> > +#include <linux/bug.h>
> > +#include <linux/bitfield.h>
> > +#include <linux/clk.h>
> > +#include <linux/clk-provider.h>
> > +#include <linux/device.h>
> > +#include <linux/err.h>
> > +#include <linux/init.h>
> > +#include <linux/io.h>
> > +#include <linux/kernel.h>
> > +#include <linux/pm.h>
> > +#include <linux/slab.h>
> > +#include <linux/soc/renesas/rcar-rst.h>
> > +#include <linux/sys_soc.h>
> 
> This include is not needed.

I got it.

> > +
> > +#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
> > +
> > +#include "renesas-cpg-mssr.h"
> > +
> > +enum rcar_r8a779a0_clk_types {
> > +       CLK_TYPE_R8A779A0_MAIN = CLK_TYPE_CUSTOM,
> > +       CLK_TYPE_R8A779A0_PLL1,
> > +       CLK_TYPE_R8A779A0_PLL20,
> > +       CLK_TYPE_R8A779A0_PLL21,
> > +       CLK_TYPE_R8A779A0_PLL30,
> > +       CLK_TYPE_R8A779A0_PLL31,
> > +       CLK_TYPE_R8A779A0_PLL5,
> > +       CLK_TYPE_R8A779A0_MDSEL,        /* Select parent/divider using mode pin */
> > +       CLK_TYPE_R8A779A0_Z,
> > +       CLK_TYPE_R8A779A0_OSC,  /* OSC EXTAL predivider and fixed divider */
> > +
> > +       /* SoC specific definitions start here */
> > +       CLK_TYPE_R8A779A0_SOC_BASE,
> 
> This last definition is not needed.

I got it.

> > +};
> > +
> > +#define DEF_R8A779A0_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
> > +       DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL,   \
> > +                (_parent0) << 16 | (_parent1),         \
> > +                .div = (_div0) << 16 | (_div1), .offset = _md)
> > +
> > +#define DEF_R8A779A0_OSC(_name, _id, _parent, _div)            \
> > +       DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_OSC, _parent, .div = _div)
> 
> Perhaps you can just include "rcar-gen3-cpg.h", so you can use the
> DEF_GEN3_MDSEL() and DEF_GEN3_OSC() definitions now (and probably
> DEF_GEN3_SD later)?

I think so. I'll include "rcar-gen3-cpg.h".

> > +
> > +struct rcar_r8a779a0_cpg_pll_config {
> > +       u8 extal_div;
> > +       u8 pll1_mult;
> > +       u8 pll1_div;
> > +       u8 pll5_mult;
> > +       u8 pll5_div;
> > +       u8 osc_prediv;
> > +};
> > +
> > +enum clk_ids {
> > +       /* Core Clock Outputs exported to DT */
> > +       LAST_DT_CORE_CLK = R8A779A0_CLK_OSCCLK,
> > +
> > +       /* External Input Clocks */
> > +       CLK_EXTAL,
> > +       CLK_EXTALR,
> > +
> > +       /* Internal Core Clocks */
> > +       CLK_MAIN,
> > +       CLK_PLL1,
> > +       CLK_PLL20,
> > +       CLK_PLL21,
> > +       CLK_PLL30,
> > +       CLK_PLL31,
> > +       CLK_PLL5,
> > +       CLK_PLL1_DIV2,
> > +       CLK_PLL20_DIV2,
> > +       CLK_PLL21_DIV2,
> > +       CLK_PLL30_DIV2,
> > +       CLK_PLL31_DIV2,
> > +       CLK_PLL5_DIV2,
> > +       CLK_PLL5_DIV4,
> > +       CLK_S1,
> > +       CLK_S2,
> > +       CLK_S3,
> > +       CLK_SDSRC,
> > +       CLK_RPCSRC,
> > +       CLK_OCO,
> > +
> > +       /* Module Clocks */
> > +       MOD_CLK_BASE
> > +};
> > +
> > +static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
> > +       /* External Clock Inputs */
> > +       DEF_INPUT("extal",  CLK_EXTAL),
> > +       DEF_INPUT("extalr", CLK_EXTALR),
> > +
> > +       /* Internal Core Clocks */
> > +       DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL),
> > +       DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN),
> > +       DEF_BASE(".pll20",      CLK_PLL20, CLK_TYPE_R8A779A0_PLL20, CLK_MAIN),
> > +       DEF_BASE(".pll21",      CLK_PLL21, CLK_TYPE_R8A779A0_PLL21, CLK_MAIN),
> > +       DEF_BASE(".pll30",      CLK_PLL30, CLK_TYPE_R8A779A0_PLL30, CLK_MAIN),
> > +       DEF_BASE(".pll31",      CLK_PLL31, CLK_TYPE_R8A779A0_PLL31, CLK_MAIN),
> > +       DEF_BASE(".pll5",       CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN),
> > +
> > +       DEF_FIXED(".pll1_div2",  CLK_PLL1_DIV2,    CLK_PLL1,   2, 1),
> > +       DEF_FIXED(".pll20_div2", CLK_PLL20_DIV2,   CLK_PLL20,  2, 1),
> > +       DEF_FIXED(".pll21_div2", CLK_PLL21_DIV2,   CLK_PLL21,  2, 1),
> > +       DEF_FIXED(".pll30_div2", CLK_PLL30_DIV2,   CLK_PLL30,  2, 1),
> > +       DEF_FIXED(".pll31_div2", CLK_PLL31_DIV2,   CLK_PLL31,  2, 1),
> > +       DEF_FIXED(".pll5_div2",  CLK_PLL5_DIV2,    CLK_PLL5,   2, 1),
> 
> Please align the values in the last column.

I got it.

> > +       DEF_FIXED(".pll5_div4",  CLK_PLL5_DIV4,    CLK_PLL5_DIV2,   2, 1),
> > +       DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,   2, 1),
> > +       DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,   133, 50),
> 
> div = 8, mul = 3 sounds more likely.
> Or perhaps S2 is derived from PLL5, which runs at a multiple of 400 MHz?
> Or perhaps S2 does not exist...

As I mentioned patch 7/14, S2 doesn't exist...

> > +       DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,   4, 1),
> > +       DEF_RATE(".oco",        CLK_OCO,           32768),
> > +
> > +       /* Core Clock Outputs */
> > +       DEF_FIXED("zx",         R8A779A0_CLK_ZX,     CLK_PLL20_DIV2,  2, 1),
> > +       DEF_FIXED("s1d1",       R8A779A0_CLK_S1D1,   CLK_S1, 1, 1),
> > +       DEF_FIXED("s1d2",       R8A779A0_CLK_S1D2,   CLK_S1, 2, 1),
> > +       DEF_FIXED("s1d4",       R8A779A0_CLK_S1D4,   CLK_S1, 4, 1),
> > +       DEF_FIXED("s1d8",       R8A779A0_CLK_S1D8,   CLK_S1, 8, 1),
> > +       DEF_FIXED("s1d12",      R8A779A0_CLK_S1D12,  CLK_S1, 12, 1),
> > +       DEF_FIXED("s2d1",       R8A779A0_CLK_S2D1,   CLK_S2, 1, 1),
> > +       DEF_FIXED("s2d2",       R8A779A0_CLK_S2D2,   CLK_S2, 2, 1),
> > +       DEF_FIXED("s2d4",       R8A779A0_CLK_S2D4,   CLK_S2, 4, 1),
> > +       DEF_FIXED("s3d1",       R8A779A0_CLK_S3D1,   CLK_S3, 1, 1),
> > +       DEF_FIXED("s3d2",       R8A779A0_CLK_S3D2,   CLK_S3, 2, 1),
> > +       DEF_FIXED("s3d4",       R8A779A0_CLK_S3D4,   CLK_S3, 4, 1),
> 
> Please align the values in the last column.

I got it.

> > +       DEF_FIXED("zs",         R8A779A0_CLK_ZS,     CLK_PLL1_DIV2,   4, 1),
> > +       DEF_FIXED("zt",         R8A779A0_CLK_ZT,     CLK_PLL1_DIV2,   2, 1),
> > +       DEF_FIXED("ztr",        R8A779A0_CLK_ZTR,    CLK_PLL1_DIV2,   2, 1),
> > +       DEF_FIXED("zr",         R8A779A0_CLK_ZR,     CLK_PLL1_DIV2,   1, 1),
> 
> ZR = PLL6 / 4.
> Is PLL6 the same as PLL1, they always run at the same rate?
> There don't seem to be any registers documented to control PLL6VCO.

According to the internal manual, V3U doesn't have PLL6.
And, ZR is connected to PLL1 / 2.

> > +       DEF_FIXED("dsi",        R8A779A0_CLK_DSI,    CLK_PLL5_DIV4,   1, 1),
> > +       DEF_FIXED("cnndsp",     R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4,   1, 1),
> > +       DEF_FIXED("vip",        R8A779A0_CLK_VIP,    CLK_PLL5,        5, 1),
> > +       DEF_FIXED("adgh",       R8A779A0_CLK_ADGH,   CLK_PLL5_DIV4,   1, 1),
> > +       DEF_FIXED("icu",        R8A779A0_CLK_ICU,    CLK_PLL5_DIV4,   2, 1),
> > +       DEF_FIXED("icud2",      R8A779A0_CLK_ICUD2,  CLK_PLL5_DIV4,   4, 1),
> > +       DEF_FIXED("vcbus",      R8A779A0_CLK_VCBUS,  CLK_PLL5_DIV4,   1, 1),
> > +
> > +       DEF_FIXED("cbfusa",     R8A779A0_CLK_CBFUSA, CLK_MAIN,   2, 1),
> > +
> > +       DEF_DIV6P1("mso",       R8A779A0_CLK_MSO,    CLK_PLL5_DIV4, 0x87c),
> > +       DEF_DIV6P1("canfd",     R8A779A0_CLK_CANFD,  CLK_PLL5_DIV4, 0x878),
> > +       DEF_DIV6P1("csi0",      R8A779A0_CLK_CSI0,   CLK_PLL5_DIV4, 0x880),
> > +       DEF_DIV6P1("fray",      R8A779A0_CLK_FRAY,   CLK_PLL5_DIV4, 0x88c),
> 
> The FRAY register doesn't seem to be documented?

It seems so... So, since we are not using this clock for now, I'll drop it.

> > +       DEF_DIV6P1("post",      R8A779A0_CLK_POST,   CLK_PLL5_DIV4, 0x890),
> > +       DEF_DIV6P1("post2",     R8A779A0_CLK_POST2,  CLK_PLL5_DIV4, 0x894),
> > +       DEF_DIV6P1("post3",     R8A779A0_CLK_POST3,  CLK_PLL5_DIV4, 0x898),
> > +
> > +       DEF_R8A779A0_OSC("osc", R8A779A0_CLK_OSCCLK, CLK_EXTAL,     8),
> > +       DEF_R8A779A0_MDSEL("r", R8A779A0_CLK_RCLK, 29, CLK_EXTALR, 1, CLK_OCO, 1),
> > +};
> > +
> > +static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
> > +       DEF_MOD("scif0",        702,    R8A779A0_CLK_S1D8),
> > +       DEF_MOD("scif1",        703,    R8A779A0_CLK_S1D8),
> > +       DEF_MOD("scif3",        704,    R8A779A0_CLK_S1D8),
> > +       DEF_MOD("scif4",        705,    R8A779A0_CLK_S1D8),
> > +};
> > +
> > +static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {
> > +       MOD_CLK_ID(408),        /* INTC-AP (GIC) */
> 
> There's no entry for this clock in r8a779a0_mod_clks[] above, so please
> drop this.
> Also, the INTC-AP clock is not documented, unfortunately.

I got it. I'll drop it.

> > +};
> > +
> > +#define CPG_PLL20CR            0x0834
> > +#define CPG_PLL21CR            0x0838
> > +#define CPG_PLL30CR            0x083c
> > +#define CPG_PLL31CR            0x0840
> > +
> > +static spinlock_t cpg_lock;
> > +
> > +static void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set)
> > +{
> > +       unsigned long flags;
> > +       u32 val;
> > +
> > +       spin_lock_irqsave(&cpg_lock, flags);
> > +       val = readl(reg);
> > +       val &= ~clear;
> > +       val |= set;
> > +       writel(val, reg);
> > +       spin_unlock_irqrestore(&cpg_lock, flags);
> > +};
> > +
> > +/*
> > + * Z Clock & Z2 Clock
> 
> All the Z clock code is currently unused.

Oops. You're correct. I'll drop Z clock code.

> > +struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
> > +       const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
> > +       struct clk **clks, void __iomem *base,
> > +       struct raw_notifier_head *notifiers)
> > +{
> 
> > +       case CLK_TYPE_R8A779A0_PLL20:
> > +               value = readl(base + CPG_PLL20CR);
> > +               mult = (((value >> 24) & 0x7f) + 1) * 2;
> > +               break;
> > +
> > +       case CLK_TYPE_R8A779A0_PLL21:
> > +               value = readl(base + CPG_PLL21CR);
> > +               mult = (((value >> 24) & 0x7f) + 1) * 2;
> > +               break;
> > +
> > +       case CLK_TYPE_R8A779A0_PLL30:
> > +               value = readl(base + CPG_PLL30CR);
> > +               mult = (((value >> 24) & 0x7f) + 1) * 2;
> > +               break;
> > +
> > +       case CLK_TYPE_R8A779A0_PLL31:
> > +               value = readl(base + CPG_PLL31CR);
> > +               mult = (((value >> 24) & 0x7f) + 1) * 2;
> > +               break;
> 
> Perhaps CLK_TYPE_R8A779A0_PLL[23][01] can share a common type, encoding
> the register offset in cpg_core_clk.offset?

I think so. If so, should I add a new macro in the r8a779a0-cpg-mssr.c to set .offset?

> > +const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = {
> > +       /* Core Clocks */
> > +       .core_clks = r8a779a0_core_clks,
> > +       .num_core_clks = ARRAY_SIZE(r8a779a0_core_clks),
> > +       .last_dt_core_clk = LAST_DT_CORE_CLK,
> > +       .num_total_core_clks = MOD_CLK_BASE,
> > +
> > +       /* Module Clocks */
> > +       .mod_clks = r8a779a0_mod_clks,
> > +       .num_mod_clks = ARRAY_SIZE(r8a779a0_mod_clks),
> > +       .num_hw_mod_clks = 12 * 32,
> 
> 15 * 32

Oops. I'll fix it.

> > +
> > +       /* Critical Module Clocks */
> > +       .crit_mod_clks = r8a779a0_crit_mod_clks,
> > +       .num_crit_mod_clks = ARRAY_SIZE(r8a779a0_crit_mod_clks),
> > +
> > +       /* Callbacks */
> > +       .init = r8a779a0_cpg_mssr_init,
> > +       .cpg_clk_register = rcar_r8a779a0_cpg_clk_register,
> > +
> > +       /* The device has only MSTP Control Register */
> > +       .mstpctrl = true,
> > +};
> > diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
> > index 5a306d2..c259e05 100644
> > --- a/drivers/clk/renesas/renesas-cpg-mssr.c
> > +++ b/drivers/clk/renesas/renesas-cpg-mssr.c
> > @@ -57,8 +57,14 @@ static const u16 mstpsr[] = {
> >         0x9A0, 0x9A4, 0x9A8, 0x9AC,
> >  };
> >
> > -#define        MSTPSR(i)       mstpsr[i]
> > +static const u16 mstpsr_mstpcr_only[] = {
> > +       0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
> > +       0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38,
> > +};
> > +
> > +static bool mstpcr_only;
> >
> > +#define        MSTPSR(i)       (mstpcr_only ? mstpsr_mstpcr_only[i] : mstpsr[i])
> 
> IMHO, ugly macro handling...
> 
> >
> >  /*
> >   * System Module Stop Control Register offsets
> > @@ -69,7 +75,8 @@ static const u16 smstpcr[] = {
> >         0x990, 0x994, 0x998, 0x99C,
> >  };
> >
> > -#define        SMSTPCR(i)      smstpcr[i]
> > +#define        SMSTPCR(i)      (mstpcr_only ? (mstpsr_mstpcr_only[i] - 0x100) : \
> > +                        smstpcr[i])
> 
> .. more ugly macro handling.
> Still, it doesn't handle the Software Reset and Clearing registers.
> 
> > @@ -140,7 +147,7 @@ struct cpg_mssr_priv {
> >         struct {
> >                 u32 mask;
> >                 u32 val;
> > -       } smstpcr_saved[ARRAY_SIZE(smstpcr)];
> > +       } smstpcr_saved[ARRAY_SIZE(mstpsr_mstpcr_only)];
> 
> Basically the maximum number of registers to save.
> 
> > @@ -938,6 +951,7 @@ static int __init cpg_mssr_common_init(struct device *dev,
> >         priv->last_dt_core_clk = info->last_dt_core_clk;
> >         RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
> >         priv->stbyctrl = info->stbyctrl;
> > +       mstpcr_only = info->mstpctrl;
> >
> >         for (i = 0; i < nclks; i++)
> >                 priv->clks[i] = ERR_PTR(-ENOENT);
> > diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
> > index 1cc5694..061eb83 100644
> > --- a/drivers/clk/renesas/renesas-cpg-mssr.h
> > +++ b/drivers/clk/renesas/renesas-cpg-mssr.h
> > @@ -131,6 +131,7 @@ struct cpg_mssr_info {
> >         unsigned int last_dt_core_clk;
> >         unsigned int num_total_core_clks;
> >         bool stbyctrl;
> > +       bool mstpctrl;
> 
> Personally, I don't like adding a second boolean flag, to be checked in
> multiple places, hidden inside macros.

I understood it.

> I think this can be handled better by defining multiple registers layout
> variants using an enum, for
>   1. R-Car Gen2/3-style register layouts,
>   2. RZ/A-style register layouts,
>   3. R-Car V3U-style register layout.
> Then register tables pointers can be set up based on the enum value, and
> code can check the enum value where needed.
> 
> Note that layout 1 can also be used for SH/R-Mobile, and we could easily
> add a 4th layout for R-Car Gen1, if we ever migrate SH/R-Mobile and/or
> R-Car Gen1 to CPG/MSSR.
> 
> What do you think?

It's a nice idea! I think the enum value of layout 1 should be 0 for
minimum changes :) So, I'll try to implement such a code.

Best regards,
Yoshihiro Shimoda

Re: [PATCH 12/14] clk: renesas: cpg-mssr: Add support for R-Car V3U

[Geert Uytterhoeven]

Hi Shimoda-san,

On Wed, Sep 9, 2020 at 4:53 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> > From: Geert Uytterhoeven, Sent: Wednesday, September 9, 2020 12:22 AM
> > On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
> > <yoshihiro.shimoda.uh@renesas.com> wrote:
> > > Initial support for R-Car V3U (r8a779a0), including core, module
> > > clocks and register access, because register specification differs
> > > than R-Car Gen2/3.

> > > +struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
> > > +       const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
> > > +       struct clk **clks, void __iomem *base,
> > > +       struct raw_notifier_head *notifiers)
> > > +{
> >
> > > +       case CLK_TYPE_R8A779A0_PLL20:
> > > +               value = readl(base + CPG_PLL20CR);
> > > +               mult = (((value >> 24) & 0x7f) + 1) * 2;
> > > +               break;
> > > +
> > > +       case CLK_TYPE_R8A779A0_PLL21:
> > > +               value = readl(base + CPG_PLL21CR);
> > > +               mult = (((value >> 24) & 0x7f) + 1) * 2;
> > > +               break;
> > > +
> > > +       case CLK_TYPE_R8A779A0_PLL30:
> > > +               value = readl(base + CPG_PLL30CR);
> > > +               mult = (((value >> 24) & 0x7f) + 1) * 2;
> > > +               break;
> > > +
> > > +       case CLK_TYPE_R8A779A0_PLL31:
> > > +               value = readl(base + CPG_PLL31CR);
> > > +               mult = (((value >> 24) & 0x7f) + 1) * 2;
> > > +               break;
> >
> > Perhaps CLK_TYPE_R8A779A0_PLL[23][01] can share a common type, encoding
> > the register offset in cpg_core_clk.offset?
>
> I think so. If so, should I add a new macro in the r8a779a0-cpg-mssr.c to set .offset?

Indeed, a new macro similar to the existing DEF_GEN3_SD().

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 10/14] soc: renesas: r8a779a0-sysc: Add r8a779a0 support

[Yoshihiro Shimoda]

Hi Geert-san,

Thank you for your review!

> From: Geert Uytterhoeven, Sent: Tuesday, September 8, 2020 8:20 PM
> 
>  Hi Shimoda-san,
> 
> On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > Add support for R-Car V3U (R8A779A0) SoC power areas and
> > register access, because register specification differs
> > than R-Car Gen2/3.
> >
> > Inspired by patches in the BSP by Tho Vu.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> 
> Thanks for your patch!
> 
> > --- /dev/null
> > +++ b/drivers/soc/renesas/r8a779a0-sysc.c
> > @@ -0,0 +1,460 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Renesas R-Car V3U System Controller
> > + *
> > + * Copyright (C) 2020 Renesas Electronics Corp.
> > + */
> > +
> > +#include <linux/bits.h>
> > +#include <linux/clk/renesas.h>
> > +#include <linux/delay.h>
> > +#include <linux/err.h>
> > +#include <linux/kernel.h>
> > +#include <linux/mm.h>
> > +#include <linux/of_address.h>
> > +#include <linux/pm_domain.h>
> > +#include <linux/slab.h>
> > +#include <linux/spinlock.h>
> > +#include <linux/io.h>
> > +#include <linux/soc/renesas/rcar-sysc.h>
> > +#include <linux/sys_soc.h>
> > +#include <linux/syscore_ops.h>
> 
> The above 3 includes are not needed.

I got it.

> > +
> > +#include <dt-bindings/power/r8a779a0-sysc.h>
> > +
> > +#include "rcar-sysc.h"
> 
> You don't reuse the rcar-sysc driver itself, but you do reuse its header
> file.  As the comments in rcar-sysc.h refer to registers that have been
> renamed (e.g. PWR*), and SYSCEXTMASK no longer exists, it might be
> easier for the casual reader to drop the include, copy the PD_*
> definitions, and define new r8a779a0_sysc_area and r8a779a0_sysc_info
> structures instead, using the new naming.

I understood it. I'll do that.

> > +
> > +static struct rcar_sysc_area r8a779a0_areas[] __initdata = {
> > +       { "always-on",       0, 0, R8A779A0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
> > +       { "a3e0",       0x1500, 0, R8A779A0_PD_A3E0, R8A779A0_PD_ALWAYS_ON, PD_SCU },
> 
> I think you can drop:
>   - chan_offs: it's always 0x1000 + pdr * 64,
>   - chan_bit: it's always zero,

I got it.

> > +/* SYSC Common */
> > +#define SYSCSR         0x000   /* SYSC Status Register */
> > +#define SYSCPONSR(x)   (0x800 + ((x) * 0x4)) /* Power-ON Status Register 0 */
> > +#define SYSCPOFFSR(x)  (0x808 + ((x) * 0x4)) /* Power-OFF Status Register */
> > +#define SYSCISCR(x)    (0x810 + ((x) * 0x4)) /* Interrupt Status/Clear Register */
> > +#define SYSCIER(x)     (0x820 + ((x) * 0x4)) /* Interrupt Enable Register */
> > +#define SYSCIMR(x)     (0x830 + ((x) * 0x4)) /* Interrupt Mask Register */
> > +
> > +/* Power Domain Registers */
> > +#define PDRSR(n)       (0x1000 + ((n) * 0x40))
> > +#define PDRONCR(n)     (0x1004 + ((n) * 0x40))
> > +#define PDROFFCR(n)    (0x1008 + ((n) * 0x40))
> > +#define PDRESR(n)      (0x100C + ((n) * 0x40))
> 
> While PDRESRn is described, and shown in a figure, it was forgotten in
> the Table 9.2 ("List of Registers (Power Domain Registers for each power
> domain)").

You're right.

> > +
> > +/* Power State */
> > +#define PW_ACTIVE      1       /* Active setting */
> 
> "/* PWRON/PWROFF */"?

I'll fix these lines like below:
/* PWRON/PWROFF */
#define PWRON_PWROFF		BIT(0)	/* Power-ON/OFF request */

> > +
> > +/* PDRSR */
> > +#define PDRSR_OFF              BIT(0)  /* Power-OFF state */
> > +#define PDRSR_ON               BIT(4)  /* Power-ON state */
> > +#define PDRSR_OFF_STATE                BIT(8)  /* Processing Power-OFF sequence */
> > +#define PDRSR_ON_STATE         BIT(12) /* Processing Power-ON sequence */
> > +
> > +#define SYSCSR_PONENB          1       /* Ready for power resume requests */
> > +#define SYSCSR_POFFENB         0       /* Ready for power shutoff requests */
> 
> These two bits are now combined into a single BUSY bit mask:
> (doh, all bits sets is not busy?!?)
> 
> #define SYSCSR_BUSY    GENMASK(1, 0)    /* All bit sets is not busy */

I got it. I'll fix it.

> > +
> > +#define SYSCSR_RETRIES         1000
> > +#define SYSCSR_DELAY_US                10
> > +
> > +#define PDRESR_RETRIES         1000
> > +#define PDRESR_DELAY_US                10
> > +
> > +#define SYSCISR_RETRIES                1000
> > +#define SYSCISR_DELAY_US       10
> > +
> > +#define R8A779A0_NUM_PD_ALWAYS_ON      64      /* Always-on power area */
> 
> Just use R8A779A0_PD_ALWAYS_ON instead?

I'll fix it.

> > +
> > +#define NUM_DOMAINS_EACH_REG   32
> 
> BITS_PER_TYPE(u32)?

I'll fix it.

> > +
> > +struct rcar_sysc_ch {
> > +       u16 chan_offs;
> > +       u8 chan_bit;
> > +       u8 isr_bit;
> > +};
> 
> As chan_offs is unused, and chan_bit is always zero, I think all use of
> this struct can just be replaced by "unsigned int pdr"?

I'll fix it.

> > +
> > +static void __iomem *rcar_sysc_base;
> 
> s/rcar/r8a779a0/ everywhere?

I think so. I'll rename it.

> > +static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
> > +
> > +static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on)
> > +{
> > +       unsigned int sr_bit, reg_offs;
> 
> sr_bit is no longer needed.

I'll drop it.

> > +       int k;
> > +
> > +       if (on) {
> > +               sr_bit = SYSCSR_PONENB;
> > +               reg_offs = PDRONCR(sysc_ch->isr_bit);
> > +       } else {
> > +               sr_bit = SYSCSR_POFFENB;
> > +               reg_offs = PDROFFCR(sysc_ch->isr_bit);
> > +       }
> > +
> > +       /* Wait until SYSC is ready to accept a power request */
> > +       for (k = 0; k < SYSCSR_RETRIES; k++) {
> > +               if (ioread32(rcar_sysc_base + SYSCSR) & BIT(sr_bit))
> 
>     if ((ioread32(rcar_sysc_base + SYSCSR) & SYSCSR_BUSY) == SYSCSR_BUSY)
> 
> > +                       break;
> > +               udelay(SYSCSR_DELAY_US);
> > +       }
> 
> Perhaps you can use readl_poll_timeout()?

I think so. I'll fix it.

> > +
> > +       if (k == SYSCSR_RETRIES)
> > +               return -EAGAIN;
> > +
> > +       /* Submit power shutoff or power resume request */
> > +       iowrite32(PW_ACTIVE, rcar_sysc_base + reg_offs);
> > +
> > +       return 0;
> > +}
> > +
> > +static int clear_irq_flags(unsigned int reg_idx, unsigned int isr_mask)
> > +{
> > +       int k = 0;
> > +
> > +       iowrite32(isr_mask, rcar_sysc_base + SYSCISCR(reg_idx));
> > +
> > +       for (k = 0; k < SYSCISR_RETRIES; k++) {
> > +               if ((ioread32(rcar_sysc_base + SYSCISCR(reg_idx)) & isr_mask) == 0)
> > +                       break;
> > +
> > +               udelay(SYSCISR_DELAY_US);
> > +       }
> 
> readl_poll_timeout()?

Yes, I'll use it.

> > +
> > +       if (k == SYSCISR_RETRIES) {
> > +               pr_err("\n %s : Can not clear IRQ flags in SYSCISCR", __func__);
> > +               return -EIO;
> > +       }
> > +
> > +       return 0;
> > +}
> 
> > +static bool has_cpg_mstp;
> 
> Please drop this and all related code, R-Car V3U does not use the legacy
> CPG/MSSR PM Domain.

I'll drop it.

> > +static const struct of_device_id rcar_sysc_matches[] __initconst = {
> > +#ifdef CONFIG_SYSC_R8A779A0
> 
> Please drop the #ifdef, as compilation of this file already depends on
> this symbol.

Oops. I got it.

Best regards,
Yoshihiro Shimoda

RE: [PATCH 11/14] soc: renesas: rcar-rst: Add support for R-Car V3U

[Yoshihiro Shimoda]

Hi Geert-san,

> From: Geert Uytterhoeven, Sent: Tuesday, September 8, 2020 8:36 PM
> 
> Hi Shimoda-san,
> 
> On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > Add support for R-Car V3U (R8A779A0) to the R-Car RST driver.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> 
> Thanks for your patch!
> 
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Thank you for your review!

> > --- a/drivers/soc/renesas/rcar-rst.c
> > +++ b/drivers/soc/renesas/rcar-rst.c
> > @@ -37,6 +37,10 @@ static const struct rst_config rcar_rst_gen3 __initconst = {
> >         .modemr = 0x60,
> >  };
> >
> > +static const struct rst_config rcar_rst_r8a779a0 __initconst = {
> > +       .modemr = 0x00,         /* MODEMR0 and it has CPG related bits */
> 
> Do you need the bits from MODEMR1, too?
> Perhaps the time is ripe to add rcar_rst_read_mode_pins64(),
> so users can access more than 32 bits on SoCs that provide it (R-Car
> V3H and V3U)?

I think so. However, main users of rcar_rst_read_mode_pins()
are cpg drivers for now. So, perhaps no one uses more than 32 bits for now.

> At least the numbering is sane on R-Car V3U. On R-Car V3H, MD29 and
> higher are stored starting at bit 1 of the second MODEMR register...

Oh, it's strange assignment...

Best regards,
Yoshihiro Shimoda

Re: [PATCH 11/14] soc: renesas: rcar-rst: Add support for R-Car V3U

[Geert Uytterhoeven]

Hi Shimoda-san,

On Thu, Sep 10, 2020 at 6:45 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> > From: Geert Uytterhoeven, Sent: Tuesday, September 8, 2020 8:36 PM
> > On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
> > <yoshihiro.shimoda.uh@renesas.com> wrote:
> > > Add support for R-Car V3U (R8A779A0) to the R-Car RST driver.
> > >
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

> > > --- a/drivers/soc/renesas/rcar-rst.c
> > > +++ b/drivers/soc/renesas/rcar-rst.c
> > > @@ -37,6 +37,10 @@ static const struct rst_config rcar_rst_gen3 __initconst = {
> > >         .modemr = 0x60,
> > >  };
> > >
> > > +static const struct rst_config rcar_rst_r8a779a0 __initconst = {
> > > +       .modemr = 0x00,         /* MODEMR0 and it has CPG related bits */
> >
> > Do you need the bits from MODEMR1, too?
> > Perhaps the time is ripe to add rcar_rst_read_mode_pins64(),
> > so users can access more than 32 bits on SoCs that provide it (R-Car
> > V3H and V3U)?
>
> I think so. However, main users of rcar_rst_read_mode_pins()
> are cpg drivers for now. So, perhaps no one uses more than 32 bits for now.

We can always add rcar_rst_read_mode_pins64() when it becomes really
needed.

Hence i.e. will queue this as-is in renesas-devel for v5.10.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 02/14] dt-bindings: arm: renesas: Document Renesas Falcon boards

[Geert Uytterhoeven]

Hi Shimoda-san,

On Tue, Sep 8, 2020 at 10:45 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> > From: Geert Uytterhoeven, Sent: Tuesday, September 8, 2020 4:12 PM
> > On Tue, Sep 8, 2020 at 3:01 AM Yoshihiro Shimoda
> > <yoshihiro.shimoda.uh@renesas.com> wrote:
> > > > From: Geert Uytterhoeven, Sent: Tuesday, September 8, 2020 12:31 AM
> > > > On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
> > > > <yoshihiro.shimoda.uh@renesas.com> wrote:
> > > > > Add device tree bindings documentation for Renesas R-Car V3U
> > > > > Falcon CPU and BreakOut boards.
> > > > >
> > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > >
> > > > Thanks for your patch!
> > > >
> > > > > --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> > > > > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> > > > > @@ -283,6 +283,9 @@ properties:
> > > > >
> > > > >        - description: R-Car V3U (R8A779A0)
> > > > >          items:
> > > > > +          - enum:
> > > > > +              - renesas,falcon-cpu # Falcon CPU board (RTP0RC779A0CPB0010S)
> > > > > +              - renesas,falcon-breakout # Falcon BreakOut board (RTP0RC779A0BOB0010S)
> > > > >            - const: renesas,r8a779a0
> > > >
> > > > How is this intended to be used?
> > >
> > > I intended to use "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0"
> > > in the future. However, if so, I should fix the description like Kingfisher.
> > >
> > > > The above means its users should declare either
> > > >
> > > >     compatible = "renesas,falcon-cpu", "renesas,r8a779a0";
> > > >
> > > > or
> > > >
> > > >     compatible = "renesas,falcon-breakout", "renesas,r8a779a0";
> > >
> > > I understood it. I mistook the description...
> > >
> > > > However, falcon-cpu.dtsi has just
> > > >
> > > >     compatible = "renesas,falcon-cpu";
> > > >
> > > > Who will use "renesas,falcon-breakout"?
> > >
> > > I intended to add falcon-breakout.dtsi and the file intended to use
> > > "renesas,falcon-breakout" like Kingfisher + ULCB in the future.
> > >
> > > However, I realized a combination between the cpu board and
> > > the breakout board differs than ULCB + Kingfisher like below:
> > >
> > > - The ULCB without the Kingfisher can work.
> > > -- So, some .dts files exist like r8a77951-ulcb.dts.
> > > -- And, r8a77951-ulcb-kf.dts includes r8a77951-ulcb.dts for ULCB + Kingfisher.
> > >
> > > - The Falcon CPU board without the breakout board cannot work actually.
> > > -- But, on this initial patch series enables the CPU board hardware (memory nodes & SCIF0) only.
> > > -- The breakout board has some hardware like Ethernet and CAN.
> > > -- The breakout board also has some connectors for sub boards.
> > > -- So, I intended to add falcon-breakout.dtsi to support Ethernet in the future.
> > >
> > > In this case, I wonder if we should describe just "renesas,falcon" only
> > > because we will not have r8a779a0-falcon-{cpu,breakout}.dts files.
> > > But, what do you think?
> >
> > What kind of connector does the Falcon CPU board have?
> > Perhaps it can be plugged into another base board, too?
>
> The Falcon CPU board has 2 EXIO connectors. The EXIO connector
> has 400 pins. So, I think it can be plugged into another base board.
>
> > What about modelling it like the iwave,g22m SoM, and the iwave,g22d
> > SODIMM board?
> > arch/arm/boot/dts/r8a7745-iwg*
>
> Thank you for the suggestion. So, I'll fix the patch like below.
> ---
>
>        - description: R-Car V3U (R8A779A0)
>          items:
> +          - enum:
> +              - renesas,r8a779a0-cpu # Falcon CPU board (RTP0RC779A0CPB0010S
> +          - const: renesas,r8a779a0
> +
> +      - items:
> +          - enum:
> +              - renesas,r8a779a0-breakout # Falcon BreakOut board (RTP0RC779A0BOB0010S)
> +          - const: renesas,r8a779a0-cpu
>            - const: renesas,r8a779a0
>
>        - description: RZ/N1D (R9A06G032)
> ---
>
> And, I will fix the compatible of r8a779a0-falcon.dts in the patch 14/14 like below.
> ---
> +       compatible = "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0";
> ---
>
> But, what do you think?

Thanks, looks good to me.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 02/14] dt-bindings: arm: renesas: Document Renesas Falcon boards

[Yoshihiro Shimoda]

Hi Geert-san,

> From: Geert Uytterhoeven, Sent: Thursday, September 10, 2020 6:10 PM
> On Tue, Sep 8, 2020 at 10:45 AM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > > From: Geert Uytterhoeven, Sent: Tuesday, September 8, 2020 4:12 PM
> > > On Tue, Sep 8, 2020 at 3:01 AM Yoshihiro Shimoda
> > > <yoshihiro.shimoda.uh@renesas.com> wrote:
> > > > > From: Geert Uytterhoeven, Sent: Tuesday, September 8, 2020 12:31 AM
> > > > > On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
> > > > > <yoshihiro.shimoda.uh@renesas.com> wrote:
> > > > > > Add device tree bindings documentation for Renesas R-Car V3U
> > > > > > Falcon CPU and BreakOut boards.
> > > > > >
> > > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > > >
> > > > > Thanks for your patch!
> > > > >
> > > > > > --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> > > > > > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> > > > > > @@ -283,6 +283,9 @@ properties:
> > > > > >
> > > > > >        - description: R-Car V3U (R8A779A0)
> > > > > >          items:
> > > > > > +          - enum:
> > > > > > +              - renesas,falcon-cpu # Falcon CPU board (RTP0RC779A0CPB0010S)
> > > > > > +              - renesas,falcon-breakout # Falcon BreakOut board (RTP0RC779A0BOB0010S)
> > > > > >            - const: renesas,r8a779a0
> > > > >
> > > > > How is this intended to be used?
> > > >
> > > > I intended to use "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0"
> > > > in the future. However, if so, I should fix the description like Kingfisher.
> > > >
> > > > > The above means its users should declare either
> > > > >
> > > > >     compatible = "renesas,falcon-cpu", "renesas,r8a779a0";
> > > > >
> > > > > or
> > > > >
> > > > >     compatible = "renesas,falcon-breakout", "renesas,r8a779a0";
> > > >
> > > > I understood it. I mistook the description...
> > > >
> > > > > However, falcon-cpu.dtsi has just
> > > > >
> > > > >     compatible = "renesas,falcon-cpu";
> > > > >
> > > > > Who will use "renesas,falcon-breakout"?
> > > >
> > > > I intended to add falcon-breakout.dtsi and the file intended to use
> > > > "renesas,falcon-breakout" like Kingfisher + ULCB in the future.
> > > >
> > > > However, I realized a combination between the cpu board and
> > > > the breakout board differs than ULCB + Kingfisher like below:
> > > >
> > > > - The ULCB without the Kingfisher can work.
> > > > -- So, some .dts files exist like r8a77951-ulcb.dts.
> > > > -- And, r8a77951-ulcb-kf.dts includes r8a77951-ulcb.dts for ULCB + Kingfisher.
> > > >
> > > > - The Falcon CPU board without the breakout board cannot work actually.
> > > > -- But, on this initial patch series enables the CPU board hardware (memory nodes & SCIF0) only.
> > > > -- The breakout board has some hardware like Ethernet and CAN.
> > > > -- The breakout board also has some connectors for sub boards.
> > > > -- So, I intended to add falcon-breakout.dtsi to support Ethernet in the future.
> > > >
> > > > In this case, I wonder if we should describe just "renesas,falcon" only
> > > > because we will not have r8a779a0-falcon-{cpu,breakout}.dts files.
> > > > But, what do you think?
> > >
> > > What kind of connector does the Falcon CPU board have?
> > > Perhaps it can be plugged into another base board, too?
> >
> > The Falcon CPU board has 2 EXIO connectors. The EXIO connector
> > has 400 pins. So, I think it can be plugged into another base board.
> >
> > > What about modelling it like the iwave,g22m SoM, and the iwave,g22d
> > > SODIMM board?
> > > arch/arm/boot/dts/r8a7745-iwg*
> >
> > Thank you for the suggestion. So, I'll fix the patch like below.
> > ---
> >
> >        - description: R-Car V3U (R8A779A0)
> >          items:
> > +          - enum:
> > +              - renesas,r8a779a0-cpu # Falcon CPU board (RTP0RC779A0CPB0010S
> > +          - const: renesas,r8a779a0
> > +
> > +      - items:
> > +          - enum:
> > +              - renesas,r8a779a0-breakout # Falcon BreakOut board (RTP0RC779A0BOB0010S)
> > +          - const: renesas,r8a779a0-cpu
> >            - const: renesas,r8a779a0
> >
> >        - description: RZ/N1D (R9A06G032)
> > ---
> >
> > And, I will fix the compatible of r8a779a0-falcon.dts in the patch 14/14 like below.
> > ---
> > +       compatible = "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0";
> > ---
> >
> > But, what do you think?
> 
> Thanks, looks good to me.

Thank you for your reply! I'll fix it.

Best regards,
Yoshihiro Shimoda

RE: [PATCH 13/14] arm64: dts: renesas: Add Renesas R8A779A0 SoC support

[Yoshihiro Shimoda]

Hi Geert-san,

Thank you for your review!

> From: Geert Uytterhoeven, Sent: Wednesday, September 9, 2020 2:16 AM
> 
> Hi Shimoda-san,
> 
> On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > Add initial support for the Renesas R8A77990 (R-Car V3U) support.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> 
> Thanks for your patch!
> 
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> 
> > +       soc: soc {
> 
> > +
> > +               sysc: system-controller@e6180000 {
> > +                       compatible = "renesas,r8a779a0-sysc";
> > +                       reg = <0 0xe6180000 0 0x3078>;
> 
> Length 0x4000?

Yes, I'll fix it.

> > +                       #power-domain-cells = <1>;
> > +               };
> > +
> > +               scif0: serial@e6e60000 {
> > +                       compatible = "renesas,scif-r8a779a0",
> > +                                    "renesas,rcar-gen3-scif", "renesas,scif";
> > +                       reg = <0 0xe6e60000 0 64>;
> > +                       interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&cpg CPG_MOD 702>,
> > +                                <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
> > +                                <&scif_clk>;
> > +                       clock-names = "fck", "brg_int", "scif_clk";
> > +                       power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
> 
> Missing resets property.

Oops. I'll add it.

> > +                       status = "disabled";
> > +               };
> > +
> > +               gic: interrupt-controller@f1000000 {
> > +                       compatible = "arm,gic-v3";
> > +                       #interrupt-cells = <3>;
> > +                       #address-cells = <0>;
> > +                       interrupt-controller;
> > +                       reg = <0x0 0xf1000000 0 0x20000>,
> > +                             <0x0 0xf1060000 0 0x110000>;
> > +                       interrupts = <GIC_PPI 9
> > +                                     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
> 
> "GIC_CPU_MASK_SIMPLE(1)", as currently only one CPU core is used.

I got it. I'll fix it.

> > +                       power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
> > +               };
> > +
> > +               prr: chipid@fff00044 {
> > +                       compatible = "renesas,prr";
> > +                       reg = <0 0xfff00044 0 4>;
> > +               };
> > +       };
> > +
> > +       timer {
> > +               compatible = "arm,armv8-timer";
> > +               interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> > +                                     <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> > +                                     <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> > +                                     <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
> 
> "GIC_CPU_MASK_SIMPLE(1)" for all 4 interrupts (and in the future "8",
> not "2").

Oops. You're correct. I'll fix it.

Best regards,
Yoshihiro Shimoda

RE: [PATCH 14/14] arm64: dts: renesas: Add Renesas Falcon boards support

[Yoshihiro Shimoda]

Hi Geert-san,

Thank you for your review!

> From: Geert Uytterhoeven, Sent: Wednesday, September 9, 2020 2:21 AM
> 
> Hi Shimoda-san,
> 
> On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > Initial support for the Renesas Falcon CPU and BreakOut boards
> > support.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> 
> Thanks for your patch!
> 
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/falcon-cpu.dtsi
> > @@ -0,0 +1,44 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Device Tree Source for the Falcon CPU board
> > + *
> > + * Copyright (C) 2020 Renesas Electronics Corp.
> > + */
> 
> As this board contains the CPU, I had expected
> 
>     #include "r8a779a0.dtsi"
> 
> here.

I got it. I'll add it.

> > +
> > +/ {
> > +       model = "Renesas Falcon CPU board";
> > +       compatible = "renesas,falcon-cpu";
> 
> + renesas,r8a779a0.

Oops. I'll add it.

Also, I'll fix a compatible in the r8a779a0-falcon.dts.

Best regards,
Yoshihiro Shimoda

Re: [PATCH 14/14] arm64: dts: renesas: Add Renesas Falcon boards support

[Geert Uytterhoeven]

Hi Shimoda-san,

On Thu, Sep 10, 2020 at 1:04 PM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> > From: Geert Uytterhoeven, Sent: Wednesday, September 9, 2020 2:21 AM
> > On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
> > <yoshihiro.shimoda.uh@renesas.com> wrote:
> > > Initial support for the Renesas Falcon CPU and BreakOut boards
> > > support.
> > >
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/renesas/falcon-cpu.dtsi
> > > @@ -0,0 +1,44 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + * Device Tree Source for the Falcon CPU board
> > > + *
> > > + * Copyright (C) 2020 Renesas Electronics Corp.
> > > + */
> >
> > As this board contains the CPU, I had expected
> >
> >     #include "r8a779a0.dtsi"
> >
> > here.
>
> I got it. I'll add it.

Thanks!

BTW, I forgot to mention that the file should probably be named
r8a779a0-falcon-cpu.dtsi, i.e. incl. the SoC part number prefix.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 14/14] arm64: dts: renesas: Add Renesas Falcon boards support

[Yoshihiro Shimoda]

Hi Geert-san,

> From: Geert Uytterhoeven, Sent: Thursday, September 10, 2020 8:14 PM
> 
> Hi Shimoda-san,
> 
> On Thu, Sep 10, 2020 at 1:04 PM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > > From: Geert Uytterhoeven, Sent: Wednesday, September 9, 2020 2:21 AM
> > > On Mon, Sep 7, 2020 at 11:20 AM Yoshihiro Shimoda
> > > <yoshihiro.shimoda.uh@renesas.com> wrote:
> > > > Initial support for the Renesas Falcon CPU and BreakOut boards
> > > > support.
> > > >
> > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > >
> > > Thanks for your patch!
> > >
> > > > --- /dev/null
> > > > +++ b/arch/arm64/boot/dts/renesas/falcon-cpu.dtsi
> > > > @@ -0,0 +1,44 @@
> > > > +// SPDX-License-Identifier: GPL-2.0
> > > > +/*
> > > > + * Device Tree Source for the Falcon CPU board
> > > > + *
> > > > + * Copyright (C) 2020 Renesas Electronics Corp.
> > > > + */
> > >
> > > As this board contains the CPU, I had expected
> > >
> > >     #include "r8a779a0.dtsi"
> > >
> > > here.
> >
> > I got it. I'll add it.
> 
> Thanks!
> 
> BTW, I forgot to mention that the file should probably be named
> r8a779a0-falcon-cpu.dtsi, i.e. incl. the SoC part number prefix.

I got it. I'll rename the file on v2 patch.

Best regards,
Yoshihiro Shimoda

Re: [PATCH 06/14] dt-bindings: clock: renesas,cpg-mssr: Document r8a779a0

[Rob Herring]

On Mon, 07 Sep 2020 18:19:42 +0900, Yoshihiro Shimoda wrote:
> Add binding documentation for the R-Car V3U (R8A779A0) Clock Pulse
> Generator.
> 
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
>  Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 08/14] dt-bindings: serial: renesas,scif: Document r8a779a0 bindings

[Rob Herring]

On Mon, 07 Sep 2020 18:19:44 +0900, Yoshihiro Shimoda wrote:
> R-Car V3U (R8A779A0) SoC also has the R-Car Gen3 compatible
> SCIF ports, so document the SoC specific bindings.
> 
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
>  Documentation/devicetree/bindings/serial/renesas,scif.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>