[PATCH v2 0/2] Add Ethernet to RZ/V2M

[PATCH v2 0/2] Add Ethernet to RZ/V2M

[Phil Edworthy]

Add Ethernet to the RZ/V2M SoC (r9a09g011) and the RZ/V2M EVK board.

v2:
 - Fix interrupt names

Phil Edworthy (2):
  arm64: dts: renesas: r9a09g011: Add ethernet nodes
  arm64: dts: renesas: rzv2m evk: Enable ethernet

 .../boot/dts/renesas/r9a09g011-v2mevk2.dts    | 14 +++++
 arch/arm64/boot/dts/renesas/r9a09g011.dtsi    | 51 +++++++++++++++++++
 2 files changed, 65 insertions(+)

-- 
2.34.1

[PATCH v2 1/2] arm64: dts: renesas: r9a09g011: Add ethernet nodes

[Phil Edworthy]

Add Ethernet nodes to SoC dtsi.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2:
 - Fix interrupt names
---
 arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 51 ++++++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
index 27810f4ad4cb..d4cc5459fbb7 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
@@ -62,6 +62,57 @@ gic: interrupt-controller@82000000 {
 			clock-names = "clk";
 		};
 
+		avb: ethernet@a3300000 {
+			compatible = "renesas,etheravb-r9a09g011","renesas,etheravb-rzv2m";
+			reg = <0 0xa3300000 0 0x800>;
+			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, /* ch0: Rx0 BE */
+				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, /* ch1: Rx1 NC */
+				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* ch18: Tx0 BE */
+				     <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* ch19: Tx1 NC */
+				     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, /* DiA */
+				     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, /* DiB */
+				     <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, /* Line1_A */
+				     <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, /* Line1_B */
+				     <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, /* Line2_A */
+				     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* Line2_B */
+				     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; /* Line3 MAC */
+			interrupt-names = "ch0", "ch1", "ch2", "ch3",
+					  "ch4", "ch5", "ch6", "ch7",
+					  "ch8", "ch9", "ch10", "ch11",
+					  "ch12", "ch13", "ch14", "ch15",
+					  "ch16", "ch17", "ch18", "ch19",
+					  "ch20", "ch21", "dia", "dib",
+					  "err_a", "err_b", "mgmt_a", "mgmt_b",
+					  "line3";
+			clocks = <&cpg CPG_MOD R9A09G011_ETH0_CLK_AXI>,
+				 <&cpg CPG_MOD R9A09G011_ETH0_CLK_CHI>,
+				 <&cpg CPG_MOD R9A09G011_ETH0_GPTP_EXT>;
+			clock-names = "axi", "chi", "gptp";
+			resets = <&cpg R9A09G011_ETH0_RST_HW_N>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disable";
+		};
+
 		cpg: clock-controller@a3500000 {
 			compatible = "renesas,r9a09g011-cpg";
 			reg = <0 0xa3500000 0 0x1000>;
-- 
2.34.1

[PATCH v2 2/2] arm64: dts: renesas: rzv2m evk: Enable ethernet

[Phil Edworthy]

Enable Ethernet interface on RZ/V2M EVK.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2:
 - No change
---
 arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
index 41cba82c2252..ec7099211cab 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
@@ -14,6 +14,7 @@ / {
 
 	aliases {
 		serial0 = &uart0;
+		ethernet0 = &avb;
 	};
 
 	chosen {
@@ -42,3 +43,16 @@ &extal_clk {
 &uart0 {
 	status = "okay";
 };
+
+&avb {
+	renesas,no-ether-link;
+	phy-handle = <&phy0>;
+	phy-mode = "gmii";
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-id0022.1622",
+			     "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+	};
+};
-- 
2.34.1

Re: [PATCH v2 1/2] arm64: dts: renesas: r9a09g011: Add ethernet nodes

[Geert Uytterhoeven]

On Tue, May 17, 2022 at 10:17 AM Phil Edworthy
<phil.edworthy@renesas.com> wrote:
> Add Ethernet nodes to SoC dtsi.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v2:
>  - Fix interrupt names

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.20.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 2/2] arm64: dts: renesas: rzv2m evk: Enable ethernet

[Geert Uytterhoeven]

Hi Phil,

On Tue, May 17, 2022 at 10:17 AM Phil Edworthy
<phil.edworthy@renesas.com> wrote:
> Enable Ethernet interface on RZ/V2M EVK.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v2:
>  - No change

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
> +++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
> @@ -42,3 +43,16 @@ &extal_clk {
>  &uart0 {
>         status = "okay";
>  };
> +
> +&avb {
> +       renesas,no-ether-link;
> +       phy-handle = <&phy0>;
> +       phy-mode = "gmii";
> +       status = "okay";
> +
> +       phy0: ethernet-phy@0 {
> +               compatible = "ethernet-phy-id0022.1622",

My schematics says RTL8211FG-CG, not Micrel KSZ9031?
I.e. "ethernet-phy-id001c.c916"?

As there is no PHY reset to deassert, you can remove the compatible
property, and check what's read back from the PHY ID registers.

I'd say you can just drop the compatible value completely, but you
would have to readd it anyway when the PHY reset is documented.

> +                            "ethernet-phy-ieee802.3-c22";
> +               reg = <0>;

Once you have GPIO/IRQ support, you can add the interrupts and
resets properties, pointing to P16_12 resp. P17_00.

> +       };
> +};

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v2 2/2] arm64: dts: renesas: rzv2m evk: Enable ethernet

[Phil Edworthy]

Hi Geert,

Thanks for your review!

On 19 May 2022 11:20 Geert Uytterhoeven wrote:
> On Tue, May 17, 2022 at 10:17 AM Phil Edworthy <phil.edworthy@renesas.com>
> wrote:
> > Enable Ethernet interface on RZ/V2M EVK.
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v2:
> >  - No change
> 
> Thanks for your patch!
> 
> > --- a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
> > @@ -42,3 +43,16 @@ &extal_clk {
> >  &uart0 {
> >         status = "okay";
> >  };
> > +
> > +&avb {
> > +       renesas,no-ether-link;
> > +       phy-handle = <&phy0>;
> > +       phy-mode = "gmii";
> > +       status = "okay";
> > +
> > +       phy0: ethernet-phy@0 {
> > +               compatible = "ethernet-phy-id0022.1622",
> 
> My schematics says RTL8211FG-CG, not Micrel KSZ9031?
> I.e. "ethernet-phy-id001c.c916"?
Yes, you are correct, I have since dumped the id in get_phy_c22_id().
Sorry, I should have checked that the BSP was correct.

> As there is no PHY reset to deassert, you can remove the compatible
> property, and check what's read back from the PHY ID registers.
> 
> I'd say you can just drop the compatible value completely, but you would
> have to readd it anyway when the PHY reset is documented.
> 
> > +                            "ethernet-phy-ieee802.3-c22";
> > +               reg = <0>;
> 
> Once you have GPIO/IRQ support, you can add the interrupts and resets
> properties, pointing to P16_12 resp. P17_00.
Will do!

Thanks
Phil