From: Kishon Vijay Abraham I <kishon@ti.com>
To: Andrew Murray <andrew.murray@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Rob Herring <robh+dt@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-omap@vger.kernel.org>
Subject: Re: [PATCH 05/13] PCI: cadence: Add read and write accessors to perform only 32-bit accesses
Date: Thu, 19 Dec 2019 17:26:05 +0530 [thread overview]
Message-ID: <d1ee4579-a3da-6a73-3516-a6d264f80995@ti.com> (raw)
In-Reply-To: <20191216144932.GY24359@e119886-lin.cambridge.arm.com>
Hi Andrew,
On 16/12/19 8:19 pm, Andrew Murray wrote:
> On Mon, Dec 09, 2019 at 02:51:39PM +0530, Kishon Vijay Abraham I wrote:
>> Certain platforms like TI's J721E allow only 32-bit register accesses.
>
> When I first read this I thought you meant only 32-bit accesses are allowed
> and not other sizes (such as 64-bit). However the limitation you address
> here is that the J721E allows only 32-bit *aligned* register accesses.
It's both, it allows only 32-bit aligned accesses and the size should be
only 32 bits. That's why I always use "readl" in the APIs below.
>
> It would be helpful to make this clearer in the commit message.
>
> You can also shorten the commit subject to 'PCI: cadence: Add read/write
> accessors for 32-bit aligned accesses' or similar.
>
>> Add read and write accessors to perform only 32-bit accesses in order to
>> support platfroms like TI's J721E.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>> drivers/pci/controller/cadence/pcie-cadence.c | 40 +++++++++++++++++++
>> drivers/pci/controller/cadence/pcie-cadence.h | 2 +
>> 2 files changed, 42 insertions(+)
>>
>> diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c
>> index cd795f6fc1e2..de5b3b06f2d0 100644
>> --- a/drivers/pci/controller/cadence/pcie-cadence.c
>> +++ b/drivers/pci/controller/cadence/pcie-cadence.c
>> @@ -7,6 +7,46 @@
>>
>> #include "pcie-cadence.h"
>>
>> +u32 cdns_pcie_read32(void __iomem *addr, int size)
>
> Given there is already a cdns_pcie_readl in pcie-cadence.h it may help
> to name this in a way that doesn't cause confusion. Here 32 is perhaps
> being used to suggest the size of the actual read performed, the
> maximum size of 'size' or the alignment.
>
>
>> +{
>> + void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4);
>> + unsigned int offset = (unsigned long)addr & 0x3;
>> + u32 val = readl(aligned_addr);
>> +
>> + if (!IS_ALIGNED((uintptr_t)addr, size)) {
>> + pr_err("Invalid Address in function:%s\n", __func__);
>
> Would this be better as a BUG? Without a BUG this error could get ignored
> and yet the device may not behave as expected.
yeah.
>
>
>> + return 0;
>> + }
>> +
>> + if (size > 2)
>> + return val;
>
> I think you make the assumption here that if size > 2 then it's 4. It could
> be 3 (though unlikely) in which case you'd want to fall through to the next
> line.
This assumption is used elsewhere too (e.g drivers/pci/access.c). I
generally don't prefer adding handlers for non-occurring error
scenarios, but If you insist I can fix that.
Thanks
Kishon
next prev parent reply other threads:[~2019-12-19 11:54 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-09 9:21 [PATCH 00/13] Add PCIe support to TI's J721E SoC Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 01/13] PCI: cadence: Remove stray "pm_runtime_put_sync()" in error path Kishon Vijay Abraham I
2019-12-16 13:45 ` Andrew Murray
2019-12-19 8:31 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 02/13] linux/kernel.h: Add PTR_ALIGN_DOWN macro Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 03/13] PCI: cadence: Add support to use custom read and write accessors Kishon Vijay Abraham I
2019-12-16 14:07 ` Andrew Murray
2019-12-19 11:41 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 04/13] PCI: cadence: Add support to start link and verify link status Kishon Vijay Abraham I
2019-12-17 11:58 ` Andrew Murray
2019-12-19 12:01 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 05/13] PCI: cadence: Add read and write accessors to perform only 32-bit accesses Kishon Vijay Abraham I
2019-12-09 21:15 ` Bjorn Helgaas
2019-12-16 14:49 ` Andrew Murray
2019-12-19 11:56 ` Kishon Vijay Abraham I [this message]
2019-12-19 12:03 ` Arnd Bergmann
2019-12-19 13:19 ` Kishon Vijay Abraham I
2019-12-19 20:16 ` Arnd Bergmann
2019-12-17 23:36 ` Bjorn Helgaas
2019-12-19 12:49 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 06/13] PCI: cadence: Allow pci_host_bridge to have custom pci_ops Kishon Vijay Abraham I
2019-12-17 12:32 ` Andrew Murray
2019-12-19 12:02 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 07/13] PCI: cadence: Add new *ops* for CPU addr fixup Kishon Vijay Abraham I
2019-12-17 12:40 ` Andrew Murray
2019-12-19 12:03 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 08/13] PCI: cadence: Use local management register to configure Vendor ID Kishon Vijay Abraham I
2019-12-17 12:42 ` Andrew Murray
2019-12-19 12:12 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 09/13] dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC Kishon Vijay Abraham I
2019-12-19 0:08 ` Rob Herring
2019-12-19 13:13 ` Kishon Vijay Abraham I
2019-12-24 8:06 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 10/13] dt-bindings: PCI: Add EP " Kishon Vijay Abraham I
2019-12-19 0:14 ` Rob Herring
2019-12-19 13:14 ` Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 11/13] PCI: j721e: Add TI J721E PCIe driver Kishon Vijay Abraham I
2019-12-17 14:23 ` Andrew Murray
2019-12-19 22:47 ` Bjorn Helgaas
2019-12-09 9:21 ` [PATCH 12/13] misc: pci_endpoint_test: Add J721E in pci_device_id table Kishon Vijay Abraham I
2019-12-09 9:21 ` [PATCH 13/13] MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe Kishon Vijay Abraham I
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