[PATCH] docs/memory-barriers.txt: Enforce heavy ordering for port I/O accesses

[PATCH] docs/memory-barriers.txt: Enforce heavy ordering for port I/O accesses

[Will Deacon]

David Laight explains:

  | A long time ago there was a document from Intel that said that
  | inb/outb weren't necessarily synchronised wrt memory accesses.
  | (Might be P-pro era). However no processors actually behaved that
  | way and more recent docs say that inb/outb are fully ordered.

This also reflects the situation on other architectures, the the port
accessor macros tend to be implemented in terms of readX/writeX.

Update Documentation/memory-barriers.txt to reflect reality.

Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: David Laight <David.Laight@ACULAB.COM>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---

Just remembered I had this patch kicking around in my tree...

 Documentation/memory-barriers.txt | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
index c1d913944ad8..0c34c5dac138 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -2619,10 +2619,8 @@ functions:
      intermediary bridges (such as the PCI host bridge) may not fully honour
      that.
 
-     They are guaranteed to be fully ordered with respect to each other.
-
-     They are not guaranteed to be fully ordered with respect to other types of
-     memory and I/O operation.
+     They are guaranteed to be fully ordered with respect to each other and
+     also with respect to other types of memory and I/O operation.
 
  (*) readX(), writeX():
 
-- 
2.1.4

Re: [PATCH] docs/memory-barriers.txt: Enforce heavy ordering for port I/O accesses

[Andrea Parri]

On Mon, Nov 26, 2018 at 04:52:14PM +0000, Will Deacon wrote:
> David Laight explains:
> 
>   | A long time ago there was a document from Intel that said that
>   | inb/outb weren't necessarily synchronised wrt memory accesses.
>   | (Might be P-pro era). However no processors actually behaved that
>   | way and more recent docs say that inb/outb are fully ordered.

No intention to diminish David Laight's authority of course, but I would
have really appreciated a reference to these "recent docs" (section, pg.
or the like, especially if a reference manual...) here...


> 
> This also reflects the situation on other architectures, the the port
> accessor macros tend to be implemented in terms of readX/writeX.
> 
> Update Documentation/memory-barriers.txt to reflect reality.

..., IOW, what do you mean by "reality"?

> 
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: David Laight <David.Laight@ACULAB.COM>
> Cc: Alan Stern <stern@rowland.harvard.edu>
> Cc: Peter Zijlstra <peterz@infradead.org>
> Cc: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
> Signed-off-by: Will Deacon <will.deacon@arm.com>

Please Cc me on future patches to memory-barriers.txt (can not speak for
my co-maintainers, but I'm inclined to say that get_maintainers.pl knows
better...).

  Andrea


> ---
> 
> Just remembered I had this patch kicking around in my tree...
> 
>  Documentation/memory-barriers.txt | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
> index c1d913944ad8..0c34c5dac138 100644
> --- a/Documentation/memory-barriers.txt
> +++ b/Documentation/memory-barriers.txt
> @@ -2619,10 +2619,8 @@ functions:
>       intermediary bridges (such as the PCI host bridge) may not fully honour
>       that.
>  
> -     They are guaranteed to be fully ordered with respect to each other.
> -
> -     They are not guaranteed to be fully ordered with respect to other types of
> -     memory and I/O operation.
> +     They are guaranteed to be fully ordered with respect to each other and
> +     also with respect to other types of memory and I/O operation.
>  
>   (*) readX(), writeX():
>  
> -- 
> 2.1.4
> 

Re: [PATCH] docs/memory-barriers.txt: Enforce heavy ordering for port I/O accesses

[Paul E. McKenney]

On Mon, Nov 26, 2018 at 04:52:14PM +0000, Will Deacon wrote:
> David Laight explains:
> 
>   | A long time ago there was a document from Intel that said that
>   | inb/outb weren't necessarily synchronised wrt memory accesses.
>   | (Might be P-pro era). However no processors actually behaved that
>   | way and more recent docs say that inb/outb are fully ordered.
> 
> This also reflects the situation on other architectures, the the port
> accessor macros tend to be implemented in terms of readX/writeX.
> 
> Update Documentation/memory-barriers.txt to reflect reality.
> 
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: David Laight <David.Laight@ACULAB.COM>
> Cc: Alan Stern <stern@rowland.harvard.edu>
> Cc: Peter Zijlstra <peterz@infradead.org>
> Cc: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
> Signed-off-by: Will Deacon <will.deacon@arm.com>

Queued, with the addition of Cc: of LKML, linux-arch, and linux-docs,
thank you!

(Otherwise, these lists can get lost when I send out the LKMM series.)

							Thanx, Paul

> ---
> 
> Just remembered I had this patch kicking around in my tree...
> 
>  Documentation/memory-barriers.txt | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
> index c1d913944ad8..0c34c5dac138 100644
> --- a/Documentation/memory-barriers.txt
> +++ b/Documentation/memory-barriers.txt
> @@ -2619,10 +2619,8 @@ functions:
>       intermediary bridges (such as the PCI host bridge) may not fully honour
>       that.
> 
> -     They are guaranteed to be fully ordered with respect to each other.
> -
> -     They are not guaranteed to be fully ordered with respect to other types of
> -     memory and I/O operation.
> +     They are guaranteed to be fully ordered with respect to each other and
> +     also with respect to other types of memory and I/O operation.
> 
>   (*) readX(), writeX():
> 
> -- 
> 2.1.4
> 

Re: [PATCH] docs/memory-barriers.txt: Enforce heavy ordering for port I/O accesses

[Paul E. McKenney]

On Mon, Nov 26, 2018 at 08:33:49PM +0100, Andrea Parri wrote:
> On Mon, Nov 26, 2018 at 04:52:14PM +0000, Will Deacon wrote:
> > David Laight explains:
> > 
> >   | A long time ago there was a document from Intel that said that
> >   | inb/outb weren't necessarily synchronised wrt memory accesses.
> >   | (Might be P-pro era). However no processors actually behaved that
> >   | way and more recent docs say that inb/outb are fully ordered.
> 
> No intention to diminish David Laight's authority of course, but I would
> have really appreciated a reference to these "recent docs" (section, pg.
> or the like, especially if a reference manual...) here...

I would be inclined to cut Will a break given the research for his
recent talk on this topic, but it would be good to get an ack from
someone from Intel.  And memory-model patches require an ack or better
in any case.  ;-)

							Thanx, Paul

> > This also reflects the situation on other architectures, the the port
> > accessor macros tend to be implemented in terms of readX/writeX.
> > 
> > Update Documentation/memory-barriers.txt to reflect reality.
> 
> ..., IOW, what do you mean by "reality"?
> 
> > 
> > Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: David Laight <David.Laight@ACULAB.COM>
> > Cc: Alan Stern <stern@rowland.harvard.edu>
> > Cc: Peter Zijlstra <peterz@infradead.org>
> > Cc: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
> > Signed-off-by: Will Deacon <will.deacon@arm.com>
> 
> Please Cc me on future patches to memory-barriers.txt (can not speak for
> my co-maintainers, but I'm inclined to say that get_maintainers.pl knows
> better...).
> 
>   Andrea
> 
> 
> > ---
> > 
> > Just remembered I had this patch kicking around in my tree...
> > 
> >  Documentation/memory-barriers.txt | 6 ++----
> >  1 file changed, 2 insertions(+), 4 deletions(-)
> > 
> > diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
> > index c1d913944ad8..0c34c5dac138 100644
> > --- a/Documentation/memory-barriers.txt
> > +++ b/Documentation/memory-barriers.txt
> > @@ -2619,10 +2619,8 @@ functions:
> >       intermediary bridges (such as the PCI host bridge) may not fully honour
> >       that.
> >  
> > -     They are guaranteed to be fully ordered with respect to each other.
> > -
> > -     They are not guaranteed to be fully ordered with respect to other types of
> > -     memory and I/O operation.
> > +     They are guaranteed to be fully ordered with respect to each other and
> > +     also with respect to other types of memory and I/O operation.
> >  
> >   (*) readX(), writeX():
> >  
> > -- 
> > 2.1.4
> > 
> 

Re: [PATCH] docs/memory-barriers.txt: Enforce heavy ordering for port I/O accesses

[Matthew Wilcox]

On Tue, Nov 27, 2018 at 10:40:21AM -0800, Paul E. McKenney wrote:
> On Mon, Nov 26, 2018 at 08:33:49PM +0100, Andrea Parri wrote:
> > On Mon, Nov 26, 2018 at 04:52:14PM +0000, Will Deacon wrote:
> > > David Laight explains:
> > > 
> > >   | A long time ago there was a document from Intel that said that
> > >   | inb/outb weren't necessarily synchronised wrt memory accesses.
> > >   | (Might be P-pro era). However no processors actually behaved that
> > >   | way and more recent docs say that inb/outb are fully ordered.
> > 
> > No intention to diminish David Laight's authority of course, but I would
> > have really appreciated a reference to these "recent docs" (section, pg.
> > or the like, especially if a reference manual...) here...
> 
> I would be inclined to cut Will a break given the research for his
> recent talk on this topic, but it would be good to get an ack from
> someone from Intel.  And memory-model patches require an ack or better
> in any case.  ;-)

Here's a quote from Section 18.6 of volume 1 of the Software Developer
Manual, November 2018 edition:

When the I/O address space is used instead of memory-mapped I/O, the
situation is different in two respects:
• The processor never buffers I/O writes. Therefore, strict ordering of
I/O operations is enforced by the processor. (As with memory-mapped I/O,
it is possible for a chip set to post writes in certain I/O ranges.)
• The processor synchronizes I/O instruction execution with external
bus activity (see Table 18-1).

Table 18-1 says that in* delays execution of the current instruction until
completion of pending stores, and out* delays execution of the _next_
instruction until completion of both pending stores and the current store.