* [PATCH] ras-mce-handler: Add support for Hygon Dhyana family 18h processor
@ 2019-05-23 13:00 Pu Wen
2019-06-14 2:18 ` Wen Pu
0 siblings, 1 reply; 3+ messages in thread
From: Pu Wen @ 2019-05-23 13:00 UTC (permalink / raw)
To: mchehab; +Cc: linux-edac, Pu Wen
The Hygon Dhyana family 18h processor is derived from AMD family 17h.
The Hygon Dhyana support to Linux is already accepted upstream[1].
Add Hygon Dhyana support to mce handler of rasdaemon in order to handle
MCE events on Hygon Dhyana platforms.
Reference:
[1] https://git.kernel.org/tip/fec98069fb72fb656304a3e52265e0c2fc9adf87
Signed-off-by: Pu Wen <puwen@hygon.cn>
---
ras-mce-handler.c | 9 ++++++++-
ras-mce-handler.h | 1 +
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/ras-mce-handler.c b/ras-mce-handler.c
index c11d489..eb548c6 100644
--- a/ras-mce-handler.c
+++ b/ras-mce-handler.c
@@ -55,7 +55,8 @@ static char *cputype_name[] = {
[CPU_KNIGHTS_LANDING] = "Knights Landing",
[CPU_KNIGHTS_MILL] = "Knights Mill",
[CPU_SKYLAKE_XEON] = "Skylake server",
- [CPU_NAPLES] = "AMD Family 17h Zen1"
+ [CPU_NAPLES] = "AMD Family 17h Zen1",
+ [CPU_DHYANA] = "Hygon Family 18h Moksha"
};
static enum cputype select_intel_cputype(struct ras_events *ras)
@@ -200,6 +201,11 @@ static int detect_cpu(struct ras_events *ras)
ret = EINVAL;
}
goto ret;
+ } else if (!strcmp(mce->vendor,"HygonGenuine")) {
+ if (mce->family == 24) {
+ mce->cputype = CPU_DHYANA;
+ }
+ goto ret;
} else if (!strcmp(mce->vendor,"GenuineIntel")) {
mce->cputype = select_intel_cputype(ras);
} else {
@@ -436,6 +442,7 @@ int ras_mce_event_handler(struct trace_seq *s,
rc = parse_amd_k8_event(ras, &e);
break;
case CPU_NAPLES:
+ case CPU_DHYANA:
rc = parse_amd_smca_event(ras, &e);
break;
default: /* All other CPU types are Intel */
diff --git a/ras-mce-handler.h b/ras-mce-handler.h
index 8aaecd1..94395eb 100644
--- a/ras-mce-handler.h
+++ b/ras-mce-handler.h
@@ -51,6 +51,7 @@ enum cputype {
CPU_KNIGHTS_MILL,
CPU_SKYLAKE_XEON,
CPU_NAPLES,
+ CPU_DHYANA,
};
struct mce_event {
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] ras-mce-handler: Add support for Hygon Dhyana family 18h processor
2019-05-23 13:00 [PATCH] ras-mce-handler: Add support for Hygon Dhyana family 18h processor Pu Wen
@ 2019-06-14 2:18 ` Wen Pu
2019-06-24 12:41 ` Mauro Carvalho Chehab
0 siblings, 1 reply; 3+ messages in thread
From: Wen Pu @ 2019-06-14 2:18 UTC (permalink / raw)
To: mchehab; +Cc: linux-edac
Friendly ping...
On 2019/5/23 21:00, Pu Wen wrote:
> The Hygon Dhyana family 18h processor is derived from AMD family 17h.
> The Hygon Dhyana support to Linux is already accepted upstream[1].
>
> Add Hygon Dhyana support to mce handler of rasdaemon in order to handle
> MCE events on Hygon Dhyana platforms.
>
> Reference:
> [1] https://git.kernel.org/tip/fec98069fb72fb656304a3e52265e0c2fc9adf87
>
> Signed-off-by: Pu Wen <puwen@hygon.cn>
> ---
> ras-mce-handler.c | 9 ++++++++-
> ras-mce-handler.h | 1 +
> 2 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/ras-mce-handler.c b/ras-mce-handler.c
> index c11d489..eb548c6 100644
> --- a/ras-mce-handler.c
> +++ b/ras-mce-handler.c
> @@ -55,7 +55,8 @@ static char *cputype_name[] = {
> [CPU_KNIGHTS_LANDING] = "Knights Landing",
> [CPU_KNIGHTS_MILL] = "Knights Mill",
> [CPU_SKYLAKE_XEON] = "Skylake server",
> - [CPU_NAPLES] = "AMD Family 17h Zen1"
> + [CPU_NAPLES] = "AMD Family 17h Zen1",
> + [CPU_DHYANA] = "Hygon Family 18h Moksha"
> };
>
> static enum cputype select_intel_cputype(struct ras_events *ras)
> @@ -200,6 +201,11 @@ static int detect_cpu(struct ras_events *ras)
> ret = EINVAL;
> }
> goto ret;
> + } else if (!strcmp(mce->vendor,"HygonGenuine")) {
> + if (mce->family == 24) {
> + mce->cputype = CPU_DHYANA;
> + }
> + goto ret;
> } else if (!strcmp(mce->vendor,"GenuineIntel")) {
> mce->cputype = select_intel_cputype(ras);
> } else {
> @@ -436,6 +442,7 @@ int ras_mce_event_handler(struct trace_seq *s,
> rc = parse_amd_k8_event(ras, &e);
> break;
> case CPU_NAPLES:
> + case CPU_DHYANA:
> rc = parse_amd_smca_event(ras, &e);
> break;
> default: /* All other CPU types are Intel */
> diff --git a/ras-mce-handler.h b/ras-mce-handler.h
> index 8aaecd1..94395eb 100644
> --- a/ras-mce-handler.h
> +++ b/ras-mce-handler.h
> @@ -51,6 +51,7 @@ enum cputype {
> CPU_KNIGHTS_MILL,
> CPU_SKYLAKE_XEON,
> CPU_NAPLES,
> + CPU_DHYANA,
> };
>
> struct mce_event {
>
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] ras-mce-handler: Add support for Hygon Dhyana family 18h processor
2019-06-14 2:18 ` Wen Pu
@ 2019-06-24 12:41 ` Mauro Carvalho Chehab
0 siblings, 0 replies; 3+ messages in thread
From: Mauro Carvalho Chehab @ 2019-06-24 12:41 UTC (permalink / raw)
To: Wen Pu; +Cc: linux-edac
Em Fri, 14 Jun 2019 02:18:10 +0000
Wen Pu <puwen@hygon.cn> escreveu:
> Friendly ping...
>
> On 2019/5/23 21:00, Pu Wen wrote:
> > The Hygon Dhyana family 18h processor is derived from AMD family 17h.
> > The Hygon Dhyana support to Linux is already accepted upstream[1].
> >
> > Add Hygon Dhyana support to mce handler of rasdaemon in order to handle
> > MCE events on Hygon Dhyana platforms.
Applied, thanks!
> >
> > Reference:
> > [1] https://git.kernel.org/tip/fec98069fb72fb656304a3e52265e0c2fc9adf87
> >
> > Signed-off-by: Pu Wen <puwen@hygon.cn>
> > ---
> > ras-mce-handler.c | 9 ++++++++-
> > ras-mce-handler.h | 1 +
> > 2 files changed, 9 insertions(+), 1 deletion(-)
> >
> > diff --git a/ras-mce-handler.c b/ras-mce-handler.c
> > index c11d489..eb548c6 100644
> > --- a/ras-mce-handler.c
> > +++ b/ras-mce-handler.c
> > @@ -55,7 +55,8 @@ static char *cputype_name[] = {
> > [CPU_KNIGHTS_LANDING] = "Knights Landing",
> > [CPU_KNIGHTS_MILL] = "Knights Mill",
> > [CPU_SKYLAKE_XEON] = "Skylake server",
> > - [CPU_NAPLES] = "AMD Family 17h Zen1"
> > + [CPU_NAPLES] = "AMD Family 17h Zen1",
> > + [CPU_DHYANA] = "Hygon Family 18h Moksha"
> > };
> >
> > static enum cputype select_intel_cputype(struct ras_events *ras)
> > @@ -200,6 +201,11 @@ static int detect_cpu(struct ras_events *ras)
> > ret = EINVAL;
> > }
> > goto ret;
> > + } else if (!strcmp(mce->vendor,"HygonGenuine")) {
> > + if (mce->family == 24) {
> > + mce->cputype = CPU_DHYANA;
> > + }
> > + goto ret;
> > } else if (!strcmp(mce->vendor,"GenuineIntel")) {
> > mce->cputype = select_intel_cputype(ras);
> > } else {
> > @@ -436,6 +442,7 @@ int ras_mce_event_handler(struct trace_seq *s,
> > rc = parse_amd_k8_event(ras, &e);
> > break;
> > case CPU_NAPLES:
> > + case CPU_DHYANA:
> > rc = parse_amd_smca_event(ras, &e);
> > break;
> > default: /* All other CPU types are Intel */
> > diff --git a/ras-mce-handler.h b/ras-mce-handler.h
> > index 8aaecd1..94395eb 100644
> > --- a/ras-mce-handler.h
> > +++ b/ras-mce-handler.h
> > @@ -51,6 +51,7 @@ enum cputype {
> > CPU_KNIGHTS_MILL,
> > CPU_SKYLAKE_XEON,
> > CPU_NAPLES,
> > + CPU_DHYANA,
> > };
> >
> > struct mce_event {
> >
Thanks,
Mauro
^ permalink raw reply [flat|nested] 3+ messages in thread
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2019-05-23 13:00 [PATCH] ras-mce-handler: Add support for Hygon Dhyana family 18h processor Pu Wen
2019-06-14 2:18 ` Wen Pu
2019-06-24 12:41 ` Mauro Carvalho Chehab
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