* Re: [PATCH] riscv: move sifive_l2_cache.c to drivers/misc
[not found] ` <20190807152215.GA26690@kroah.com>
@ 2019-08-07 15:24 ` Christoph Hellwig
2019-08-07 15:40 ` Paul Walmsley
0 siblings, 1 reply; 4+ messages in thread
From: Christoph Hellwig @ 2019-08-07 15:24 UTC (permalink / raw)
To: Greg KH
Cc: Christoph Hellwig, palmer, arnd, linux-riscv, linux-kernel,
linux-edac, mchehab, james.morse
On Wed, Aug 07, 2019 at 05:22:15PM +0200, Greg KH wrote:
> > Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
> > Signed-off-by: Christoph Hellwig <hch@lst.de>
> > ---
> > arch/riscv/mm/Makefile | 1 -
> > drivers/misc/Makefile | 1 +
> > {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0
> > 3 files changed, 1 insertion(+), 1 deletion(-)
> > rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%)
>
> Why isn't this in drivers/edac/ ?
> why is this a misc driver? Seems like it should sit next to the edac
> stuff.
No idea. EDAC maintainers, would you object to taking what is
currently in arch/riscv/mm//sifive_l2_cache.c to drivers/edac/ ?
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] riscv: move sifive_l2_cache.c to drivers/misc
2019-08-07 15:24 ` [PATCH] riscv: move sifive_l2_cache.c to drivers/misc Christoph Hellwig
@ 2019-08-07 15:40 ` Paul Walmsley
2019-08-08 7:50 ` Christoph Hellwig
0 siblings, 1 reply; 4+ messages in thread
From: Paul Walmsley @ 2019-08-07 15:40 UTC (permalink / raw)
To: Christoph Hellwig
Cc: Greg KH, arnd, palmer, linux-kernel, james.morse, linux-riscv,
mchehab, linux-edac
On Wed, 7 Aug 2019, Christoph Hellwig wrote:
> On Wed, Aug 07, 2019 at 05:22:15PM +0200, Greg KH wrote:
> > > Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
> > > Signed-off-by: Christoph Hellwig <hch@lst.de>
> > > ---
> > > arch/riscv/mm/Makefile | 1 -
> > > drivers/misc/Makefile | 1 +
> > > {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0
> > > 3 files changed, 1 insertion(+), 1 deletion(-)
> > > rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%)
> >
> > Why isn't this in drivers/edac/ ?
> > why is this a misc driver? Seems like it should sit next to the edac
> > stuff.
>
> No idea. EDAC maintainers, would you object to taking what is
> currently in arch/riscv/mm//sifive_l2_cache.c to drivers/edac/ ?
If this driver is moved out of arch/riscv/mm, it should ideally go into
some sort of common L2 cache controller driver directory, along
with other L2 cache controller drivers like arch/arm/mm/*l2c*.
Like many L2 cache controllers, this controller also supports cache
flushing operations and SoC-specific way operations. We just don't use
those on RISC-V - yet.
- Paul
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] riscv: move sifive_l2_cache.c to drivers/misc
2019-08-07 15:40 ` Paul Walmsley
@ 2019-08-08 7:50 ` Christoph Hellwig
2019-08-08 8:07 ` Arnd Bergmann
0 siblings, 1 reply; 4+ messages in thread
From: Christoph Hellwig @ 2019-08-08 7:50 UTC (permalink / raw)
To: Paul Walmsley
Cc: Christoph Hellwig, Greg KH, arnd, palmer, linux-kernel,
james.morse, linux-riscv, mchehab, linux-edac
On Wed, Aug 07, 2019 at 08:40:58AM -0700, Paul Walmsley wrote:
> On Wed, 7 Aug 2019, Christoph Hellwig wrote:
>
> > On Wed, Aug 07, 2019 at 05:22:15PM +0200, Greg KH wrote:
> > > > Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
> > > > Signed-off-by: Christoph Hellwig <hch@lst.de>
> > > > ---
> > > > arch/riscv/mm/Makefile | 1 -
> > > > drivers/misc/Makefile | 1 +
> > > > {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0
> > > > 3 files changed, 1 insertion(+), 1 deletion(-)
> > > > rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%)
> > >
> > > Why isn't this in drivers/edac/ ?
> > > why is this a misc driver? Seems like it should sit next to the edac
> > > stuff.
> >
> > No idea. EDAC maintainers, would you object to taking what is
> > currently in arch/riscv/mm//sifive_l2_cache.c to drivers/edac/ ?
>
> If this driver is moved out of arch/riscv/mm, it should ideally go into
> some sort of common L2 cache controller driver directory, along
> with other L2 cache controller drivers like arch/arm/mm/*l2c*.
>
> Like many L2 cache controllers, this controller also supports cache
> flushing operations and SoC-specific way operations. We just don't use
> those on RISC-V - yet.
Well, another reason to not have it under arch/riscv/ as it is a SOC
specific driver, which we all have somewhere else, just like arm64
and new arm ports do. And especially not unconditionally built.
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] riscv: move sifive_l2_cache.c to drivers/misc
2019-08-08 7:50 ` Christoph Hellwig
@ 2019-08-08 8:07 ` Arnd Bergmann
0 siblings, 0 replies; 4+ messages in thread
From: Arnd Bergmann @ 2019-08-08 8:07 UTC (permalink / raw)
To: Christoph Hellwig
Cc: Paul Walmsley, Greg KH, Palmer Dabbelt,
Linux Kernel Mailing List, James Morse, linux-riscv,
Mauro Carvalho Chehab, linux-edac
On Thu, Aug 8, 2019 at 9:50 AM Christoph Hellwig <hch@lst.de> wrote:
> On Wed, Aug 07, 2019 at 08:40:58AM -0700, Paul Walmsley wrote:
> > On Wed, 7 Aug 2019, Christoph Hellwig wrote:
> > > On Wed, Aug 07, 2019 at 05:22:15PM +0200, Greg KH wrote:
> > > > > Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
> > > > > Signed-off-by: Christoph Hellwig <hch@lst.de>
> > > > > ---
> > > > > arch/riscv/mm/Makefile | 1 -
> > > > > drivers/misc/Makefile | 1 +
> > > > > {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0
> > > > > 3 files changed, 1 insertion(+), 1 deletion(-)
> > > > > rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%)
> > > >
> > > > Why isn't this in drivers/edac/ ?
> > > > why is this a misc driver? Seems like it should sit next to the edac
> > > > stuff.
> > >
> > > No idea. EDAC maintainers, would you object to taking what is
> > > currently in arch/riscv/mm//sifive_l2_cache.c to drivers/edac/ ?
> >
> > If this driver is moved out of arch/riscv/mm, it should ideally go into
> > some sort of common L2 cache controller driver directory, along
> > with other L2 cache controller drivers like arch/arm/mm/*l2c*.
> >
> > Like many L2 cache controllers, this controller also supports cache
> > flushing operations and SoC-specific way operations. We just don't use
> > those on RISC-V - yet.
>
> Well, another reason to not have it under arch/riscv/ as it is a SOC
> specific driver, which we all have somewhere else, just like arm64
> and new arm ports do. And especially not unconditionally built.
soc specific drivers that don't have their own subsystem can
go into drivers/soc/$VENDOR/.
For this driver, I would also think that the edac subsystem is the
best fit. Right now, the driver is split in two halves: there
is drivers/edac/sifive_edac.c and arch/riscv/mm/sifive_l2_cache.c,
with neither of those working without the other.
Moving both into a single file would seem to allow simplifying
it as a proper 'platform_driver', which the drivers/edac side today
is not (it just registers a platform device in its module_init call).
Arnd
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2019-08-08 8:07 UTC | newest]
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[not found] ` <20190807152215.GA26690@kroah.com>
2019-08-07 15:24 ` [PATCH] riscv: move sifive_l2_cache.c to drivers/misc Christoph Hellwig
2019-08-07 15:40 ` Paul Walmsley
2019-08-08 7:50 ` Christoph Hellwig
2019-08-08 8:07 ` Arnd Bergmann
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