From: Sascha Hauer <s.hauer@pengutronix.de>
To: linux-edac@vger.kernel.org
Cc: Borislav Petkov <bp@alien8.de>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Tony Luck <tony.luck@intel.com>,
James Morse <james.morse@arm.com>,
Robert Richter <rrichter@marvell.com>,
York Sun <york.sun@nxp.com>,
kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>
Subject: [PATCH v2 0/3] Add L1 and L2 error detection for A53 and A57
Date: Tue, 13 Oct 2020 14:50:30 +0200 [thread overview]
Message-ID: <20201013125033.4749-1-s.hauer@pengutronix.de> (raw)
This driver is based on an earlier version from York Sun which can
be found here: https://lkml.org/lkml/2018/3/14/1203.
At that time the conclusion was that this driver is not suitable for
mainline as it used IMPLEMENTATION DEFINED CPU registers and also
NXP specific SMC calls. All this was used for the error injection only,
for error reporting it is not needed.
This is another try to get this driver to mainline. All error injection
code has been removed (though it has initially been used to test this
driver on an i.MX8 SoC), what's left is unfortunately not testable, but
also doesn't contain none of the doubtful code anymore.
Changes since v1:
- Split dt-binding into separate patch
- Sort local function variables in reverse-xmas tree order
- drop unnecessary comparison and make variable bool
Sascha Hauer (2):
dt-bindings: edac: Add binding for L1/L2 error detection for Cortex
A53/57
drivers/edac: Add L1 and L2 error detection for A53 and A57
York Sun (1):
arm64: dts: ls104x: Add L1/L2 cache edac node
.../bindings/edac/arm,cortex-a5x-edac.yaml | 32 +++
.../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 5 +
.../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 5 +
drivers/edac/Kconfig | 6 +
drivers/edac/Makefile | 1 +
drivers/edac/cortex_arm64_l1_l2.c | 208 ++++++++++++++++++
6 files changed, 257 insertions(+)
create mode 100644 Documentation/devicetree/bindings/edac/arm,cortex-a5x-edac.yaml
create mode 100644 drivers/edac/cortex_arm64_l1_l2.c
--
2.28.0
next reply other threads:[~2020-10-13 12:50 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-13 12:50 Sascha Hauer [this message]
2020-10-13 12:50 ` [PATCH 1/3] dt-bindings: edac: Add binding for L1/L2 error detection for Cortex A53/57 Sascha Hauer
2020-10-14 13:25 ` Rob Herring
2020-10-13 12:50 ` [PATCH 2/3] drivers/edac: Add L1 and L2 error detection for A53 and A57 Sascha Hauer
2020-11-06 19:34 ` James Morse
2020-10-13 12:50 ` [PATCH 3/3] arm64: dts: ls104x: Add L1/L2 cache edac node Sascha Hauer
2020-10-14 13:25 ` [PATCH v2 0/3] Add L1 and L2 error detection for A53 and A57 Rob Herring
2020-10-14 14:04 ` Sascha Hauer
2020-10-14 15:17 ` Rob Herring
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