From: Sascha Hauer <s.hauer@pengutronix.de>
To: Rob Herring <robh@kernel.org>
Cc: linux-edac@vger.kernel.org, Borislav Petkov <bp@alien8.de>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Tony Luck <tony.luck@intel.com>,
James Morse <james.morse@arm.com>,
Robert Richter <rrichter@marvell.com>,
York Sun <york.sun@nxp.com>,
kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v2 0/3] Add L1 and L2 error detection for A53 and A57
Date: Wed, 14 Oct 2020 16:04:29 +0200 [thread overview]
Message-ID: <20201014140429.GE13710@pengutronix.de> (raw)
In-Reply-To: <20201014132511.GA1517487@bogus>
On Wed, Oct 14, 2020 at 08:25:11AM -0500, Rob Herring wrote:
> On Tue, Oct 13, 2020 at 02:50:30PM +0200, Sascha Hauer wrote:
> > This driver is based on an earlier version from York Sun which can
> > be found here: https://lkml.org/lkml/2018/3/14/1203.
> >
> > At that time the conclusion was that this driver is not suitable for
> > mainline as it used IMPLEMENTATION DEFINED CPU registers and also
> > NXP specific SMC calls. All this was used for the error injection only,
> > for error reporting it is not needed.
>
> Have you looked at Amazon's version:
> http://lore.kernel.org/r/20200510151310.17372-2-hhhawa@amazon.com
No, I was not aware of that driver. It's basically the same driver, but
limited to a single SoC. Looks like at least some things are better in
that driver, read_sysreg_s(ARM_CA57_L2MERRSR_EL1) reads better than my
open coded variant.
>
> Which is an A57 EDAC driver. Looks like it never got upstream though,
> but it's not clear why.
>
> You'll note that it doesn't have a virtual DT node either.
Testing the SoC type in an initcall looks odd to me. Wouldn't a
dedicated node be preferred?
Sascha
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next prev parent reply other threads:[~2020-10-14 14:04 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-13 12:50 [PATCH v2 0/3] Add L1 and L2 error detection for A53 and A57 Sascha Hauer
2020-10-13 12:50 ` [PATCH 1/3] dt-bindings: edac: Add binding for L1/L2 error detection for Cortex A53/57 Sascha Hauer
2020-10-14 13:25 ` Rob Herring
2020-10-13 12:50 ` [PATCH 2/3] drivers/edac: Add L1 and L2 error detection for A53 and A57 Sascha Hauer
2020-11-06 19:34 ` James Morse
2020-10-13 12:50 ` [PATCH 3/3] arm64: dts: ls104x: Add L1/L2 cache edac node Sascha Hauer
2020-10-14 13:25 ` [PATCH v2 0/3] Add L1 and L2 error detection for A53 and A57 Rob Herring
2020-10-14 14:04 ` Sascha Hauer [this message]
2020-10-14 15:17 ` Rob Herring
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