From: Sascha Hauer <s.hauer@pengutronix.de>
To: linux-edac@vger.kernel.org
Cc: Borislav Petkov <bp@alien8.de>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Tony Luck <tony.luck@intel.com>,
James Morse <james.morse@arm.com>,
Robert Richter <rrichter@marvell.com>,
York Sun <york.sun@nxp.com>,
kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>
Subject: [PATCH 3/3] arm64: dts: ls104x: Add L1/L2 cache edac node
Date: Tue, 13 Oct 2020 14:50:33 +0200 [thread overview]
Message-ID: <20201013125033.4749-4-s.hauer@pengutronix.de> (raw)
In-Reply-To: <20201013125033.4749-1-s.hauer@pengutronix.de>
From: York Sun <york.sun@nxp.com>
The Cortex A53/A57 cores on the Layerscape LS104x SoCs support EDAC
for the L1/L2 caches. Add the corresponding nodes for it.
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 5 +++++
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 5 +++++
2 files changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 5c2e370f6316..76cc62b02494 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -935,6 +935,11 @@ optee {
};
};
+ edac-a53 {
+ compatible = "arm,cortex-a53-edac";
+ cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
};
#include "qoriq-qman-portals.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 0246d975a206..ed35211c9b35 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -895,6 +895,11 @@ optee {
method = "smc";
};
};
+
+ edac-a57 {
+ compatible = "arm,cortex-a57-edac";
+ cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
};
#include "qoriq-qman-portals.dtsi"
--
2.28.0
next prev parent reply other threads:[~2020-10-13 12:50 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-13 12:50 [PATCH v2 0/3] Add L1 and L2 error detection for A53 and A57 Sascha Hauer
2020-10-13 12:50 ` [PATCH 1/3] dt-bindings: edac: Add binding for L1/L2 error detection for Cortex A53/57 Sascha Hauer
2020-10-14 13:25 ` Rob Herring
2020-10-13 12:50 ` [PATCH 2/3] drivers/edac: Add L1 and L2 error detection for A53 and A57 Sascha Hauer
2020-11-06 19:34 ` James Morse
2020-10-13 12:50 ` Sascha Hauer [this message]
2020-10-14 13:25 ` [PATCH v2 0/3] " Rob Herring
2020-10-14 14:04 ` Sascha Hauer
2020-10-14 15:17 ` Rob Herring
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