From: matthew.gerlach@linux.intel.com
To: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com,
basheer.ahmed.muddebihal@intel.com, trix@redhat.com,
mdf@kernel.org, linux-fpga@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
tianfei.zhang@intel.com, corbet@lwn.net,
gregkh@linuxfoundation.org, linux-serial@vger.kernel.org,
jirislaby@kernel.org, geert+renesas@glider.be,
andriy.shevchenko@linux.intel.com,
niklas.soderlund+renesas@ragnatech.se, phil.edworthy@renesas.com,
macro@orcam.me.uk, johan@kernel.org, lukas@wunner.de
Cc: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Subject: [PATCH v1 1/5] Documentation: fpga: dfl: Add documentation for DFHv1
Date: Tue, 6 Sep 2022 12:04:22 -0700 [thread overview]
Message-ID: <20220906190426.3139760-2-matthew.gerlach@linux.intel.com> (raw)
In-Reply-To: <20220906190426.3139760-1-matthew.gerlach@linux.intel.com>
From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Add documentation describing the extentions provided by Version
1 of the Device Feature Header (DFHv1).
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
Documentation/fpga/dfl.rst | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst
index 15b670926084..31699b89781e 100644
--- a/Documentation/fpga/dfl.rst
+++ b/Documentation/fpga/dfl.rst
@@ -561,6 +561,30 @@ new DFL feature via UIO direct access, its feature id should be added to the
driver's id_table.
+Extending the Device Feature Header - DFHv1
+===========================================
+The current 8 bytes of the Device Feature Header, hereafter referred to as
+to DFHv0, provide very little opportunity for the hardware to describe itself
+to software. Version 1 of the Device Feature Header (DFHv1) is being introduced
+to provide increased flexibility and extensibility to hardware designs using
+Device Feature Lists. The list below describes some of the goals behind the
+changes in DFHv1:
+
+* Provide a standardized mechanism for features to describe
+ parameters/capabilities to software.
+* Standardize the use of a GUID for all DFHv1 types.
+* Decouple the location of the DFH from the register space of the feature itself.
+
+Modeled after PCI Capabilities, DFHv1 Parameters provide a mechanism to associate
+a list of parameter values to a particular feature.
+
+With DFHv0, not all features types contained a GUID. DFHv1 makes the GUILD standard
+across all types.
+
+With DFHv0, the register map of a given feature is located immediately following
+the DFHv0 in the memory space. With DFHv1, the location of the feature register
+map can be specified as an offset to the DFHv1 or as an absolute address.
+
Open discussion
===============
FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration
--
2.25.1
next prev parent reply other threads:[~2022-09-06 19:06 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-06 19:04 [PATCH v1 0/5] Enhance definition of DFH and use enhancements for uart driver matthew.gerlach
2022-09-06 19:04 ` matthew.gerlach [this message]
2022-09-06 20:08 ` [PATCH v1 1/5] Documentation: fpga: dfl: Add documentation for DFHv1 Andy Shevchenko
2022-09-07 19:15 ` matthew.gerlach
2022-09-11 9:57 ` Xu Yilun
2022-09-11 16:06 ` matthew.gerlach
2022-09-06 19:04 ` [PATCH v1 2/5] fpga: dfl: Move the DFH definitions matthew.gerlach
2022-09-06 20:07 ` Andy Shevchenko
2022-09-07 21:01 ` matthew.gerlach
2022-09-07 5:08 ` Greg KH
2022-09-11 15:40 ` matthew.gerlach
2022-09-11 17:54 ` Geert Uytterhoeven
2022-09-11 8:04 ` Xu Yilun
2022-09-11 16:13 ` matthew.gerlach
2022-09-06 19:04 ` [PATCH v1 3/5] fpga: dfl: Add DFHv1 Register Definitions matthew.gerlach
2022-09-11 8:27 ` Xu Yilun
2022-09-11 16:21 ` matthew.gerlach
2022-09-06 19:04 ` [PATCH v1 4/5] fpga: dfl: add generic support for MSIX interrupts matthew.gerlach
2022-09-06 20:15 ` Andy Shevchenko
2022-09-07 21:37 ` matthew.gerlach
2022-09-08 11:04 ` Andy Shevchenko
2022-09-08 17:34 ` matthew.gerlach
2022-09-08 17:51 ` Andy Shevchenko
2022-09-08 19:28 ` Geert Uytterhoeven
2022-09-08 20:21 ` matthew.gerlach
2022-09-11 9:06 ` Xu Yilun
2022-09-06 19:04 ` [PATCH v1 5/5] tty: serial: 8250: add DFL bus driver for Altera 16550 matthew.gerlach
2022-09-06 20:24 ` Andy Shevchenko
2022-09-08 18:27 ` matthew.gerlach
2022-09-08 21:16 ` Andy Shevchenko
2022-09-11 15:56 ` matthew.gerlach
2022-09-12 10:54 ` Andy Shevchenko
2022-09-11 9:41 ` Xu Yilun
2022-09-12 15:29 ` matthew.gerlach
2022-09-13 2:48 ` Xu Yilun
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