From: matthew.gerlach@linux.intel.com
To: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com,
basheer.ahmed.muddebihal@intel.com, trix@redhat.com,
mdf@kernel.org, linux-fpga@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
tianfei.zhang@intel.com, corbet@lwn.net,
gregkh@linuxfoundation.org, linux-serial@vger.kernel.org,
jirislaby@kernel.org, geert+renesas@glider.be,
andriy.shevchenko@linux.intel.com,
niklas.soderlund+renesas@ragnatech.se, phil.edworthy@renesas.com,
macro@orcam.me.uk, johan@kernel.org, lukas@wunner.de
Cc: Basheer Ahmed Muddebihal
<basheer.ahmed.muddebihal@linux.intel.com>,
Matthew Gerlach <matthew.gerlach@linux.intel.com>
Subject: [PATCH v1 3/5] fpga: dfl: Add DFHv1 Register Definitions
Date: Tue, 6 Sep 2022 12:04:24 -0700 [thread overview]
Message-ID: <20220906190426.3139760-4-matthew.gerlach@linux.intel.com> (raw)
In-Reply-To: <20220906190426.3139760-1-matthew.gerlach@linux.intel.com>
From: Basheer Ahmed Muddebihal <basheer.ahmed.muddebihal@linux.intel.com>
This patch adds the definitions for DFHv1 header and related register
bitfields.
Signed-off-by: Basheer Ahmed Muddebihal <basheer.ahmed.muddebihal@linux.intel.com>
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
include/linux/dfl.h | 37 +++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/include/linux/dfl.h b/include/linux/dfl.h
index b5accdcfa368..61bcf20c1bc8 100644
--- a/include/linux/dfl.h
+++ b/include/linux/dfl.h
@@ -23,6 +23,16 @@
#define GUID_H 0x10
#define NEXT_AFU 0x18
+/*
+ * DFHv1 Register Offset definitons
+ * In DHFv1, DFH + GUID + CSR_START + CSR_SIZE_GROUP + PARAM_HDR + PARAM_DATA
+ * as common header registers
+ */
+#define DFHv1_CSR_ADDR 0x18 /* CSR Register start address */
+#define DFHv1_CSR_SIZE_GRP 0x20 /* Size of Reg Block and Group/tag */
+#define DFHv1_PARAM_HDR 0x28 /* Optional First Param header */
+#define DFHv1_PARAM_DATA 0x8 /* Offset of Param data from Param header */
+
#define DFH_SIZE 0x8
/* Device Feature Header Register Bitfield */
@@ -30,8 +40,35 @@
#define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */
#define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */
#define DFH_EOL BIT_ULL(40) /* End of list */
+#define DFH_VERSION GENMASK_ULL(59, 52) /* DFH version */
#define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */
+/*
+ * CSR Rel Bit, 1'b0 = relative (offset from feature DFH start),
+ * 1'b1 = absolute (ARM or other non-PCIe use)
+ */
+#define DFHv1_CSR_ADDR_REL BIT_ULL(0)
+
+/*
+ * CSR Header Register Bit Definitions
+ */
+#define DFHv1_CSR_ADDR_MASK GENMASK_ULL(63, 1) /* 63:1 of CSR address */
+
+/*
+ * CSR SIZE Goup Register Bit Definitions
+ */
+#define DFHv1_CSR_SIZE_GRP_INSTANCE_ID GENMASK_ULL(15, 0) /* Enumeration instantiated IP */
+#define DFHv1_CSR_SIZE_GRP_GROUPING_ID GENMASK_ULL(30, 16) /* Group Features/interfaces */
+#define DFHv1_CSR_SIZE_GRP_HAS_PARAMS BIT_ULL(31) /* Presence of Parameters */
+#define DFHv1_CSR_SIZE_GRP_SIZE GENMASK_ULL(63, 32) /* Size of CSR Block in bytes */
+
+/*
+ * PARAM Header Register Bit Definitions
+ */
+#define DFHv1_PARAM_HDR_ID GENMASK_ULL(15, 0) /* Id of this Param */
+#define DFHv1_PARAM_HDR_VERSION GENMASK_ULL(31, 16) /* Version Param */
+#define DFHv1_PARAM_HDR_NEXT_OFFSET GENMASK_ULL(63, 32) /* Offset of next Param */
+
/**
* enum dfl_id_type - define the DFL FIU types
*/
--
2.25.1
next prev parent reply other threads:[~2022-09-06 19:06 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-06 19:04 [PATCH v1 0/5] Enhance definition of DFH and use enhancements for uart driver matthew.gerlach
2022-09-06 19:04 ` [PATCH v1 1/5] Documentation: fpga: dfl: Add documentation for DFHv1 matthew.gerlach
2022-09-06 20:08 ` Andy Shevchenko
2022-09-07 19:15 ` matthew.gerlach
2022-09-11 9:57 ` Xu Yilun
2022-09-11 16:06 ` matthew.gerlach
2022-09-06 19:04 ` [PATCH v1 2/5] fpga: dfl: Move the DFH definitions matthew.gerlach
2022-09-06 20:07 ` Andy Shevchenko
2022-09-07 21:01 ` matthew.gerlach
2022-09-07 5:08 ` Greg KH
2022-09-11 15:40 ` matthew.gerlach
2022-09-11 17:54 ` Geert Uytterhoeven
2022-09-11 8:04 ` Xu Yilun
2022-09-11 16:13 ` matthew.gerlach
2022-09-06 19:04 ` matthew.gerlach [this message]
2022-09-11 8:27 ` [PATCH v1 3/5] fpga: dfl: Add DFHv1 Register Definitions Xu Yilun
2022-09-11 16:21 ` matthew.gerlach
2022-09-06 19:04 ` [PATCH v1 4/5] fpga: dfl: add generic support for MSIX interrupts matthew.gerlach
2022-09-06 20:15 ` Andy Shevchenko
2022-09-07 21:37 ` matthew.gerlach
2022-09-08 11:04 ` Andy Shevchenko
2022-09-08 17:34 ` matthew.gerlach
2022-09-08 17:51 ` Andy Shevchenko
2022-09-08 19:28 ` Geert Uytterhoeven
2022-09-08 20:21 ` matthew.gerlach
2022-09-11 9:06 ` Xu Yilun
2022-09-06 19:04 ` [PATCH v1 5/5] tty: serial: 8250: add DFL bus driver for Altera 16550 matthew.gerlach
2022-09-06 20:24 ` Andy Shevchenko
2022-09-08 18:27 ` matthew.gerlach
2022-09-08 21:16 ` Andy Shevchenko
2022-09-11 15:56 ` matthew.gerlach
2022-09-12 10:54 ` Andy Shevchenko
2022-09-11 9:41 ` Xu Yilun
2022-09-12 15:29 ` matthew.gerlach
2022-09-13 2:48 ` Xu Yilun
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