From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: matthew.gerlach@linux.intel.com
Cc: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com,
basheer.ahmed.muddebihal@intel.com, trix@redhat.com,
mdf@kernel.org, linux-fpga@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
tianfei.zhang@intel.com, corbet@lwn.net,
gregkh@linuxfoundation.org, linux-serial@vger.kernel.org,
jirislaby@kernel.org, geert+renesas@glider.be,
niklas.soderlund+renesas@ragnatech.se, phil.edworthy@renesas.com,
macro@orcam.me.uk, johan@kernel.org, lukas@wunner.de
Subject: Re: [PATCH v1 4/5] fpga: dfl: add generic support for MSIX interrupts
Date: Thu, 8 Sep 2022 14:04:12 +0300 [thread overview]
Message-ID: <YxnMLI17XvjN74DW@smile.fi.intel.com> (raw)
In-Reply-To: <alpine.DEB.2.22.394.2209071433320.3336870@rhweight-WRK1>
On Wed, Sep 07, 2022 at 02:37:32PM -0700, matthew.gerlach@linux.intel.com wrote:
> On Tue, 6 Sep 2022, Andy Shevchenko wrote:
> > On Tue, Sep 06, 2022 at 12:04:25PM -0700, matthew.gerlach@linux.intel.com wrote:
...
> > > + if (fid != FEATURE_ID_AFU && fid != PORT_FEATURE_ID_ERROR &&
> > > + fid != PORT_FEATURE_ID_UINT && fid != FME_FEATURE_ID_GLOBAL_ERR) {
> > > + v = readq(base);
> > > + v = FIELD_GET(DFH_VERSION, v);
> > > +
> > > + if (v == 1) {
> > > + v = readq(base + DFHv1_CSR_SIZE_GRP);
> >
> > I am already lost what v keeps...
> >
> > Perhaps
> >
> > v = readq(base);
> > switch (FIELD_GET(DFH_VERSION, v)) {
> > case 1:
> > ...
> > break;
> > }
>
> How about?
> if (FIELD_GET(DFH_VERSION, readq(base)) == 1) {
> ...
> }
This one tends to be expanded in the future, so I would keep it switch case.
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2022-09-08 11:06 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-06 19:04 [PATCH v1 0/5] Enhance definition of DFH and use enhancements for uart driver matthew.gerlach
2022-09-06 19:04 ` [PATCH v1 1/5] Documentation: fpga: dfl: Add documentation for DFHv1 matthew.gerlach
2022-09-06 20:08 ` Andy Shevchenko
2022-09-07 19:15 ` matthew.gerlach
2022-09-11 9:57 ` Xu Yilun
2022-09-11 16:06 ` matthew.gerlach
2022-09-06 19:04 ` [PATCH v1 2/5] fpga: dfl: Move the DFH definitions matthew.gerlach
2022-09-06 20:07 ` Andy Shevchenko
2022-09-07 21:01 ` matthew.gerlach
2022-09-07 5:08 ` Greg KH
2022-09-11 15:40 ` matthew.gerlach
2022-09-11 17:54 ` Geert Uytterhoeven
2022-09-11 8:04 ` Xu Yilun
2022-09-11 16:13 ` matthew.gerlach
2022-09-06 19:04 ` [PATCH v1 3/5] fpga: dfl: Add DFHv1 Register Definitions matthew.gerlach
2022-09-11 8:27 ` Xu Yilun
2022-09-11 16:21 ` matthew.gerlach
2022-09-06 19:04 ` [PATCH v1 4/5] fpga: dfl: add generic support for MSIX interrupts matthew.gerlach
2022-09-06 20:15 ` Andy Shevchenko
2022-09-07 21:37 ` matthew.gerlach
2022-09-08 11:04 ` Andy Shevchenko [this message]
2022-09-08 17:34 ` matthew.gerlach
2022-09-08 17:51 ` Andy Shevchenko
2022-09-08 19:28 ` Geert Uytterhoeven
2022-09-08 20:21 ` matthew.gerlach
2022-09-11 9:06 ` Xu Yilun
2022-09-06 19:04 ` [PATCH v1 5/5] tty: serial: 8250: add DFL bus driver for Altera 16550 matthew.gerlach
2022-09-06 20:24 ` Andy Shevchenko
2022-09-08 18:27 ` matthew.gerlach
2022-09-08 21:16 ` Andy Shevchenko
2022-09-11 15:56 ` matthew.gerlach
2022-09-12 10:54 ` Andy Shevchenko
2022-09-11 9:41 ` Xu Yilun
2022-09-12 15:29 ` matthew.gerlach
2022-09-13 2:48 ` Xu Yilun
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