[PATCH 0/4]Add afi config drivers support

[PATCH 0/4]Add afi config drivers support

[Nava kishore Manne]

Xilinx SoC platforms (Zynq and ZynqMP) connect the PS to the programmable
logic (PL) through the AXI port.This AXI port helps to establish the data
path between the PS and PL. In-order to establish the proper communication
data path between PS and PL the AXI port data path should be configured
with the proper Bus-width values and it will also handle the PS-PL reset
signals to reset the PL domain.

This patch series adds afi config drivers support to handle the PS-PL
resets and AXI port bus-width configurations.

Nava kishore Manne (4):
  firmware: xilinx: Add afi ioctl support
  bindings: fpga: Add binding doc for the zynqmp afi config driver
  bindings: firmware: Update binding doc for the zynqmp afi config node
  fpga: zynqmp: Add afi config driver

 .../firmware/xilinx/xlnx,zynqmp-firmware.yaml |   7 +
 .../bindings/fpga/xlnx,zynqmp-afi-fpga.yaml   | 100 +++++++++
 MAINTAINERS                                   |   6 +
 drivers/firmware/xilinx/zynqmp.c              |  14 ++
 drivers/fpga/Kconfig                          |  13 ++
 drivers/fpga/Makefile                         |   1 +
 drivers/fpga/zynqmp-afi.c                     | 211 ++++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h          |  36 +++
 8 files changed, 388 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
 create mode 100644 drivers/fpga/zynqmp-afi.c

-- 
2.25.1

[PATCH 1/4] firmware: xilinx: Add afi ioctl support

[Nava kishore Manne]

Adds afi ioctl to support dynamic PS-PL bus width settings.

Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
---
 drivers/firmware/xilinx/zynqmp.c     | 14 +++++++++++
 include/linux/firmware/xlnx-zynqmp.h | 36 ++++++++++++++++++++++++++++
 2 files changed, 50 insertions(+)

diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index d1f652802181..cbd84c96a66a 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -843,6 +843,20 @@ int zynqmp_pm_read_pggs(u32 index, u32 *value)
 }
 EXPORT_SYMBOL_GPL(zynqmp_pm_read_pggs);
 
+/**
+ * zynqmp_pm_afi() - PM API for setting the PS-PL bus width
+ * @config_id:	Register index value
+ * @bus_width:	Afi interface bus width value.
+ *
+ * Return:	Returns status, either success or error+reason
+ */
+int zynqmp_pm_afi(u32 config_id, u32 bus_width)
+{
+	return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_AFI,
+				   config_id, bus_width, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_afi);
+
 /**
  * zynqmp_pm_set_boot_health_status() - PM API for setting healthy boot status
  * @value:	Status value to be written
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 9f50dacbf7d6..7d0d98303acc 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -78,6 +78,16 @@
 #define EVENT_ERROR_PSM_ERR1	(0x28108000U)
 #define EVENT_ERROR_PSM_ERR2	(0x2810C000U)
 
+#define AFIFM_BUS_WIDTH_128_CONFIG_VAL	0x0U
+#define AFIFM_BUS_WIDTH_64_CONFIG_VAL	0x1U
+#define AFIFM_BUS_WIDTH_32_CONFIG_VAL	0x2U
+
+#define AFIFS_SS0_SS2_BUS_WIDTH_128_CONFIG_VAL	0x200U
+#define AFIFS_SS0_SS2_BUS_WIDTH_64_CONFIG_VAL	0x100U
+#define AFIFS_SS1_BUS_WIDTH_128_CONFIG_VAL	0x800U
+#define AFIFS_SS1_BUS_WIDTH_64_CONFIG_VAL	0x400U
+#define AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL	0x0U
+
 enum pm_api_cb_id {
 	PM_INIT_SUSPEND_CB = 30,
 	PM_ACKNOWLEDGE_CB = 31,
@@ -147,6 +157,7 @@ enum pm_ioctl_id {
 	IOCTL_READ_PGGS = 15,
 	/* Set healthy bit value */
 	IOCTL_SET_BOOT_HEALTH_STATUS = 17,
+	IOCTL_AFI = 18,
 	IOCTL_OSPI_MUX_SELECT = 21,
 	/* Register SGI to ATF */
 	IOCTL_REGISTER_SGI = 25,
@@ -155,6 +166,25 @@ enum pm_ioctl_id {
 	IOCTL_GET_FEATURE_CONFIG = 27,
 };
 
+enum pm_afi_config_id {
+	AFIFM0_RDCTRL = 0,
+	AFIFM0_WRCTRL = 1,
+	AFIFM1_RDCTRL = 2,
+	AFIFM1_WRCTRL = 3,
+	AFIFM2_RDCTRL = 4,
+	AFIFM2_WRCTRL = 5,
+	AFIFM3_RDCTRL = 6,
+	AFIFM3_WRCTRL = 7,
+	AFIFM4_RDCTRL = 8,
+	AFIFM4_WRCTRL = 9,
+	AFIFM5_RDCTRL = 10,
+	AFIFM5_WRCTRL = 11,
+	AFIFM6_RDCTRL = 12,
+	AFIFM6_WRCTRL = 13,
+	AFIFS = 14,
+	AFIFS_SS2 = 15,
+};
+
 enum pm_query_id {
 	PM_QID_INVALID = 0,
 	PM_QID_CLOCK_GET_NAME = 1,
@@ -475,6 +505,7 @@ int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
 int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value);
 int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload);
 int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset);
+int zynqmp_pm_afi(u32 config_id, u32 bus_width);
 #else
 static inline int zynqmp_pm_get_api_version(u32 *version)
 {
@@ -745,6 +776,11 @@ static inline int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset)
 {
 	return -ENODEV;
 }
+
+static inline int zynqmp_pm_afi(u32 config_id, u32 bus_width)
+{
+	return -ENODEV;
+}
 #endif
 
 #endif /* __FIRMWARE_ZYNQMP_H__ */
-- 
2.25.1

Re: [PATCH 1/4] firmware: xilinx: Add afi ioctl support

[Xu Yilun]

On 2022-08-24 at 09:25:39 +0530, Nava kishore Manne wrote:
> Adds afi ioctl to support dynamic PS-PL bus width settings.

Please also describe what is afi, PS, PL here, Patch #0 won't appear in
upstream tree finally.

Thanks,
Yilun

> 
> Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
> ---
>  drivers/firmware/xilinx/zynqmp.c     | 14 +++++++++++
>  include/linux/firmware/xlnx-zynqmp.h | 36 ++++++++++++++++++++++++++++
>  2 files changed, 50 insertions(+)
> 
> diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
> index d1f652802181..cbd84c96a66a 100644
> --- a/drivers/firmware/xilinx/zynqmp.c
> +++ b/drivers/firmware/xilinx/zynqmp.c
> @@ -843,6 +843,20 @@ int zynqmp_pm_read_pggs(u32 index, u32 *value)
>  }
>  EXPORT_SYMBOL_GPL(zynqmp_pm_read_pggs);
>  
> +/**
> + * zynqmp_pm_afi() - PM API for setting the PS-PL bus width
> + * @config_id:	Register index value
> + * @bus_width:	Afi interface bus width value.
> + *
> + * Return:	Returns status, either success or error+reason

I see other functions are also like this, but I still can't figure out
what values for success and what for error+reason.

Thanks,
Yilun

> + */
> +int zynqmp_pm_afi(u32 config_id, u32 bus_width)
> +{
> +	return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_AFI,
> +				   config_id, bus_width, NULL);
> +}
> +EXPORT_SYMBOL_GPL(zynqmp_pm_afi);
> +
>  /**
>   * zynqmp_pm_set_boot_health_status() - PM API for setting healthy boot status
>   * @value:	Status value to be written
> diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
> index 9f50dacbf7d6..7d0d98303acc 100644
> --- a/include/linux/firmware/xlnx-zynqmp.h
> +++ b/include/linux/firmware/xlnx-zynqmp.h
> @@ -78,6 +78,16 @@
>  #define EVENT_ERROR_PSM_ERR1	(0x28108000U)
>  #define EVENT_ERROR_PSM_ERR2	(0x2810C000U)
>  
> +#define AFIFM_BUS_WIDTH_128_CONFIG_VAL	0x0U
> +#define AFIFM_BUS_WIDTH_64_CONFIG_VAL	0x1U
> +#define AFIFM_BUS_WIDTH_32_CONFIG_VAL	0x2U
> +
> +#define AFIFS_SS0_SS2_BUS_WIDTH_128_CONFIG_VAL	0x200U
> +#define AFIFS_SS0_SS2_BUS_WIDTH_64_CONFIG_VAL	0x100U
> +#define AFIFS_SS1_BUS_WIDTH_128_CONFIG_VAL	0x800U
> +#define AFIFS_SS1_BUS_WIDTH_64_CONFIG_VAL	0x400U
> +#define AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL	0x0U
> +
>  enum pm_api_cb_id {
>  	PM_INIT_SUSPEND_CB = 30,
>  	PM_ACKNOWLEDGE_CB = 31,
> @@ -147,6 +157,7 @@ enum pm_ioctl_id {
>  	IOCTL_READ_PGGS = 15,
>  	/* Set healthy bit value */
>  	IOCTL_SET_BOOT_HEALTH_STATUS = 17,
> +	IOCTL_AFI = 18,
>  	IOCTL_OSPI_MUX_SELECT = 21,
>  	/* Register SGI to ATF */
>  	IOCTL_REGISTER_SGI = 25,
> @@ -155,6 +166,25 @@ enum pm_ioctl_id {
>  	IOCTL_GET_FEATURE_CONFIG = 27,
>  };
>  
> +enum pm_afi_config_id {
> +	AFIFM0_RDCTRL = 0,
> +	AFIFM0_WRCTRL = 1,
> +	AFIFM1_RDCTRL = 2,
> +	AFIFM1_WRCTRL = 3,
> +	AFIFM2_RDCTRL = 4,
> +	AFIFM2_WRCTRL = 5,
> +	AFIFM3_RDCTRL = 6,
> +	AFIFM3_WRCTRL = 7,
> +	AFIFM4_RDCTRL = 8,
> +	AFIFM4_WRCTRL = 9,
> +	AFIFM5_RDCTRL = 10,
> +	AFIFM5_WRCTRL = 11,
> +	AFIFM6_RDCTRL = 12,
> +	AFIFM6_WRCTRL = 13,
> +	AFIFS = 14,
> +	AFIFS_SS2 = 15,
> +};
> +
>  enum pm_query_id {
>  	PM_QID_INVALID = 0,
>  	PM_QID_CLOCK_GET_NAME = 1,
> @@ -475,6 +505,7 @@ int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
>  int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value);
>  int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload);
>  int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset);
> +int zynqmp_pm_afi(u32 config_id, u32 bus_width);
>  #else
>  static inline int zynqmp_pm_get_api_version(u32 *version)
>  {
> @@ -745,6 +776,11 @@ static inline int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset)
>  {
>  	return -ENODEV;
>  }
> +
> +static inline int zynqmp_pm_afi(u32 config_id, u32 bus_width)
> +{
> +	return -ENODEV;
> +}
>  #endif
>  
>  #endif /* __FIRMWARE_ZYNQMP_H__ */
> -- 
> 2.25.1
> 

RE: [PATCH 1/4] firmware: xilinx: Add afi ioctl support

[Manne, Nava kishore]

Hi Yilun,

	Please find my response inline. 

> -----Original Message-----
> From: Xu Yilun <yilun.xu@intel.com>
> Sent: Saturday, August 27, 2022 11:52 AM
> To: Manne, Nava kishore <nava.kishore.manne@amd.com>
> Cc: git (AMD-Xilinx) <git@amd.com>; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; michal.simek@xilinx.com;
> mdf@kernel.org; hao.wu@intel.com; trix@redhat.com;
> p.zabel@pengutronix.de; gregkh@linuxfoundation.org;
> ronak.jain@xilinx.com; rajan.vaja@xilinx.com;
> abhyuday.godhasara@xilinx.com; piyush.mehta@xilinx.com;
> lakshmi.sai.krishna.potthuri@xilinx.com; harsha.harsha@xilinx.com;
> linus.walleij@linaro.org; nava.manne@xilinx.com;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; linux-fpga@vger.kernel.org; yilun.xu@intel.com
> Subject: Re: [PATCH 1/4] firmware: xilinx: Add afi ioctl support
> 
> On 2022-08-24 at 09:25:39 +0530, Nava kishore Manne wrote:
> > Adds afi ioctl to support dynamic PS-PL bus width settings.
> 
> Please also describe what is afi, PS, PL here, Patch #0 won't appear in
> upstream tree finally.
> 

Agree, Will update the description in v2.

> Thanks,
> Yilun
> 
> >
> > Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
> > ---
> >  drivers/firmware/xilinx/zynqmp.c     | 14 +++++++++++
> >  include/linux/firmware/xlnx-zynqmp.h | 36
> > ++++++++++++++++++++++++++++
> >  2 files changed, 50 insertions(+)
> >
> > diff --git a/drivers/firmware/xilinx/zynqmp.c
> > b/drivers/firmware/xilinx/zynqmp.c
> > index d1f652802181..cbd84c96a66a 100644
> > --- a/drivers/firmware/xilinx/zynqmp.c
> > +++ b/drivers/firmware/xilinx/zynqmp.c
> > @@ -843,6 +843,20 @@ int zynqmp_pm_read_pggs(u32 index, u32
> *value)  }
> > EXPORT_SYMBOL_GPL(zynqmp_pm_read_pggs);
> >
> > +/**
> > + * zynqmp_pm_afi() - PM API for setting the PS-PL bus width
> > + * @config_id:	Register index value
> > + * @bus_width:	Afi interface bus width value.
> > + *
> > + * Return:	Returns status, either success or error+reason
> 
> I see other functions are also like this, but I still can't figure out what values
> for success and what for error+reason.
> 

Please find the relevant error info here:
https://elixir.bootlin.com/linux/v6.0-rc3/source/drivers/firmware/xilinx/zynqmp.c#L81

Regards,
Navakishore.

Re: [PATCH 1/4] firmware: xilinx: Add afi ioctl support

[Xu Yilun]

On 2022-08-30 at 09:25:47 +0000, Manne, Nava kishore wrote:
> Hi Yilun,
> 
> 	Please find my response inline. 
> 
> > -----Original Message-----
> > From: Xu Yilun <yilun.xu@intel.com>
> > Sent: Saturday, August 27, 2022 11:52 AM
> > To: Manne, Nava kishore <nava.kishore.manne@amd.com>
> > Cc: git (AMD-Xilinx) <git@amd.com>; robh+dt@kernel.org;
> > krzysztof.kozlowski+dt@linaro.org; michal.simek@xilinx.com;
> > mdf@kernel.org; hao.wu@intel.com; trix@redhat.com;
> > p.zabel@pengutronix.de; gregkh@linuxfoundation.org;
> > ronak.jain@xilinx.com; rajan.vaja@xilinx.com;
> > abhyuday.godhasara@xilinx.com; piyush.mehta@xilinx.com;
> > lakshmi.sai.krishna.potthuri@xilinx.com; harsha.harsha@xilinx.com;
> > linus.walleij@linaro.org; nava.manne@xilinx.com;
> > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> > kernel@vger.kernel.org; linux-fpga@vger.kernel.org; yilun.xu@intel.com
> > Subject: Re: [PATCH 1/4] firmware: xilinx: Add afi ioctl support
> > 
> > On 2022-08-24 at 09:25:39 +0530, Nava kishore Manne wrote:
> > > Adds afi ioctl to support dynamic PS-PL bus width settings.
> > 
> > Please also describe what is afi, PS, PL here, Patch #0 won't appear in
> > upstream tree finally.
> > 
> 
> Agree, Will update the description in v2.
> 
> > Thanks,
> > Yilun
> > 
> > >
> > > Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
> > > ---
> > >  drivers/firmware/xilinx/zynqmp.c     | 14 +++++++++++
> > >  include/linux/firmware/xlnx-zynqmp.h | 36
> > > ++++++++++++++++++++++++++++
> > >  2 files changed, 50 insertions(+)
> > >
> > > diff --git a/drivers/firmware/xilinx/zynqmp.c
> > > b/drivers/firmware/xilinx/zynqmp.c
> > > index d1f652802181..cbd84c96a66a 100644
> > > --- a/drivers/firmware/xilinx/zynqmp.c
> > > +++ b/drivers/firmware/xilinx/zynqmp.c
> > > @@ -843,6 +843,20 @@ int zynqmp_pm_read_pggs(u32 index, u32
> > *value)  }
> > > EXPORT_SYMBOL_GPL(zynqmp_pm_read_pggs);
> > >
> > > +/**
> > > + * zynqmp_pm_afi() - PM API for setting the PS-PL bus width
> > > + * @config_id:	Register index value
> > > + * @bus_width:	Afi interface bus width value.
> > > + *
> > > + * Return:	Returns status, either success or error+reason
> > 
> > I see other functions are also like this, but I still can't figure out what values
> > for success and what for error+reason.
> > 
> 
> Please find the relevant error info here:
> https://elixir.bootlin.com/linux/v6.0-rc3/source/drivers/firmware/xilinx/zynqmp.c#L81

The caller should at least know what value is success and what are
failures from the kernel doc, so they could write the code which call
your API.

Thanks,
Yilun

> 
> Regards,
> Navakishore.
> 

[PATCH 2/4] bindings: fpga: Add binding doc for the zynqmp afi config driver

[Nava kishore Manne]

Xilinx Zynq US+ MPSoC platform connect the PS to the programmable
logic(PL) through the AXI port. This AXI port helps to establish
the data path between the PS and PL. In-order to establish the proper
communication data path between PS and PL the AXI port data path should
be configured with the proper Bus-width values.

This patch adds the binding document for the zynqmp afi config driver
to handle the AXI port bus-width configurations and PS-PL resets.

Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
---
 .../bindings/fpga/xlnx,zynqmp-afi-fpga.yaml   | 100 ++++++++++++++++++
 1 file changed, 100 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml

diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
new file mode 100644
index 000000000000..faae4951e991
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-afi-fpga.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx ZynqMP AFI interface Manager.
+
+maintainers:
+  - Nava kishore Manne <nava.kishore.manne@amd.com>
+
+description: The Zynq UltraScale+ MPSoC Processing System core provides access
+  from PL masters to PS internal peripherals, and memory through AXI FIFO
+  interface(AFI)
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - xlnx,zynqmp-afi-fpga
+
+  resets:
+    description:
+      A list of phandles for resets listed in reset-names.
+
+  reset-names:
+    items:
+      - const: pl0-rst
+      - const: pl1-rst
+      - const: pl2-rst
+      - const: pl3-rst
+
+patternProperties:
+  "^xlnx,afifm[0-6]-rd-bus-width$":
+    description: bus width used to configure the afifm-rd interface.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [ 32, 64, 128 ]
+
+  "^xlnx,afifm[0-6]-wr-bus-width$":
+    description: bus width used to configure the afifm-wr interface.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [ 32, 64, 128 ]
+
+  "^xlnx,afifs-ss[0-2]-bus-width$":
+    description: bus width used to configure the afifs interface.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [ 32, 64, 128 ]
+
+required:
+  - compatible
+  - xlnx,afifm0-rd-bus-width
+  - xlnx,afifm1-rd-bus-width
+  - xlnx,afifm2-rd-bus-width
+  - xlnx,afifm3-rd-bus-width
+  - xlnx,afifm4-rd-bus-width
+  - xlnx,afifm5-rd-bus-width
+  - xlnx,afifm6-rd-bus-width
+  - xlnx,afifm0-wr-bus-width
+  - xlnx,afifm1-wr-bus-width
+  - xlnx,afifm2-wr-bus-width
+  - xlnx,afifm3-wr-bus-width
+  - xlnx,afifm4-wr-bus-width
+  - xlnx,afifm5-wr-bus-width
+  - xlnx,afifm6-wr-bus-width
+  - xlnx,afifs-ss0-bus-width
+  - xlnx,afifs-ss1-bus-width
+  - xlnx,afifs-ss2-bus-width
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
+    zynqmp-afi {
+      compatible = "xlnx,zynqmp-afi-fpga";
+      xlnx,afifm0-rd-bus-width = <32>;
+      xlnx,afifm1-rd-bus-width = <32>;
+      xlnx,afifm2-rd-bus-width = <64>;
+      xlnx,afifm3-rd-bus-width = <128>;
+      xlnx,afifm4-rd-bus-width = <32>;
+      xlnx,afifm5-rd-bus-width = <64>;
+      xlnx,afifm6-rd-bus-width = <128>;
+      xlnx,afifm0-wr-bus-width = <32>;
+      xlnx,afifm1-wr-bus-width = <32>;
+      xlnx,afifm2-wr-bus-width = <64>;
+      xlnx,afifm3-wr-bus-width = <128>;
+      xlnx,afifm4-wr-bus-width = <32>;
+      xlnx,afifm5-wr-bus-width = <64>;
+      xlnx,afifm6-wr-bus-width = <128>;
+      xlnx,afifs-ss0-bus-width = <64>;
+      xlnx,afifs-ss1-bus-width = <64>;
+      xlnx,afifs-ss2-bus-width = <64>;
+      resets = <&zynqmp_reset ZYNQMP_RESET_PS_PL0>,
+               <&zynqmp_reset ZYNQMP_RESET_PS_PL1>,
+               <&zynqmp_reset ZYNQMP_RESET_PS_PL2>,
+               <&zynqmp_reset ZYNQMP_RESET_PS_PL3>;
+      reset-names = "pl0-rst", "pl1-rst", "pl2-rst", "pl3-rst";
+    };
+
+...
-- 
2.25.1

Re: [PATCH 2/4] bindings: fpga: Add binding doc for the zynqmp afi config driver

[Krzysztof Kozlowski]

On 24/08/2022 06:55, Nava kishore Manne wrote:
> Xilinx Zynq US+ MPSoC platform connect the PS to the programmable
> logic(PL) through the AXI port. This AXI port helps to establish

Use subject prefixes matching the subsystem (git log --oneline -- ...).

> the data path between the PS and PL. In-order to establish the proper
> communication data path between PS and PL the AXI port data path should
> be configured with the proper Bus-width values.
> 
> This patch adds the binding document for the zynqmp afi config driver
> to handle the AXI port bus-width configurations and PS-PL resets.

Do not use "This commit/patch".
https://elixir.bootlin.com/linux/v5.17.1/source/Documentation/process/submitting-patches.rst#L95

> 
> Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
> ---
>  .../bindings/fpga/xlnx,zynqmp-afi-fpga.yaml   | 100 ++++++++++++++++++
>  1 file changed, 100 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
> 
> diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
> new file mode 100644
> index 000000000000..faae4951e991
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
> @@ -0,0 +1,100 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-afi-fpga.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx ZynqMP AFI interface Manager.
> +
> +maintainers:
> +  - Nava kishore Manne <nava.kishore.manne@amd.com>
> +
> +description: The Zynq UltraScale+ MPSoC Processing System core provides access
> +  from PL masters to PS internal peripherals, and memory through AXI FIFO
> +  interface(AFI)
> +
> +properties:
> +  compatible:
> +    items:

No items, you have only one item.

> +      - enum:
> +          - xlnx,zynqmp-afi-fpga
> +
> +  resets:
> +    description:
> +      A list of phandles for resets listed in reset-names.

You need maxItems:4

> +
> +  reset-names:
> +    items:
> +      - const: pl0-rst
> +      - const: pl1-rst
> +      - const: pl2-rst
> +      - const: pl3-rst
> +
> +patternProperties:
> +  "^xlnx,afifm[0-6]-rd-bus-width$":
> +    description: bus width used to configure the afifm-rd interface.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [ 32, 64, 128 ]
> +
> +  "^xlnx,afifm[0-6]-wr-bus-width$":
> +    description: bus width used to configure the afifm-wr interface.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [ 32, 64, 128 ]
> +
> +  "^xlnx,afifs-ss[0-2]-bus-width$":
> +    description: bus width used to configure the afifs interface.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [ 32, 64, 128 ]
> +
> +required:
> +  - compatible
> +  - xlnx,afifm0-rd-bus-width
> +  - xlnx,afifm1-rd-bus-width
> +  - xlnx,afifm2-rd-bus-width
> +  - xlnx,afifm3-rd-bus-width
> +  - xlnx,afifm4-rd-bus-width
> +  - xlnx,afifm5-rd-bus-width
> +  - xlnx,afifm6-rd-bus-width
> +  - xlnx,afifm0-wr-bus-width
> +  - xlnx,afifm1-wr-bus-width
> +  - xlnx,afifm2-wr-bus-width
> +  - xlnx,afifm3-wr-bus-width
> +  - xlnx,afifm4-wr-bus-width
> +  - xlnx,afifm5-wr-bus-width
> +  - xlnx,afifm6-wr-bus-width
> +  - xlnx,afifs-ss0-bus-width
> +  - xlnx,afifs-ss1-bus-width
> +  - xlnx,afifs-ss2-bus-width
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
> +    zynqmp-afi {

Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation



Best regards,
Krzysztof

RE: [PATCH 2/4] bindings: fpga: Add binding doc for the zynqmp afi config driver

[Manne, Nava kishore]

Hi Krzysztof,

	Please find my response inline.

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Wednesday, August 24, 2022 6:29 PM
> To: Manne, Nava kishore <nava.kishore.manne@amd.com>; git (AMD-Xilinx)
> <git@amd.com>; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> michal.simek@xilinx.com; mdf@kernel.org; hao.wu@intel.com;
> yilun.xu@intel.com; trix@redhat.com; p.zabel@pengutronix.de;
> gregkh@linuxfoundation.org; ronak.jain@xilinx.com; rajan.vaja@xilinx.com;
> abhyuday.godhasara@xilinx.com; piyush.mehta@xilinx.com;
> lakshmi.sai.krishna.potthuri@xilinx.com; harsha.harsha@xilinx.com;
> linus.walleij@linaro.org; nava.manne@xilinx.com;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; linux-fpga@vger.kernel.org
> Subject: Re: [PATCH 2/4] bindings: fpga: Add binding doc for the zynqmp afi
> config driver
> 
> On 24/08/2022 06:55, Nava kishore Manne wrote:
> > Xilinx Zynq US+ MPSoC platform connect the PS to the programmable
> > logic(PL) through the AXI port. This AXI port helps to establish
> 
> Use subject prefixes matching the subsystem (git log --oneline -- ...).
> 

Will fix in v2.

> > the data path between the PS and PL. In-order to establish the proper
> > communication data path between PS and PL the AXI port data path
> > should be configured with the proper Bus-width values.
> >
> > This patch adds the binding document for the zynqmp afi config driver
> > to handle the AXI port bus-width configurations and PS-PL resets.
> 
> Do not use "This commit/patch".
> https://elixir.bootlin.com/linux/v5.17.1/source/Documentation/process/sub
> mitting-patches.rst#L95
> 

Will fix in v2.

> >
> > Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
> > ---
> >  .../bindings/fpga/xlnx,zynqmp-afi-fpga.yaml   | 100 ++++++++++++++++++
> >  1 file changed, 100 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
> > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
> > new file mode 100644
> > index 000000000000..faae4951e991
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-
> fpga.yaml
> > @@ -0,0 +1,100 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-afi-fpga.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Xilinx ZynqMP AFI interface Manager.
> > +
> > +maintainers:
> > +  - Nava kishore Manne <nava.kishore.manne@amd.com>
> > +
> > +description: The Zynq UltraScale+ MPSoC Processing System core
> > +provides access
> > +  from PL masters to PS internal peripherals, and memory through AXI
> > +FIFO
> > +  interface(AFI)
> > +
> > +properties:
> > +  compatible:
> > +    items:
> 
> No items, you have only one item.
> 

Will fix in v2.

> > +      - enum:
> > +          - xlnx,zynqmp-afi-fpga
> > +
> > +  resets:
> > +    description:
> > +      A list of phandles for resets listed in reset-names.
> 
> You need maxItems:4
> 

Will fix in v2.

> > +
> > +  reset-names:
> > +    items:
> > +      - const: pl0-rst
> > +      - const: pl1-rst
> > +      - const: pl2-rst
> > +      - const: pl3-rst
> > +
> > +patternProperties:
> > +  "^xlnx,afifm[0-6]-rd-bus-width$":
> > +    description: bus width used to configure the afifm-rd interface.
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    enum: [ 32, 64, 128 ]
> > +
> > +  "^xlnx,afifm[0-6]-wr-bus-width$":
> > +    description: bus width used to configure the afifm-wr interface.
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    enum: [ 32, 64, 128 ]
> > +
> > +  "^xlnx,afifs-ss[0-2]-bus-width$":
> > +    description: bus width used to configure the afifs interface.
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    enum: [ 32, 64, 128 ]
> > +
> > +required:
> > +  - compatible
> > +  - xlnx,afifm0-rd-bus-width
> > +  - xlnx,afifm1-rd-bus-width
> > +  - xlnx,afifm2-rd-bus-width
> > +  - xlnx,afifm3-rd-bus-width
> > +  - xlnx,afifm4-rd-bus-width
> > +  - xlnx,afifm5-rd-bus-width
> > +  - xlnx,afifm6-rd-bus-width
> > +  - xlnx,afifm0-wr-bus-width
> > +  - xlnx,afifm1-wr-bus-width
> > +  - xlnx,afifm2-wr-bus-width
> > +  - xlnx,afifm3-wr-bus-width
> > +  - xlnx,afifm4-wr-bus-width
> > +  - xlnx,afifm5-wr-bus-width
> > +  - xlnx,afifm6-wr-bus-width
> > +  - xlnx,afifs-ss0-bus-width
> > +  - xlnx,afifs-ss1-bus-width
> > +  - xlnx,afifs-ss2-bus-width
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
> > +    zynqmp-afi {
> 
> Node names should be generic.
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-
> devicetree-basics.html#generic-names-recommendation
> 

Will fix in v2.

Regards,
Navakishore.

Re: [PATCH 2/4] bindings: fpga: Add binding doc for the zynqmp afi config driver

[Rob Herring]

On Tue, Aug 30, 2022 at 05:31:07AM +0000, Manne, Nava kishore wrote:
> Hi Krzysztof,
> 
> 	Please find my response inline.
> 
> > -----Original Message-----
> > From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> > Sent: Wednesday, August 24, 2022 6:29 PM
> > To: Manne, Nava kishore <nava.kishore.manne@amd.com>; git (AMD-Xilinx)
> > <git@amd.com>; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> > michal.simek@xilinx.com; mdf@kernel.org; hao.wu@intel.com;
> > yilun.xu@intel.com; trix@redhat.com; p.zabel@pengutronix.de;
> > gregkh@linuxfoundation.org; ronak.jain@xilinx.com; rajan.vaja@xilinx.com;
> > abhyuday.godhasara@xilinx.com; piyush.mehta@xilinx.com;
> > lakshmi.sai.krishna.potthuri@xilinx.com; harsha.harsha@xilinx.com;
> > linus.walleij@linaro.org; nava.manne@xilinx.com;
> > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> > kernel@vger.kernel.org; linux-fpga@vger.kernel.org
> > Subject: Re: [PATCH 2/4] bindings: fpga: Add binding doc for the zynqmp afi
> > config driver
> > 
> > On 24/08/2022 06:55, Nava kishore Manne wrote:
> > > Xilinx Zynq US+ MPSoC platform connect the PS to the programmable
> > > logic(PL) through the AXI port. This AXI port helps to establish
> > 
> > Use subject prefixes matching the subsystem (git log --oneline -- ...).
> > 
> 
> Will fix in v2.

This is what we assume. No need to reply back with agreement, and save 
us some mail to read.

Rob

Re: [PATCH 2/4] bindings: fpga: Add binding doc for the zynqmp afi config driver

[Rob Herring]

On Wed, Aug 24, 2022 at 09:25:40AM +0530, Nava kishore Manne wrote:
> Xilinx Zynq US+ MPSoC platform connect the PS to the programmable
> logic(PL) through the AXI port. This AXI port helps to establish
> the data path between the PS and PL. In-order to establish the proper
> communication data path between PS and PL the AXI port data path should
> be configured with the proper Bus-width values.
> 
> This patch adds the binding document for the zynqmp afi config driver
> to handle the AXI port bus-width configurations and PS-PL resets.
> 
> Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
> ---
>  .../bindings/fpga/xlnx,zynqmp-afi-fpga.yaml   | 100 ++++++++++++++++++
>  1 file changed, 100 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
> 
> diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
> new file mode 100644
> index 000000000000..faae4951e991
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
> @@ -0,0 +1,100 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-afi-fpga.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx ZynqMP AFI interface Manager.
> +
> +maintainers:
> +  - Nava kishore Manne <nava.kishore.manne@amd.com>
> +
> +description: The Zynq UltraScale+ MPSoC Processing System core provides access
> +  from PL masters to PS internal peripherals, and memory through AXI FIFO
> +  interface(AFI)
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - xlnx,zynqmp-afi-fpga
> +
> +  resets:
> +    description:
> +      A list of phandles for resets listed in reset-names.
> +
> +  reset-names:
> +    items:
> +      - const: pl0-rst
> +      - const: pl1-rst
> +      - const: pl2-rst
> +      - const: pl3-rst

Not all that useful of names given it is just indices. Minimally, '-rst' 
is redundant and I don't know what 'pl' means.

> +
> +patternProperties:
> +  "^xlnx,afifm[0-6]-rd-bus-width$":
> +    description: bus width used to configure the afifm-rd interface.

...width in bits...

> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [ 32, 64, 128 ]
> +
> +  "^xlnx,afifm[0-6]-wr-bus-width$":

Can combine these 2:

"^xlnx,afifm[0-6]-(wr|rd)-bus-width$"

> +    description: bus width used to configure the afifm-wr interface.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [ 32, 64, 128 ]
> +
> +  "^xlnx,afifs-ss[0-2]-bus-width$":
> +    description: bus width used to configure the afifs interface.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [ 32, 64, 128 ]
> +
> +required:
> +  - compatible
> +  - xlnx,afifm0-rd-bus-width
> +  - xlnx,afifm1-rd-bus-width
> +  - xlnx,afifm2-rd-bus-width
> +  - xlnx,afifm3-rd-bus-width
> +  - xlnx,afifm4-rd-bus-width
> +  - xlnx,afifm5-rd-bus-width
> +  - xlnx,afifm6-rd-bus-width
> +  - xlnx,afifm0-wr-bus-width
> +  - xlnx,afifm1-wr-bus-width
> +  - xlnx,afifm2-wr-bus-width
> +  - xlnx,afifm3-wr-bus-width
> +  - xlnx,afifm4-wr-bus-width
> +  - xlnx,afifm5-wr-bus-width
> +  - xlnx,afifm6-wr-bus-width
> +  - xlnx,afifs-ss0-bus-width
> +  - xlnx,afifs-ss1-bus-width
> +  - xlnx,afifs-ss2-bus-width
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
> +    zynqmp-afi {
> +      compatible = "xlnx,zynqmp-afi-fpga";
> +      xlnx,afifm0-rd-bus-width = <32>;
> +      xlnx,afifm1-rd-bus-width = <32>;
> +      xlnx,afifm2-rd-bus-width = <64>;
> +      xlnx,afifm3-rd-bus-width = <128>;
> +      xlnx,afifm4-rd-bus-width = <32>;
> +      xlnx,afifm5-rd-bus-width = <64>;
> +      xlnx,afifm6-rd-bus-width = <128>;
> +      xlnx,afifm0-wr-bus-width = <32>;
> +      xlnx,afifm1-wr-bus-width = <32>;
> +      xlnx,afifm2-wr-bus-width = <64>;
> +      xlnx,afifm3-wr-bus-width = <128>;
> +      xlnx,afifm4-wr-bus-width = <32>;
> +      xlnx,afifm5-wr-bus-width = <64>;
> +      xlnx,afifm6-wr-bus-width = <128>;
> +      xlnx,afifs-ss0-bus-width = <64>;
> +      xlnx,afifs-ss1-bus-width = <64>;
> +      xlnx,afifs-ss2-bus-width = <64>;
> +      resets = <&zynqmp_reset ZYNQMP_RESET_PS_PL0>,
> +               <&zynqmp_reset ZYNQMP_RESET_PS_PL1>,
> +               <&zynqmp_reset ZYNQMP_RESET_PS_PL2>,
> +               <&zynqmp_reset ZYNQMP_RESET_PS_PL3>;
> +      reset-names = "pl0-rst", "pl1-rst", "pl2-rst", "pl3-rst";

Should devices on this bus be child devices or do they fit on some other 
bus?

> +    };
> +
> +...
> -- 
> 2.25.1
> 
> 

[PATCH 3/4] bindings: firmware: Update binding doc for the zynqmp afi config node

[Nava kishore Manne]

Updates binding document for the zynqmp afi config node to handle the
PS_PL Bus-width and resets.

Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
---
 .../bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml     | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
index f14f7b454f07..9504665cad95 100644
--- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
+++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
@@ -59,6 +59,13 @@ properties:
       controller.
     type: object
 
+  zynqmp-fpga:
+    $ref: /schemas/fpga/xlnx,zynqmp-afi-fpga.yaml#
+    description: The Zynq UltraScale+ MPSoC Processing System core provides
+      access from PL masters to PS internal peripherals, and memory through
+      AXI FIFO interface(AFI)
+    type: object
+
 required:
   - compatible
 
-- 
2.25.1

Re: [PATCH 3/4] bindings: firmware: Update binding doc for the zynqmp afi config node

[Krzysztof Kozlowski]

Use subject prefixes matching the subsystem (git log --oneline -- ...).

"bindings" is no correct.

On 24/08/2022 06:55, Nava kishore Manne wrote:
> Updates binding document for the zynqmp afi config node to handle the
> PS_PL Bus-width and resets.

Use imperative language:
https://elixir.bootlin.com/linux/v5.17.1/source/Documentation/process/submitting-patches.rst#L95
> 
> Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
> ---
>  .../bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml     | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
> index f14f7b454f07..9504665cad95 100644
> --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
> +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
> @@ -59,6 +59,13 @@ properties:
>        controller.
>      type: object
>  
> +  zynqmp-fpga:

Just: fpga

> +    $ref: /schemas/fpga/xlnx,zynqmp-afi-fpga.yaml#
> +    description: The Zynq UltraScale+ MPSoC Processing System core provides
> +      access from PL masters to PS internal peripherals, and memory through
> +      AXI FIFO interface(AFI)
> +    type: object
> +
>  required:
>    - compatible
>  


Best regards,
Krzysztof

RE: [PATCH 3/4] bindings: firmware: Update binding doc for the zynqmp afi config node

[Manne, Nava kishore]

Hi Krzysztof,

	Please find my response inline. 

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Wednesday, August 24, 2022 6:28 PM
> To: Manne, Nava kishore <nava.kishore.manne@amd.com>; git (AMD-Xilinx)
> <git@amd.com>; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> michal.simek@xilinx.com; mdf@kernel.org; hao.wu@intel.com;
> yilun.xu@intel.com; trix@redhat.com; p.zabel@pengutronix.de;
> gregkh@linuxfoundation.org; ronak.jain@xilinx.com; rajan.vaja@xilinx.com;
> abhyuday.godhasara@xilinx.com; piyush.mehta@xilinx.com;
> lakshmi.sai.krishna.potthuri@xilinx.com; harsha.harsha@xilinx.com;
> linus.walleij@linaro.org; nava.manne@xilinx.com;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; linux-fpga@vger.kernel.org
> Subject: Re: [PATCH 3/4] bindings: firmware: Update binding doc for the
> zynqmp afi config node
> 
> Use subject prefixes matching the subsystem (git log --oneline -- ...).
> 
> "bindings" is no correct.

Will fix in v2.

> 
> On 24/08/2022 06:55, Nava kishore Manne wrote:
> > Updates binding document for the zynqmp afi config node to handle the
> > PS_PL Bus-width and resets.
> 
> Use imperative language:
> https://elixir.bootlin.com/linux/v5.17.1/source/Documentation/process/sub
> mitting-patches.rst#L95

Will fix in v2.

> >
> > Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
> > ---
> >  .../bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml     | 7 +++++++
> >  1 file changed, 7 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-
> firmwa
> > re.yaml
> > b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-
> firmwa
> > re.yaml index f14f7b454f07..9504665cad95 100644
> > ---
> > a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-
> firmwa
> > re.yaml
> > +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-fi
> > +++ rmware.yaml
> > @@ -59,6 +59,13 @@ properties:
> >        controller.
> >      type: object
> >
> > +  zynqmp-fpga:
> 
> Just: fpga
> 
 
Will fix in v2.

Regards,
Navakishore.

[PATCH 4/4] fpga: zynqmp: Add afi config driver

[Nava kishore Manne]

Add zynqmp AXI FIFO interface(AFI) config driver. This is useful for the
configuration of the PS-PL interface on Zynq US+ MPSoC platform.

Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
---
 MAINTAINERS               |   6 ++
 drivers/fpga/Kconfig      |  13 +++
 drivers/fpga/Makefile     |   1 +
 drivers/fpga/zynqmp-afi.c | 211 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 231 insertions(+)
 create mode 100644 drivers/fpga/zynqmp-afi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 20ffac651214..957e753e6406 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8032,6 +8032,12 @@ F:	Documentation/fpga/
 F:	drivers/fpga/
 F:	include/linux/fpga/
 
+FPGA ZYNQMP PS-PL BRIDGE DRIVER
+M:	Nava kishore Manne <nava.kishore.manne@amd.com>
+S:	Supported
+F:	Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
+F:	drivers/fpga/zynqmp-afi.c
+
 INTEL MAX10 BMC SECURE UPDATES
 M:	Russ Weight <russell.h.weight@intel.com>
 L:	linux-fpga@vger.kernel.org
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 6c416955da53..c08794d30fb5 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -130,6 +130,19 @@ config XILINX_PR_DECOUPLER
 	  reconfiguration, preventing the system deadlock that can
 	  occur if AXI transactions are interrupted by DFX.
 
+config ZYNQMP_AFI
+	tristate "Xilinx ZYNQMP AFI support"
+	depends on FPGA_BRIDGE
+	help
+	  Say Y to enable drivers to handle the PS-PL clocks configurations
+	  and PS-PL Bus-width. Xilinx Zynq US+ MPSoC connect the PS to the
+	  programmable logic (PL) through the AXI port. This AXI port helps
+	  to establish the data path between the PS and PL.
+	  In-order to establish the proper communication path between PS and PL,
+	  the AXI port data path should be configured with the proper Bus-width
+	  values and it will also handles the PS-PL reset signals to reset the
+	  PL domain.
+
 config FPGA_REGION
 	tristate "FPGA Region"
 	depends on FPGA_BRIDGE
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 42ae8b58abce..94cfe60972db 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_FPGA_BRIDGE)		+= fpga-bridge.o
 obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE)	+= altera-hps2fpga.o altera-fpga2sdram.o
 obj-$(CONFIG_ALTERA_FREEZE_BRIDGE)	+= altera-freeze-bridge.o
 obj-$(CONFIG_XILINX_PR_DECOUPLER)	+= xilinx-pr-decoupler.o
+obj-$(CONFIG_ZYNQMP_AFI)		+= zynqmp-afi.o
 
 # High Level Interfaces
 obj-$(CONFIG_FPGA_REGION)		+= fpga-region.o
diff --git a/drivers/fpga/zynqmp-afi.c b/drivers/fpga/zynqmp-afi.c
new file mode 100644
index 000000000000..bc975d304039
--- /dev/null
+++ b/drivers/fpga/zynqmp-afi.c
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Xilinx, Inc.
+ */
+
+#include <linux/err.h>
+#include <linux/firmware/xlnx-zynqmp.h>
+#include <linux/fpga/fpga-bridge.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+
+/* Registers and special values for doing register-based operations */
+#define AFI_RDCHAN_CTRL_OFFSET	0x00
+#define AFI_WRCHAN_CTRL_OFFSET	0x14
+#define AFI_BUSWIDTH_MASK	BIT(0)
+
+/**
+ * struct zynqmp_afi - AFI register description.
+ * @dev: device that owns this.
+ * @of_node: Device Tree overlay.
+ * @resets: Pointer to the reset control for ps-pl resets.
+ */
+struct zynqmp_afi {
+	struct device *dev;
+	struct device_node *of_node;
+	struct reset_control *resets;
+};
+
+/**
+ * struct zynqmp_afi_configreg - AFI configuration registers info.
+ * @reg:	Name of the AFI configuration register.
+ * @id:		Register index value.
+ */
+struct zynqmp_afi_configreg {
+	char *reg;
+	u32 id;
+};
+
+static struct zynqmp_afi_configreg afi_cfgreg[] = {
+	{.reg = "xlnx,afi-fm0-rd-bus-width",	.id = AFIFM0_RDCTRL},
+	{.reg = "xlnx,afi-fm1-rd-bus-width",	.id = AFIFM1_RDCTRL},
+	{.reg = "xlnx,afi-fm2-rd-bus-width",	.id = AFIFM2_RDCTRL},
+	{.reg = "xlnx,afi-fm3-rd-bus-width",	.id = AFIFM3_RDCTRL},
+	{.reg = "xlnx,afi-fm4-rd-bus-width",	.id = AFIFM4_RDCTRL},
+	{.reg = "xlnx,afi-fm5-rd-bus-width",	.id = AFIFM5_RDCTRL},
+	{.reg = "xlnx,afi-fm6-rd-bus-width",	.id = AFIFM6_RDCTRL},
+	{.reg = "xlnx,afi-fm0-wr-bus-width",	.id = AFIFM0_WRCTRL},
+	{.reg = "xlnx,afi-fm1-wr-bus-width",	.id = AFIFM1_WRCTRL},
+	{.reg = "xlnx,afi-fm2-wr-bus-width",	.id = AFIFM2_WRCTRL},
+	{.reg = "xlnx,afi-fm3-wr-bus-width",	.id = AFIFM3_WRCTRL},
+	{.reg = "xlnx,afi-fm4-wr-bus-width",	.id = AFIFM4_WRCTRL},
+	{.reg = "xlnx,afi-fm5-wr-bus-width",	.id = AFIFM5_WRCTRL},
+	{.reg = "xlnx,afi-fm6-wr-bus-width",	.id = AFIFM6_WRCTRL},
+	{.reg = "xlnx,afi-fs-ss0-bus-width",	.id = AFIFS},
+	{.reg = "xlnx,afi-fs-ss2-bus-width",	.id = AFIFS_SS2},
+	{}
+};
+
+static int zynqmp_afi_config(struct zynqmp_afi *afi_data)
+{
+	struct zynqmp_afi_configreg *cfgptr = afi_cfgreg;
+	struct device_node *np = afi_data->of_node;
+	u32 afi_ss0_val, afi_ss1_val, bus_width;
+	int ret;
+
+	while (cfgptr->reg) {
+		ret = of_property_read_u32(np, cfgptr->reg, &bus_width);
+		if (!ret) {
+			if (cfgptr->id == AFIFS_SS2) {
+				if (bus_width == 32)
+					ret = zynqmp_pm_afi(AFIFS_SS2,
+							    AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL);
+				else if (bus_width == 64)
+					ret = zynqmp_pm_afi(AFIFS_SS2,
+							    AFIFS_SS0_SS2_BUS_WIDTH_64_CONFIG_VAL);
+				else if (bus_width == 128)
+					ret = zynqmp_pm_afi(AFIFS_SS2,
+							    AFIFS_SS0_SS2_BUS_WIDTH_128_CONFIG_VAL);
+				else
+					return -EINVAL;
+			} else if (cfgptr->id == AFIFS) {
+				if (bus_width == 32)
+					afi_ss0_val = AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL;
+				else if (bus_width == 64)
+					afi_ss0_val = AFIFS_SS0_SS2_BUS_WIDTH_64_CONFIG_VAL;
+				else if (bus_width == 128)
+					afi_ss0_val = AFIFS_SS0_SS2_BUS_WIDTH_128_CONFIG_VAL;
+				else
+					return -EINVAL;
+
+				ret = of_property_read_u32(np, "xlnx,afi-fs-ss1-bus-width",
+							   &bus_width);
+				if (!ret) {
+					if (bus_width == 32)
+						afi_ss1_val = AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL;
+					else if (bus_width == 64)
+						afi_ss1_val = AFIFS_SS1_BUS_WIDTH_64_CONFIG_VAL;
+					else if (bus_width == 128)
+						afi_ss1_val = AFIFS_SS1_BUS_WIDTH_128_CONFIG_VAL;
+					else
+						return -EINVAL;
+
+					ret = zynqmp_pm_afi(AFIFS, afi_ss1_val | afi_ss0_val);
+				}
+			} else {
+				if (bus_width == 32)
+					ret = zynqmp_pm_afi(cfgptr->id,
+							    AFIFM_BUS_WIDTH_32_CONFIG_VAL);
+				else if (bus_width == 64)
+					ret = zynqmp_pm_afi(cfgptr->id,
+							    AFIFM_BUS_WIDTH_64_CONFIG_VAL);
+				else if (bus_width == 128)
+					ret = zynqmp_pm_afi(cfgptr->id,
+							    AFIFM_BUS_WIDTH_128_CONFIG_VAL);
+				else
+					return -EINVAL;
+			}
+		}
+		cfgptr++;
+	}
+
+	return 0;
+}
+
+static int zynqmp_afi_enable_set(struct fpga_bridge *bridge, bool enable)
+{
+	struct device_node *overlay = bridge->info->overlay;
+	struct zynqmp_afi *priv = bridge->priv;
+	int ret = 0;
+
+	if (enable) {
+		reset_control_reset(priv->resets);
+		return 0;
+	}
+
+	of_node_get(overlay);
+	priv->of_node =
+	of_find_node_with_property(overlay,
+				   "xlnx,afi-fm0-rd-bus-width");
+	if (priv->of_node)
+		ret = zynqmp_afi_config(priv);
+	of_node_put(priv->of_node);
+
+	return ret;
+}
+
+static const struct fpga_bridge_ops zynqmp_afi_br_ops = {
+	.enable_set = zynqmp_afi_enable_set,
+};
+
+static const struct of_device_id zynqmp_afi_of_match[] = {
+	{ .compatible =  "xlnx,zynqmp-afi-fpga" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, zynqmp_afi_of_match);
+
+static int zynqmp_afi_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct zynqmp_afi *priv;
+	struct fpga_bridge *br;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = dev;
+
+	priv->resets = devm_reset_control_array_get_optional_exclusive(&pdev->dev);
+	if (IS_ERR(priv->resets))
+		return PTR_ERR(priv->resets);
+
+	br = fpga_bridge_register(dev, "Xilinx ZynqMP AFI",
+				  &zynqmp_afi_br_ops, priv);
+	if (IS_ERR(br)) {
+		dev_err(dev, "unable to register Xilinx ZynqMP AFI");
+		return PTR_ERR(br);
+	}
+
+	platform_set_drvdata(pdev, br);
+
+	return 0;
+}
+
+static int zynqmp_afi_remove(struct platform_device *pdev)
+{
+	struct fpga_bridge *bridge = platform_get_drvdata(pdev);
+
+	fpga_bridge_unregister(bridge);
+
+	return 0;
+}
+
+static struct platform_driver zynqmp_afi_driver = {
+	.probe = zynqmp_afi_probe,
+	.remove = zynqmp_afi_remove,
+	.driver = {
+		.name = "zynqmp_afi",
+		.of_match_table = of_match_ptr(zynqmp_afi_of_match),
+	},
+};
+
+module_platform_driver(zynqmp_afi_driver);
+
+MODULE_DESCRIPTION("ZYNQMP FPGA AXI FIFO interface configuration module");
+MODULE_AUTHOR("Nava kishore Manne <nava.kishore.manne@amd.com>");
+MODULE_LICENSE("GPL");
-- 
2.25.1

Re: [PATCH 4/4] fpga: zynqmp: Add afi config driver

[Krzysztof Kozlowski]

On 24/08/2022 06:55, Nava kishore Manne wrote:
> Add zynqmp AXI FIFO interface(AFI) config driver. This is useful for the
> configuration of the PS-PL interface on Zynq US+ MPSoC platform.
> 
> Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
> ---

(...)

> +
> +static struct platform_driver zynqmp_afi_driver = {
> +	.probe = zynqmp_afi_probe,
> +	.remove = zynqmp_afi_remove,
> +	.driver = {
> +		.name = "zynqmp_afi",
> +		.of_match_table = of_match_ptr(zynqmp_afi_of_match),

It should generate warnings... test compile your driver.

Drop of_match_ptr() or use __maybe_unused

Best regards,
Krzysztof

Re: [PATCH 4/4] fpga: zynqmp: Add afi config driver

[Xu Yilun]

On 2022-08-24 at 09:25:42 +0530, Nava kishore Manne wrote:
> Add zynqmp AXI FIFO interface(AFI) config driver. This is useful for the
> configuration of the PS-PL interface on Zynq US+ MPSoC platform.

Please help illustrate how to use the device for FPGA reprogramming, why
it should be implemented as an FPGA bridge.

From the code I actually didn't see any operation that gates the
fpga-region from other part of the machine.

> 
> Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
> ---
>  MAINTAINERS               |   6 ++
>  drivers/fpga/Kconfig      |  13 +++
>  drivers/fpga/Makefile     |   1 +
>  drivers/fpga/zynqmp-afi.c | 211 ++++++++++++++++++++++++++++++++++++++
>  4 files changed, 231 insertions(+)
>  create mode 100644 drivers/fpga/zynqmp-afi.c
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 20ffac651214..957e753e6406 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -8032,6 +8032,12 @@ F:	Documentation/fpga/
>  F:	drivers/fpga/
>  F:	include/linux/fpga/
>  
> +FPGA ZYNQMP PS-PL BRIDGE DRIVER
> +M:	Nava kishore Manne <nava.kishore.manne@amd.com>
> +S:	Supported
> +F:	Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
> +F:	drivers/fpga/zynqmp-afi.c
> +
>  INTEL MAX10 BMC SECURE UPDATES
>  M:	Russ Weight <russell.h.weight@intel.com>
>  L:	linux-fpga@vger.kernel.org
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index 6c416955da53..c08794d30fb5 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -130,6 +130,19 @@ config XILINX_PR_DECOUPLER
>  	  reconfiguration, preventing the system deadlock that can
>  	  occur if AXI transactions are interrupted by DFX.
>  
> +config ZYNQMP_AFI
> +	tristate "Xilinx ZYNQMP AFI support"
> +	depends on FPGA_BRIDGE
> +	help
> +	  Say Y to enable drivers to handle the PS-PL clocks configurations
> +	  and PS-PL Bus-width. Xilinx Zynq US+ MPSoC connect the PS to the
> +	  programmable logic (PL) through the AXI port. This AXI port helps
> +	  to establish the data path between the PS and PL.
> +	  In-order to establish the proper communication path between PS and PL,
> +	  the AXI port data path should be configured with the proper Bus-width
> +	  values and it will also handles the PS-PL reset signals to reset the
> +	  PL domain.

Same concern, please describe its relationship to FPGA reprogramming.

> +
>  config FPGA_REGION
>  	tristate "FPGA Region"
>  	depends on FPGA_BRIDGE
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 42ae8b58abce..94cfe60972db 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -31,6 +31,7 @@ obj-$(CONFIG_FPGA_BRIDGE)		+= fpga-bridge.o
>  obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE)	+= altera-hps2fpga.o altera-fpga2sdram.o
>  obj-$(CONFIG_ALTERA_FREEZE_BRIDGE)	+= altera-freeze-bridge.o
>  obj-$(CONFIG_XILINX_PR_DECOUPLER)	+= xilinx-pr-decoupler.o
> +obj-$(CONFIG_ZYNQMP_AFI)		+= zynqmp-afi.o
>  
>  # High Level Interfaces
>  obj-$(CONFIG_FPGA_REGION)		+= fpga-region.o
> diff --git a/drivers/fpga/zynqmp-afi.c b/drivers/fpga/zynqmp-afi.c
> new file mode 100644
> index 000000000000..bc975d304039
> --- /dev/null
> +++ b/drivers/fpga/zynqmp-afi.c
> @@ -0,0 +1,211 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2022 Xilinx, Inc.
> + */
> +
> +#include <linux/err.h>
> +#include <linux/firmware/xlnx-zynqmp.h>
> +#include <linux/fpga/fpga-bridge.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +#include <linux/slab.h>
> +
> +/* Registers and special values for doing register-based operations */
> +#define AFI_RDCHAN_CTRL_OFFSET	0x00
> +#define AFI_WRCHAN_CTRL_OFFSET	0x14
> +#define AFI_BUSWIDTH_MASK	BIT(0)
> +
> +/**
> + * struct zynqmp_afi - AFI register description.
> + * @dev: device that owns this.
> + * @of_node: Device Tree overlay.
> + * @resets: Pointer to the reset control for ps-pl resets.
> + */
> +struct zynqmp_afi {
> +	struct device *dev;
> +	struct device_node *of_node;
> +	struct reset_control *resets;
> +};
> +
> +/**
> + * struct zynqmp_afi_configreg - AFI configuration registers info.
> + * @reg:	Name of the AFI configuration register.
> + * @id:		Register index value.
> + */
> +struct zynqmp_afi_configreg {
> +	char *reg;
> +	u32 id;
> +};
> +
> +static struct zynqmp_afi_configreg afi_cfgreg[] = {
> +	{.reg = "xlnx,afi-fm0-rd-bus-width",	.id = AFIFM0_RDCTRL},
> +	{.reg = "xlnx,afi-fm1-rd-bus-width",	.id = AFIFM1_RDCTRL},
> +	{.reg = "xlnx,afi-fm2-rd-bus-width",	.id = AFIFM2_RDCTRL},
> +	{.reg = "xlnx,afi-fm3-rd-bus-width",	.id = AFIFM3_RDCTRL},
> +	{.reg = "xlnx,afi-fm4-rd-bus-width",	.id = AFIFM4_RDCTRL},
> +	{.reg = "xlnx,afi-fm5-rd-bus-width",	.id = AFIFM5_RDCTRL},
> +	{.reg = "xlnx,afi-fm6-rd-bus-width",	.id = AFIFM6_RDCTRL},
> +	{.reg = "xlnx,afi-fm0-wr-bus-width",	.id = AFIFM0_WRCTRL},
> +	{.reg = "xlnx,afi-fm1-wr-bus-width",	.id = AFIFM1_WRCTRL},
> +	{.reg = "xlnx,afi-fm2-wr-bus-width",	.id = AFIFM2_WRCTRL},
> +	{.reg = "xlnx,afi-fm3-wr-bus-width",	.id = AFIFM3_WRCTRL},
> +	{.reg = "xlnx,afi-fm4-wr-bus-width",	.id = AFIFM4_WRCTRL},
> +	{.reg = "xlnx,afi-fm5-wr-bus-width",	.id = AFIFM5_WRCTRL},
> +	{.reg = "xlnx,afi-fm6-wr-bus-width",	.id = AFIFM6_WRCTRL},
> +	{.reg = "xlnx,afi-fs-ss0-bus-width",	.id = AFIFS},
> +	{.reg = "xlnx,afi-fs-ss2-bus-width",	.id = AFIFS_SS2},
> +	{}
> +};
> +
> +static int zynqmp_afi_config(struct zynqmp_afi *afi_data)
> +{
> +	struct zynqmp_afi_configreg *cfgptr = afi_cfgreg;
> +	struct device_node *np = afi_data->of_node;
> +	u32 afi_ss0_val, afi_ss1_val, bus_width;
> +	int ret;
> +
> +	while (cfgptr->reg) {
> +		ret = of_property_read_u32(np, cfgptr->reg, &bus_width);
> +		if (!ret) {
> +			if (cfgptr->id == AFIFS_SS2) {
> +				if (bus_width == 32)
> +					ret = zynqmp_pm_afi(AFIFS_SS2,
> +							    AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL);
> +				else if (bus_width == 64)
> +					ret = zynqmp_pm_afi(AFIFS_SS2,
> +							    AFIFS_SS0_SS2_BUS_WIDTH_64_CONFIG_VAL);
> +				else if (bus_width == 128)
> +					ret = zynqmp_pm_afi(AFIFS_SS2,
> +							    AFIFS_SS0_SS2_BUS_WIDTH_128_CONFIG_VAL);
> +				else
> +					return -EINVAL;
> +			} else if (cfgptr->id == AFIFS) {
> +				if (bus_width == 32)
> +					afi_ss0_val = AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL;
> +				else if (bus_width == 64)
> +					afi_ss0_val = AFIFS_SS0_SS2_BUS_WIDTH_64_CONFIG_VAL;
> +				else if (bus_width == 128)
> +					afi_ss0_val = AFIFS_SS0_SS2_BUS_WIDTH_128_CONFIG_VAL;
> +				else
> +					return -EINVAL;
> +
> +				ret = of_property_read_u32(np, "xlnx,afi-fs-ss1-bus-width",
> +							   &bus_width);
> +				if (!ret) {
> +					if (bus_width == 32)
> +						afi_ss1_val = AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL;
> +					else if (bus_width == 64)
> +						afi_ss1_val = AFIFS_SS1_BUS_WIDTH_64_CONFIG_VAL;
> +					else if (bus_width == 128)
> +						afi_ss1_val = AFIFS_SS1_BUS_WIDTH_128_CONFIG_VAL;
> +					else
> +						return -EINVAL;
> +
> +					ret = zynqmp_pm_afi(AFIFS, afi_ss1_val | afi_ss0_val);
> +				}
> +			} else {
> +				if (bus_width == 32)
> +					ret = zynqmp_pm_afi(cfgptr->id,
> +							    AFIFM_BUS_WIDTH_32_CONFIG_VAL);
> +				else if (bus_width == 64)
> +					ret = zynqmp_pm_afi(cfgptr->id,
> +							    AFIFM_BUS_WIDTH_64_CONFIG_VAL);
> +				else if (bus_width == 128)
> +					ret = zynqmp_pm_afi(cfgptr->id,
> +							    AFIFM_BUS_WIDTH_128_CONFIG_VAL);
> +				else
> +					return -EINVAL;
> +			}
> +		}
> +		cfgptr++;
> +	}
> +
> +	return 0;
> +}
> +
> +static int zynqmp_afi_enable_set(struct fpga_bridge *bridge, bool enable)
> +{
> +	struct device_node *overlay = bridge->info->overlay;
> +	struct zynqmp_afi *priv = bridge->priv;
> +	int ret = 0;
> +
> +	if (enable) {
> +		reset_control_reset(priv->resets);
> +		return 0;
> +	}
> +
> +	of_node_get(overlay);
> +	priv->of_node =
> +	of_find_node_with_property(overlay,
> +				   "xlnx,afi-fm0-rd-bus-width");

I'm a little confused here. The fpga_image_info.overlay is for
fpga-region, but from your binding doc this property is for this afi
device. You want to add another overlay targeting afi dev node during
reprograming?

> +	if (priv->of_node)
> +		ret = zynqmp_afi_config(priv);
> +	of_node_put(priv->of_node);
> +
> +	return ret;
> +}
> +
> +static const struct fpga_bridge_ops zynqmp_afi_br_ops = {
> +	.enable_set = zynqmp_afi_enable_set,
> +};
> +
> +static const struct of_device_id zynqmp_afi_of_match[] = {
> +	{ .compatible =  "xlnx,zynqmp-afi-fpga" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, zynqmp_afi_of_match);
> +
> +static int zynqmp_afi_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct zynqmp_afi *priv;
> +	struct fpga_bridge *br;
> +
> +	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +
> +	priv->dev = dev;
> +
> +	priv->resets = devm_reset_control_array_get_optional_exclusive(&pdev->dev);
> +	if (IS_ERR(priv->resets))
> +		return PTR_ERR(priv->resets);
> +
> +	br = fpga_bridge_register(dev, "Xilinx ZynqMP AFI",
> +				  &zynqmp_afi_br_ops, priv);
> +	if (IS_ERR(br)) {
> +		dev_err(dev, "unable to register Xilinx ZynqMP AFI");

Need a "\n" at the end?

Thanks,
Yilun

> +		return PTR_ERR(br);
> +	}
> +
> +	platform_set_drvdata(pdev, br);
> +
> +	return 0;
> +}
> +
> +static int zynqmp_afi_remove(struct platform_device *pdev)
> +{
> +	struct fpga_bridge *bridge = platform_get_drvdata(pdev);
> +
> +	fpga_bridge_unregister(bridge);
> +
> +	return 0;
> +}
> +
> +static struct platform_driver zynqmp_afi_driver = {
> +	.probe = zynqmp_afi_probe,
> +	.remove = zynqmp_afi_remove,
> +	.driver = {
> +		.name = "zynqmp_afi",
> +		.of_match_table = of_match_ptr(zynqmp_afi_of_match),
> +	},
> +};
> +
> +module_platform_driver(zynqmp_afi_driver);
> +
> +MODULE_DESCRIPTION("ZYNQMP FPGA AXI FIFO interface configuration module");
> +MODULE_AUTHOR("Nava kishore Manne <nava.kishore.manne@amd.com>");
> +MODULE_LICENSE("GPL");
> -- 
> 2.25.1
> 

RE: [PATCH 4/4] fpga: zynqmp: Add afi config driver

[Manne, Nava kishore]

Hi Yilun,

	Please find my response inline.

> -----Original Message-----
> From: Xu Yilun <yilun.xu@intel.com>
> Sent: Saturday, August 27, 2022 5:56 PM
> To: Manne, Nava kishore <nava.kishore.manne@amd.com>
> Cc: git (AMD-Xilinx) <git@amd.com>; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; michal.simek@xilinx.com;
> mdf@kernel.org; hao.wu@intel.com; trix@redhat.com;
> p.zabel@pengutronix.de; gregkh@linuxfoundation.org;
> ronak.jain@xilinx.com; rajan.vaja@xilinx.com;
> abhyuday.godhasara@xilinx.com; piyush.mehta@xilinx.com;
> lakshmi.sai.krishna.potthuri@xilinx.com; harsha.harsha@xilinx.com;
> linus.walleij@linaro.org; nava.manne@xilinx.com;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; linux-fpga@vger.kernel.org
> Subject: Re: [PATCH 4/4] fpga: zynqmp: Add afi config driver
> 
> CAUTION: This message has originated from an External Source. Please use
> proper judgment and caution when opening attachments, clicking links, or
> responding to this email.
> 
> 
> On 2022-08-24 at 09:25:42 +0530, Nava kishore Manne wrote:
> > Add zynqmp AXI FIFO interface(AFI) config driver. This is useful for
> > the configuration of the PS-PL interface on Zynq US+ MPSoC platform.
> 
> Please help illustrate how to use the device for FPGA reprogramming, why it
> should be implemented as an FPGA bridge.
> 
> From the code I actually didn't see any operation that gates the fpga-region
> from other part of the machine.
> 

The Zynq UltraScale MPSoC family consists of a system-on-chip (SoC) style integrated processing system (PS)
and a Programmable Logic (PL) unit, providing an extensible and flexible SoC solution on a single die. 
Xilinx Zynq US+ MPSoC connect the PS to the programmable logic (PL) through the AXI port. 
This AXI port helps to establish the data path between the PS and PL (Here AXI Interface act as a Gating between PS and PL)
and this AXI port configuration vary from design to design.  In-order to establish the proper communication path between
PS and PL (Full region),  the AXI port data path should be configured with proper values priories to load the full region.

Will update the description in v2.

> >
> > Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
> > ---
> >  MAINTAINERS               |   6 ++
> >  drivers/fpga/Kconfig      |  13 +++
> >  drivers/fpga/Makefile     |   1 +
> >  drivers/fpga/zynqmp-afi.c | 211
> > ++++++++++++++++++++++++++++++++++++++
> >  4 files changed, 231 insertions(+)
> >  create mode 100644 drivers/fpga/zynqmp-afi.c
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS index
> > 20ffac651214..957e753e6406 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -8032,6 +8032,12 @@ F:     Documentation/fpga/
> >  F:   drivers/fpga/
> >  F:   include/linux/fpga/
> >
> > +FPGA ZYNQMP PS-PL BRIDGE DRIVER
> > +M:   Nava kishore Manne <nava.kishore.manne@amd.com>
> > +S:   Supported
> > +F:   Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
> > +F:   drivers/fpga/zynqmp-afi.c
> > +
> >  INTEL MAX10 BMC SECURE UPDATES
> >  M:   Russ Weight <russell.h.weight@intel.com>
> >  L:   linux-fpga@vger.kernel.org
> > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index
> > 6c416955da53..c08794d30fb5 100644
> > --- a/drivers/fpga/Kconfig
> > +++ b/drivers/fpga/Kconfig
> > @@ -130,6 +130,19 @@ config XILINX_PR_DECOUPLER
> >         reconfiguration, preventing the system deadlock that can
> >         occur if AXI transactions are interrupted by DFX.
> >
> > +config ZYNQMP_AFI
> > +     tristate "Xilinx ZYNQMP AFI support"
> > +     depends on FPGA_BRIDGE
> > +     help
> > +       Say Y to enable drivers to handle the PS-PL clocks configurations
> > +       and PS-PL Bus-width. Xilinx Zynq US+ MPSoC connect the PS to the
> > +       programmable logic (PL) through the AXI port. This AXI port helps
> > +       to establish the data path between the PS and PL.
> > +       In-order to establish the proper communication path between PS and
> PL,
> > +       the AXI port data path should be configured with the proper Bus-
> width
> > +       values and it will also handles the PS-PL reset signals to reset the
> > +       PL domain.
> 
> Same concern, please describe its relationship to FPGA reprogramming.
> 

Same as above.
Will update the description in v2.

> > +
> >  config FPGA_REGION
> >       tristate "FPGA Region"
> >       depends on FPGA_BRIDGE
> > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index
> > 42ae8b58abce..94cfe60972db 100644
> > --- a/drivers/fpga/Makefile
> > +++ b/drivers/fpga/Makefile
> > @@ -31,6 +31,7 @@ obj-$(CONFIG_FPGA_BRIDGE)           += fpga-bridge.o
> >  obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE)    += altera-hps2fpga.o altera-
> fpga2sdram.o
> >  obj-$(CONFIG_ALTERA_FREEZE_BRIDGE)   += altera-freeze-bridge.o
> >  obj-$(CONFIG_XILINX_PR_DECOUPLER)    += xilinx-pr-decoupler.o
> > +obj-$(CONFIG_ZYNQMP_AFI)             += zynqmp-afi.o
> >
> >  # High Level Interfaces
> >  obj-$(CONFIG_FPGA_REGION)            += fpga-region.o
> > diff --git a/drivers/fpga/zynqmp-afi.c b/drivers/fpga/zynqmp-afi.c new
> > file mode 100644 index 000000000000..bc975d304039
> > --- /dev/null
> > +++ b/drivers/fpga/zynqmp-afi.c
> > @@ -0,0 +1,211 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2022 Xilinx, Inc.
> > + */
> > +
> > +#include <linux/err.h>
> > +#include <linux/firmware/xlnx-zynqmp.h> #include
> > +<linux/fpga/fpga-bridge.h> #include <linux/io.h> #include
> > +<linux/module.h> #include <linux/of.h> #include
> > +<linux/platform_device.h> #include <linux/reset.h> #include
> > +<linux/slab.h>
> > +
> > +/* Registers and special values for doing register-based operations */
> > +#define AFI_RDCHAN_CTRL_OFFSET       0x00
> > +#define AFI_WRCHAN_CTRL_OFFSET       0x14
> > +#define AFI_BUSWIDTH_MASK    BIT(0)
> > +
> > +/**
> > + * struct zynqmp_afi - AFI register description.
> > + * @dev: device that owns this.
> > + * @of_node: Device Tree overlay.
> > + * @resets: Pointer to the reset control for ps-pl resets.
> > + */
> > +struct zynqmp_afi {
> > +     struct device *dev;
> > +     struct device_node *of_node;
> > +     struct reset_control *resets;
> > +};
> > +
> > +/**
> > + * struct zynqmp_afi_configreg - AFI configuration registers info.
> > + * @reg:     Name of the AFI configuration register.
> > + * @id:              Register index value.
> > + */
> > +struct zynqmp_afi_configreg {
> > +     char *reg;
> > +     u32 id;
> > +};
> > +
> > +static struct zynqmp_afi_configreg afi_cfgreg[] = {
> > +     {.reg = "xlnx,afi-fm0-rd-bus-width",    .id = AFIFM0_RDCTRL},
> > +     {.reg = "xlnx,afi-fm1-rd-bus-width",    .id = AFIFM1_RDCTRL},
> > +     {.reg = "xlnx,afi-fm2-rd-bus-width",    .id = AFIFM2_RDCTRL},
> > +     {.reg = "xlnx,afi-fm3-rd-bus-width",    .id = AFIFM3_RDCTRL},
> > +     {.reg = "xlnx,afi-fm4-rd-bus-width",    .id = AFIFM4_RDCTRL},
> > +     {.reg = "xlnx,afi-fm5-rd-bus-width",    .id = AFIFM5_RDCTRL},
> > +     {.reg = "xlnx,afi-fm6-rd-bus-width",    .id = AFIFM6_RDCTRL},
> > +     {.reg = "xlnx,afi-fm0-wr-bus-width",    .id = AFIFM0_WRCTRL},
> > +     {.reg = "xlnx,afi-fm1-wr-bus-width",    .id = AFIFM1_WRCTRL},
> > +     {.reg = "xlnx,afi-fm2-wr-bus-width",    .id = AFIFM2_WRCTRL},
> > +     {.reg = "xlnx,afi-fm3-wr-bus-width",    .id = AFIFM3_WRCTRL},
> > +     {.reg = "xlnx,afi-fm4-wr-bus-width",    .id = AFIFM4_WRCTRL},
> > +     {.reg = "xlnx,afi-fm5-wr-bus-width",    .id = AFIFM5_WRCTRL},
> > +     {.reg = "xlnx,afi-fm6-wr-bus-width",    .id = AFIFM6_WRCTRL},
> > +     {.reg = "xlnx,afi-fs-ss0-bus-width",    .id = AFIFS},
> > +     {.reg = "xlnx,afi-fs-ss2-bus-width",    .id = AFIFS_SS2},
> > +     {}
> > +};
> > +
> > +static int zynqmp_afi_config(struct zynqmp_afi *afi_data) {
> > +     struct zynqmp_afi_configreg *cfgptr = afi_cfgreg;
> > +     struct device_node *np = afi_data->of_node;
> > +     u32 afi_ss0_val, afi_ss1_val, bus_width;
> > +     int ret;
> > +
> > +     while (cfgptr->reg) {
> > +             ret = of_property_read_u32(np, cfgptr->reg, &bus_width);
> > +             if (!ret) {
> > +                     if (cfgptr->id == AFIFS_SS2) {
> > +                             if (bus_width == 32)
> > +                                     ret = zynqmp_pm_afi(AFIFS_SS2,
> > +                                                         AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL);
> > +                             else if (bus_width == 64)
> > +                                     ret = zynqmp_pm_afi(AFIFS_SS2,
> > +
> AFIFS_SS0_SS2_BUS_WIDTH_64_CONFIG_VAL);
> > +                             else if (bus_width == 128)
> > +                                     ret = zynqmp_pm_afi(AFIFS_SS2,
> > +
> AFIFS_SS0_SS2_BUS_WIDTH_128_CONFIG_VAL);
> > +                             else
> > +                                     return -EINVAL;
> > +                     } else if (cfgptr->id == AFIFS) {
> > +                             if (bus_width == 32)
> > +                                     afi_ss0_val = AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL;
> > +                             else if (bus_width == 64)
> > +                                     afi_ss0_val =
> AFIFS_SS0_SS2_BUS_WIDTH_64_CONFIG_VAL;
> > +                             else if (bus_width == 128)
> > +                                     afi_ss0_val =
> AFIFS_SS0_SS2_BUS_WIDTH_128_CONFIG_VAL;
> > +                             else
> > +                                     return -EINVAL;
> > +
> > +                             ret = of_property_read_u32(np, "xlnx,afi-fs-ss1-bus-
> width",
> > +                                                        &bus_width);
> > +                             if (!ret) {
> > +                                     if (bus_width == 32)
> > +                                             afi_ss1_val =
> AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL;
> > +                                     else if (bus_width == 64)
> > +                                             afi_ss1_val =
> AFIFS_SS1_BUS_WIDTH_64_CONFIG_VAL;
> > +                                     else if (bus_width == 128)
> > +                                             afi_ss1_val =
> AFIFS_SS1_BUS_WIDTH_128_CONFIG_VAL;
> > +                                     else
> > +                                             return -EINVAL;
> > +
> > +                                     ret = zynqmp_pm_afi(AFIFS, afi_ss1_val |
> afi_ss0_val);
> > +                             }
> > +                     } else {
> > +                             if (bus_width == 32)
> > +                                     ret = zynqmp_pm_afi(cfgptr->id,
> > +                                                         AFIFM_BUS_WIDTH_32_CONFIG_VAL);
> > +                             else if (bus_width == 64)
> > +                                     ret = zynqmp_pm_afi(cfgptr->id,
> > +                                                         AFIFM_BUS_WIDTH_64_CONFIG_VAL);
> > +                             else if (bus_width == 128)
> > +                                     ret = zynqmp_pm_afi(cfgptr->id,
> > +                                                         AFIFM_BUS_WIDTH_128_CONFIG_VAL);
> > +                             else
> > +                                     return -EINVAL;
> > +                     }
> > +             }
> > +             cfgptr++;
> > +     }
> > +
> > +     return 0;
> > +}
> > +
> > +static int zynqmp_afi_enable_set(struct fpga_bridge *bridge, bool
> > +enable) {
> > +     struct device_node *overlay = bridge->info->overlay;
> > +     struct zynqmp_afi *priv = bridge->priv;
> > +     int ret = 0;
> > +
> > +     if (enable) {
> > +             reset_control_reset(priv->resets);
> > +             return 0;
> > +     }
> > +
> > +     of_node_get(overlay);
> > +     priv->of_node =
> > +     of_find_node_with_property(overlay,
> > +                                "xlnx,afi-fm0-rd-bus-width");
> 
> I'm a little confused here. The fpga_image_info.overlay is for fpga-region, but
> from your binding doc this property is for this afi device. You want to add
> another overlay targeting afi dev node during reprograming?
> 

Yes, it uses Overlay's(overlay targeting afi dev node). As I said above for design-to-design AFI configs
relevant to the full region may change and these configs must be set prior to program the full region
once this overlay integrated to the live tree the existing afi config values will be replace with the new one's

> > +     if (priv->of_node)
> > +             ret = zynqmp_afi_config(priv);
> > +     of_node_put(priv->of_node);
> > +
> > +     return ret;
> > +}
> > +
> > +static const struct fpga_bridge_ops zynqmp_afi_br_ops = {
> > +     .enable_set = zynqmp_afi_enable_set, };
> > +
> > +static const struct of_device_id zynqmp_afi_of_match[] = {
> > +     { .compatible =  "xlnx,zynqmp-afi-fpga" },
> > +     { },
> > +};
> > +MODULE_DEVICE_TABLE(of, zynqmp_afi_of_match);
> > +
> > +static int zynqmp_afi_probe(struct platform_device *pdev) {
> > +     struct device *dev = &pdev->dev;
> > +     struct zynqmp_afi *priv;
> > +     struct fpga_bridge *br;
> > +
> > +     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> > +     if (!priv)
> > +             return -ENOMEM;
> > +
> > +     priv->dev = dev;
> > +
> > +     priv->resets =
> devm_reset_control_array_get_optional_exclusive(&pdev->dev);
> > +     if (IS_ERR(priv->resets))
> > +             return PTR_ERR(priv->resets);
> > +
> > +     br = fpga_bridge_register(dev, "Xilinx ZynqMP AFI",
> > +                               &zynqmp_afi_br_ops, priv);
> > +     if (IS_ERR(br)) {
> > +             dev_err(dev, "unable to register Xilinx ZynqMP AFI");
> 
> Need a "\n" at the end?
> 

Will fix.

Regards,
Navakishore.

Re: [PATCH 4/4] fpga: zynqmp: Add afi config driver

[Marco Pagani]

Hi Nava,

On 2022-08-30 11:19, Manne, Nava kishore wrote:
> Hi Yilun,
> 
> 	Please find my response inline.
> 
>> -----Original Message-----
>> From: Xu Yilun <yilun.xu@intel.com>
>> Sent: Saturday, August 27, 2022 5:56 PM
>> To: Manne, Nava kishore <nava.kishore.manne@amd.com>
>> Cc: git (AMD-Xilinx) <git@amd.com>; robh+dt@kernel.org;
>> krzysztof.kozlowski+dt@linaro.org; michal.simek@xilinx.com;
>> mdf@kernel.org; hao.wu@intel.com; trix@redhat.com;
>> p.zabel@pengutronix.de; gregkh@linuxfoundation.org;
>> ronak.jain@xilinx.com; rajan.vaja@xilinx.com;
>> abhyuday.godhasara@xilinx.com; piyush.mehta@xilinx.com;
>> lakshmi.sai.krishna.potthuri@xilinx.com; harsha.harsha@xilinx.com;
>> linus.walleij@linaro.org; nava.manne@xilinx.com;
>> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
>> kernel@vger.kernel.org; linux-fpga@vger.kernel.org
>> Subject: Re: [PATCH 4/4] fpga: zynqmp: Add afi config driver
>>
>> CAUTION: This message has originated from an External Source. Please use
>> proper judgment and caution when opening attachments, clicking links, or
>> responding to this email.
>>
>>
>> On 2022-08-24 at 09:25:42 +0530, Nava kishore Manne wrote:
>>> Add zynqmp AXI FIFO interface(AFI) config driver. This is useful for
>>> the configuration of the PS-PL interface on Zynq US+ MPSoC platform.
>>
>> Please help illustrate how to use the device for FPGA reprogramming, why it
>> should be implemented as an FPGA bridge.
>>
>> From the code I actually didn't see any operation that gates the fpga-region
>> from other part of the machine.
>>
> 
> The Zynq UltraScale MPSoC family consists of a system-on-chip (SoC) style integrated processing system (PS)
> and a Programmable Logic (PL) unit, providing an extensible and flexible SoC solution on a single die. 
> Xilinx Zynq US+ MPSoC connect the PS to the programmable logic (PL) through the AXI port. 
> This AXI port helps to establish the data path between the PS and PL (Here AXI Interface act as a Gating between PS and PL)
> and this AXI port configuration vary from design to design.  In-order to establish the proper communication path between
> PS and PL (Full region),  the AXI port data path should be configured with proper values priories to load the full region.
> 
> Will update the description in v2.

Are you implementing your AFI driver as a Bridge because you want to
change the configuration of the AXI HP interfaces exported by the PS
every time you reconfigure the full fabric?

I understand the need to change the configuration of the PS-PL
interface at each full reconfiguration to ensure that the parameters
of the AXI ports exported by the PS (like the widths of data read
and write channels) matches the configuration of the master AXI ports
exported by the PL design. However, it seems to me that performing this
configuration doesn't fit the role of the FPGA Bridge, whose sole
responsibility should be gating the Region's interface during
reconfiguration.

I think this need could be addressed by adding a new component to the
FPGA subsystem called "FPGA Adapter". The Adapter will be an optional
component associated with a Region like a Bridge. It will be responsible
for changing the configuration of its Region's static interface
(or PS/HPS/DRAM interface for the full FPGA) to match the interface
exported by the specific reconfigurable module (or full static design).
Moreover, besides bus-level properties like address/data width and
protocol conversion, the Adapter could also be used to configure
system-level properties. For instance, the designer may use it to change
the memory access policy for the specific reconfigurable module if it
uses bus mastering.

> 
>>>
>>> Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
>>> ---
>>>  MAINTAINERS               |   6 ++
>>>  drivers/fpga/Kconfig      |  13 +++
>>>  drivers/fpga/Makefile     |   1 +
>>>  drivers/fpga/zynqmp-afi.c | 211
>>> ++++++++++++++++++++++++++++++++++++++
>>>  4 files changed, 231 insertions(+)
>>>  create mode 100644 drivers/fpga/zynqmp-afi.c
>>>
>>> diff --git a/MAINTAINERS b/MAINTAINERS index
>>> 20ffac651214..957e753e6406 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -8032,6 +8032,12 @@ F:     Documentation/fpga/
>>>  F:   drivers/fpga/
>>>  F:   include/linux/fpga/
>>>
>>> +FPGA ZYNQMP PS-PL BRIDGE DRIVER
>>> +M:   Nava kishore Manne <nava.kishore.manne@amd.com>
>>> +S:   Supported
>>> +F:   Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
>>> +F:   drivers/fpga/zynqmp-afi.c
>>> +
>>>  INTEL MAX10 BMC SECURE UPDATES
>>>  M:   Russ Weight <russell.h.weight@intel.com>
>>>  L:   linux-fpga@vger.kernel.org
>>> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index
>>> 6c416955da53..c08794d30fb5 100644
>>> --- a/drivers/fpga/Kconfig
>>> +++ b/drivers/fpga/Kconfig
>>> @@ -130,6 +130,19 @@ config XILINX_PR_DECOUPLER
>>>         reconfiguration, preventing the system deadlock that can
>>>         occur if AXI transactions are interrupted by DFX.
>>>
>>> +config ZYNQMP_AFI
>>> +     tristate "Xilinx ZYNQMP AFI support"
>>> +     depends on FPGA_BRIDGE
>>> +     help
>>> +       Say Y to enable drivers to handle the PS-PL clocks configurations
>>> +       and PS-PL Bus-width. Xilinx Zynq US+ MPSoC connect the PS to the
>>> +       programmable logic (PL) through the AXI port. This AXI port helps
>>> +       to establish the data path between the PS and PL.
>>> +       In-order to establish the proper communication path between PS and
>> PL,
>>> +       the AXI port data path should be configured with the proper Bus-
>> width
>>> +       values and it will also handles the PS-PL reset signals to reset the
>>> +       PL domain.
>>
>> Same concern, please describe its relationship to FPGA reprogramming.
>>
> 
> Same as above.
> Will update the description in v2.
> 
>>> +
>>>  config FPGA_REGION
>>>       tristate "FPGA Region"
>>>       depends on FPGA_BRIDGE
>>> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index
>>> 42ae8b58abce..94cfe60972db 100644
>>> --- a/drivers/fpga/Makefile
>>> +++ b/drivers/fpga/Makefile
>>> @@ -31,6 +31,7 @@ obj-$(CONFIG_FPGA_BRIDGE)           += fpga-bridge.o
>>>  obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE)    += altera-hps2fpga.o altera-
>> fpga2sdram.o
>>>  obj-$(CONFIG_ALTERA_FREEZE_BRIDGE)   += altera-freeze-bridge.o
>>>  obj-$(CONFIG_XILINX_PR_DECOUPLER)    += xilinx-pr-decoupler.o
>>> +obj-$(CONFIG_ZYNQMP_AFI)             += zynqmp-afi.o
>>>
>>>  # High Level Interfaces
>>>  obj-$(CONFIG_FPGA_REGION)            += fpga-region.o
>>> diff --git a/drivers/fpga/zynqmp-afi.c b/drivers/fpga/zynqmp-afi.c new
>>> file mode 100644 index 000000000000..bc975d304039
>>> --- /dev/null
>>> +++ b/drivers/fpga/zynqmp-afi.c
>>> @@ -0,0 +1,211 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Copyright (C) 2022 Xilinx, Inc.
>>> + */
>>> +
>>> +#include <linux/err.h>
>>> +#include <linux/firmware/xlnx-zynqmp.h> #include
>>> +<linux/fpga/fpga-bridge.h> #include <linux/io.h> #include
>>> +<linux/module.h> #include <linux/of.h> #include
>>> +<linux/platform_device.h> #include <linux/reset.h> #include
>>> +<linux/slab.h>
>>> +
>>> +/* Registers and special values for doing register-based operations */
>>> +#define AFI_RDCHAN_CTRL_OFFSET       0x00
>>> +#define AFI_WRCHAN_CTRL_OFFSET       0x14
>>> +#define AFI_BUSWIDTH_MASK    BIT(0)
>>> +
>>> +/**
>>> + * struct zynqmp_afi - AFI register description.
>>> + * @dev: device that owns this.
>>> + * @of_node: Device Tree overlay.
>>> + * @resets: Pointer to the reset control for ps-pl resets.
>>> + */
>>> +struct zynqmp_afi {
>>> +     struct device *dev;
>>> +     struct device_node *of_node;
>>> +     struct reset_control *resets;
>>> +};
>>> +
>>> +/**
>>> + * struct zynqmp_afi_configreg - AFI configuration registers info.
>>> + * @reg:     Name of the AFI configuration register.
>>> + * @id:              Register index value.
>>> + */
>>> +struct zynqmp_afi_configreg {
>>> +     char *reg;
>>> +     u32 id;
>>> +};
>>> +
>>> +static struct zynqmp_afi_configreg afi_cfgreg[] = {
>>> +     {.reg = "xlnx,afi-fm0-rd-bus-width",    .id = AFIFM0_RDCTRL},
>>> +     {.reg = "xlnx,afi-fm1-rd-bus-width",    .id = AFIFM1_RDCTRL},
>>> +     {.reg = "xlnx,afi-fm2-rd-bus-width",    .id = AFIFM2_RDCTRL},
>>> +     {.reg = "xlnx,afi-fm3-rd-bus-width",    .id = AFIFM3_RDCTRL},
>>> +     {.reg = "xlnx,afi-fm4-rd-bus-width",    .id = AFIFM4_RDCTRL},
>>> +     {.reg = "xlnx,afi-fm5-rd-bus-width",    .id = AFIFM5_RDCTRL},
>>> +     {.reg = "xlnx,afi-fm6-rd-bus-width",    .id = AFIFM6_RDCTRL},
>>> +     {.reg = "xlnx,afi-fm0-wr-bus-width",    .id = AFIFM0_WRCTRL},
>>> +     {.reg = "xlnx,afi-fm1-wr-bus-width",    .id = AFIFM1_WRCTRL},
>>> +     {.reg = "xlnx,afi-fm2-wr-bus-width",    .id = AFIFM2_WRCTRL},
>>> +     {.reg = "xlnx,afi-fm3-wr-bus-width",    .id = AFIFM3_WRCTRL},
>>> +     {.reg = "xlnx,afi-fm4-wr-bus-width",    .id = AFIFM4_WRCTRL},
>>> +     {.reg = "xlnx,afi-fm5-wr-bus-width",    .id = AFIFM5_WRCTRL},
>>> +     {.reg = "xlnx,afi-fm6-wr-bus-width",    .id = AFIFM6_WRCTRL},
>>> +     {.reg = "xlnx,afi-fs-ss0-bus-width",    .id = AFIFS},
>>> +     {.reg = "xlnx,afi-fs-ss2-bus-width",    .id = AFIFS_SS2},
>>> +     {}
>>> +};
>>> +
>>> +static int zynqmp_afi_config(struct zynqmp_afi *afi_data) {
>>> +     struct zynqmp_afi_configreg *cfgptr = afi_cfgreg;
>>> +     struct device_node *np = afi_data->of_node;
>>> +     u32 afi_ss0_val, afi_ss1_val, bus_width;
>>> +     int ret;
>>> +
>>> +     while (cfgptr->reg) {
>>> +             ret = of_property_read_u32(np, cfgptr->reg, &bus_width);
>>> +             if (!ret) {
>>> +                     if (cfgptr->id == AFIFS_SS2) {
>>> +                             if (bus_width == 32)
>>> +                                     ret = zynqmp_pm_afi(AFIFS_SS2,
>>> +                                                         AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL);
>>> +                             else if (bus_width == 64)
>>> +                                     ret = zynqmp_pm_afi(AFIFS_SS2,
>>> +
>> AFIFS_SS0_SS2_BUS_WIDTH_64_CONFIG_VAL);
>>> +                             else if (bus_width == 128)
>>> +                                     ret = zynqmp_pm_afi(AFIFS_SS2,
>>> +
>> AFIFS_SS0_SS2_BUS_WIDTH_128_CONFIG_VAL);
>>> +                             else
>>> +                                     return -EINVAL;
>>> +                     } else if (cfgptr->id == AFIFS) {
>>> +                             if (bus_width == 32)
>>> +                                     afi_ss0_val = AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL;
>>> +                             else if (bus_width == 64)
>>> +                                     afi_ss0_val =
>> AFIFS_SS0_SS2_BUS_WIDTH_64_CONFIG_VAL;
>>> +                             else if (bus_width == 128)
>>> +                                     afi_ss0_val =
>> AFIFS_SS0_SS2_BUS_WIDTH_128_CONFIG_VAL;
>>> +                             else
>>> +                                     return -EINVAL;
>>> +
>>> +                             ret = of_property_read_u32(np, "xlnx,afi-fs-ss1-bus-
>> width",
>>> +                                                        &bus_width);
>>> +                             if (!ret) {
>>> +                                     if (bus_width == 32)
>>> +                                             afi_ss1_val =
>> AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL;
>>> +                                     else if (bus_width == 64)
>>> +                                             afi_ss1_val =
>> AFIFS_SS1_BUS_WIDTH_64_CONFIG_VAL;
>>> +                                     else if (bus_width == 128)
>>> +                                             afi_ss1_val =
>> AFIFS_SS1_BUS_WIDTH_128_CONFIG_VAL;
>>> +                                     else
>>> +                                             return -EINVAL;
>>> +
>>> +                                     ret = zynqmp_pm_afi(AFIFS, afi_ss1_val |
>> afi_ss0_val);
>>> +                             }
>>> +                     } else {
>>> +                             if (bus_width == 32)
>>> +                                     ret = zynqmp_pm_afi(cfgptr->id,
>>> +                                                         AFIFM_BUS_WIDTH_32_CONFIG_VAL);
>>> +                             else if (bus_width == 64)
>>> +                                     ret = zynqmp_pm_afi(cfgptr->id,
>>> +                                                         AFIFM_BUS_WIDTH_64_CONFIG_VAL);
>>> +                             else if (bus_width == 128)
>>> +                                     ret = zynqmp_pm_afi(cfgptr->id,
>>> +                                                         AFIFM_BUS_WIDTH_128_CONFIG_VAL);
>>> +                             else
>>> +                                     return -EINVAL;
>>> +                     }
>>> +             }
>>> +             cfgptr++;
>>> +     }
>>> +
>>> +     return 0;
>>> +}
>>> +
>>> +static int zynqmp_afi_enable_set(struct fpga_bridge *bridge, bool
>>> +enable) {
>>> +     struct device_node *overlay = bridge->info->overlay;
>>> +     struct zynqmp_afi *priv = bridge->priv;
>>> +     int ret = 0;
>>> +
>>> +     if (enable) {
>>> +             reset_control_reset(priv->resets);
>>> +             return 0;
>>> +     }
>>> +
>>> +     of_node_get(overlay);
>>> +     priv->of_node =
>>> +     of_find_node_with_property(overlay,
>>> +                                "xlnx,afi-fm0-rd-bus-width");
>>
>> I'm a little confused here. The fpga_image_info.overlay is for fpga-region, but
>> from your binding doc this property is for this afi device. You want to add
>> another overlay targeting afi dev node during reprograming?
>>
> 
> Yes, it uses Overlay's(overlay targeting afi dev node). As I said above for design-to-design AFI configs
> relevant to the full region may change and these configs must be set prior to program the full region
> once this overlay integrated to the live tree the existing afi config values will be replace with the new one's
> 
>>> +     if (priv->of_node)
>>> +             ret = zynqmp_afi_config(priv);
>>> +     of_node_put(priv->of_node);
>>> +
>>> +     return ret;
>>> +}
>>> +
>>> +static const struct fpga_bridge_ops zynqmp_afi_br_ops = {
>>> +     .enable_set = zynqmp_afi_enable_set, };
>>> +
>>> +static const struct of_device_id zynqmp_afi_of_match[] = {
>>> +     { .compatible =  "xlnx,zynqmp-afi-fpga" },
>>> +     { },
>>> +};
>>> +MODULE_DEVICE_TABLE(of, zynqmp_afi_of_match);
>>> +
>>> +static int zynqmp_afi_probe(struct platform_device *pdev) {
>>> +     struct device *dev = &pdev->dev;
>>> +     struct zynqmp_afi *priv;
>>> +     struct fpga_bridge *br;
>>> +
>>> +     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
>>> +     if (!priv)
>>> +             return -ENOMEM;
>>> +
>>> +     priv->dev = dev;
>>> +
>>> +     priv->resets =
>> devm_reset_control_array_get_optional_exclusive(&pdev->dev);
>>> +     if (IS_ERR(priv->resets))
>>> +             return PTR_ERR(priv->resets);
>>> +
>>> +     br = fpga_bridge_register(dev, "Xilinx ZynqMP AFI",
>>> +                               &zynqmp_afi_br_ops, priv);
>>> +     if (IS_ERR(br)) {
>>> +             dev_err(dev, "unable to register Xilinx ZynqMP AFI");
>>
>> Need a "\n" at the end?
>>
> 
> Will fix.
> 
> Regards,
> Navakishore.
> 

Thanks,
Marco

Re: [PATCH 4/4] fpga: zynqmp: Add afi config driver

[Xu Yilun]

On 2022-09-01 at 11:53:29 +0200, Marco Pagani wrote:
> Hi Nava,
> 
> On 2022-08-30 11:19, Manne, Nava kishore wrote:
> > Hi Yilun,
> > 
> > 	Please find my response inline.
> > 
> >> -----Original Message-----
> >> From: Xu Yilun <yilun.xu@intel.com>
> >> Sent: Saturday, August 27, 2022 5:56 PM
> >> To: Manne, Nava kishore <nava.kishore.manne@amd.com>
> >> Cc: git (AMD-Xilinx) <git@amd.com>; robh+dt@kernel.org;
> >> krzysztof.kozlowski+dt@linaro.org; michal.simek@xilinx.com;
> >> mdf@kernel.org; hao.wu@intel.com; trix@redhat.com;
> >> p.zabel@pengutronix.de; gregkh@linuxfoundation.org;
> >> ronak.jain@xilinx.com; rajan.vaja@xilinx.com;
> >> abhyuday.godhasara@xilinx.com; piyush.mehta@xilinx.com;
> >> lakshmi.sai.krishna.potthuri@xilinx.com; harsha.harsha@xilinx.com;
> >> linus.walleij@linaro.org; nava.manne@xilinx.com;
> >> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> >> kernel@vger.kernel.org; linux-fpga@vger.kernel.org
> >> Subject: Re: [PATCH 4/4] fpga: zynqmp: Add afi config driver
> >>
> >> CAUTION: This message has originated from an External Source. Please use
> >> proper judgment and caution when opening attachments, clicking links, or
> >> responding to this email.
> >>
> >>
> >> On 2022-08-24 at 09:25:42 +0530, Nava kishore Manne wrote:
> >>> Add zynqmp AXI FIFO interface(AFI) config driver. This is useful for
> >>> the configuration of the PS-PL interface on Zynq US+ MPSoC platform.
> >>
> >> Please help illustrate how to use the device for FPGA reprogramming, why it
> >> should be implemented as an FPGA bridge.
> >>
> >> From the code I actually didn't see any operation that gates the fpga-region
> >> from other part of the machine.
> >>
> > 
> > The Zynq UltraScale MPSoC family consists of a system-on-chip (SoC) style integrated processing system (PS)
> > and a Programmable Logic (PL) unit, providing an extensible and flexible SoC solution on a single die. 
> > Xilinx Zynq US+ MPSoC connect the PS to the programmable logic (PL) through the AXI port. 
> > This AXI port helps to establish the data path between the PS and PL (Here AXI Interface act as a Gating between PS and PL)
> > and this AXI port configuration vary from design to design.  In-order to establish the proper communication path between
> > PS and PL (Full region),  the AXI port data path should be configured with proper values priories to load the full region.
> > 
> > Will update the description in v2.
> 
> Are you implementing your AFI driver as a Bridge because you want to
> change the configuration of the AXI HP interfaces exported by the PS
> every time you reconfigure the full fabric?
> 
> I understand the need to change the configuration of the PS-PL
> interface at each full reconfiguration to ensure that the parameters
> of the AXI ports exported by the PS (like the widths of data read
> and write channels) matches the configuration of the master AXI ports
> exported by the PL design. However, it seems to me that performing this
> configuration doesn't fit the role of the FPGA Bridge, whose sole
> responsibility should be gating the Region's interface during
> reconfiguration.
> 
> I think this need could be addressed by adding a new component to the
> FPGA subsystem called "FPGA Adapter". The Adapter will be an optional
> component associated with a Region like a Bridge. It will be responsible
> for changing the configuration of its Region's static interface
> (or PS/HPS/DRAM interface for the full FPGA) to match the interface
> exported by the specific reconfigurable module (or full static design).

I saw the Documentation/driver_api/interconnect.rst, but didn't look deep
into it. For this AFI case, it sets the bus width, is it OK to use it?

Thanks,
Yilun

> Moreover, besides bus-level properties like address/data width and
> protocol conversion, the Adapter could also be used to configure
> system-level properties. For instance, the designer may use it to change
> the memory access policy for the specific reconfigurable module if it
> uses bus mastering.
> 
> > 
> >>>
> >>> Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
> >>> ---
> >>>  MAINTAINERS               |   6 ++
> >>>  drivers/fpga/Kconfig      |  13 +++
> >>>  drivers/fpga/Makefile     |   1 +
> >>>  drivers/fpga/zynqmp-afi.c | 211
> >>> ++++++++++++++++++++++++++++++++++++++
> >>>  4 files changed, 231 insertions(+)
> >>>  create mode 100644 drivers/fpga/zynqmp-afi.c
> >>>
> >>> diff --git a/MAINTAINERS b/MAINTAINERS index
> >>> 20ffac651214..957e753e6406 100644
> >>> --- a/MAINTAINERS
> >>> +++ b/MAINTAINERS
> >>> @@ -8032,6 +8032,12 @@ F:     Documentation/fpga/
> >>>  F:   drivers/fpga/
> >>>  F:   include/linux/fpga/
> >>>
> >>> +FPGA ZYNQMP PS-PL BRIDGE DRIVER
> >>> +M:   Nava kishore Manne <nava.kishore.manne@amd.com>
> >>> +S:   Supported
> >>> +F:   Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
> >>> +F:   drivers/fpga/zynqmp-afi.c
> >>> +
> >>>  INTEL MAX10 BMC SECURE UPDATES
> >>>  M:   Russ Weight <russell.h.weight@intel.com>
> >>>  L:   linux-fpga@vger.kernel.org
> >>> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index
> >>> 6c416955da53..c08794d30fb5 100644
> >>> --- a/drivers/fpga/Kconfig
> >>> +++ b/drivers/fpga/Kconfig
> >>> @@ -130,6 +130,19 @@ config XILINX_PR_DECOUPLER
> >>>         reconfiguration, preventing the system deadlock that can
> >>>         occur if AXI transactions are interrupted by DFX.
> >>>
> >>> +config ZYNQMP_AFI
> >>> +     tristate "Xilinx ZYNQMP AFI support"
> >>> +     depends on FPGA_BRIDGE
> >>> +     help
> >>> +       Say Y to enable drivers to handle the PS-PL clocks configurations
> >>> +       and PS-PL Bus-width. Xilinx Zynq US+ MPSoC connect the PS to the
> >>> +       programmable logic (PL) through the AXI port. This AXI port helps
> >>> +       to establish the data path between the PS and PL.
> >>> +       In-order to establish the proper communication path between PS and
> >> PL,
> >>> +       the AXI port data path should be configured with the proper Bus-
> >> width
> >>> +       values and it will also handles the PS-PL reset signals to reset the
> >>> +       PL domain.
> >>
> >> Same concern, please describe its relationship to FPGA reprogramming.
> >>
> > 
> > Same as above.
> > Will update the description in v2.
> > 
> >>> +
> >>>  config FPGA_REGION
> >>>       tristate "FPGA Region"
> >>>       depends on FPGA_BRIDGE
> >>> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index
> >>> 42ae8b58abce..94cfe60972db 100644
> >>> --- a/drivers/fpga/Makefile
> >>> +++ b/drivers/fpga/Makefile
> >>> @@ -31,6 +31,7 @@ obj-$(CONFIG_FPGA_BRIDGE)           += fpga-bridge.o
> >>>  obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE)    += altera-hps2fpga.o altera-
> >> fpga2sdram.o
> >>>  obj-$(CONFIG_ALTERA_FREEZE_BRIDGE)   += altera-freeze-bridge.o
> >>>  obj-$(CONFIG_XILINX_PR_DECOUPLER)    += xilinx-pr-decoupler.o
> >>> +obj-$(CONFIG_ZYNQMP_AFI)             += zynqmp-afi.o
> >>>
> >>>  # High Level Interfaces
> >>>  obj-$(CONFIG_FPGA_REGION)            += fpga-region.o
> >>> diff --git a/drivers/fpga/zynqmp-afi.c b/drivers/fpga/zynqmp-afi.c new
> >>> file mode 100644 index 000000000000..bc975d304039
> >>> --- /dev/null
> >>> +++ b/drivers/fpga/zynqmp-afi.c
> >>> @@ -0,0 +1,211 @@
> >>> +// SPDX-License-Identifier: GPL-2.0
> >>> +/*
> >>> + * Copyright (C) 2022 Xilinx, Inc.
> >>> + */
> >>> +
> >>> +#include <linux/err.h>
> >>> +#include <linux/firmware/xlnx-zynqmp.h> #include
> >>> +<linux/fpga/fpga-bridge.h> #include <linux/io.h> #include
> >>> +<linux/module.h> #include <linux/of.h> #include
> >>> +<linux/platform_device.h> #include <linux/reset.h> #include
> >>> +<linux/slab.h>
> >>> +
> >>> +/* Registers and special values for doing register-based operations */
> >>> +#define AFI_RDCHAN_CTRL_OFFSET       0x00
> >>> +#define AFI_WRCHAN_CTRL_OFFSET       0x14
> >>> +#define AFI_BUSWIDTH_MASK    BIT(0)
> >>> +
> >>> +/**
> >>> + * struct zynqmp_afi - AFI register description.
> >>> + * @dev: device that owns this.
> >>> + * @of_node: Device Tree overlay.
> >>> + * @resets: Pointer to the reset control for ps-pl resets.
> >>> + */
> >>> +struct zynqmp_afi {
> >>> +     struct device *dev;
> >>> +     struct device_node *of_node;
> >>> +     struct reset_control *resets;
> >>> +};
> >>> +
> >>> +/**
> >>> + * struct zynqmp_afi_configreg - AFI configuration registers info.
> >>> + * @reg:     Name of the AFI configuration register.
> >>> + * @id:              Register index value.
> >>> + */
> >>> +struct zynqmp_afi_configreg {
> >>> +     char *reg;
> >>> +     u32 id;
> >>> +};
> >>> +
> >>> +static struct zynqmp_afi_configreg afi_cfgreg[] = {
> >>> +     {.reg = "xlnx,afi-fm0-rd-bus-width",    .id = AFIFM0_RDCTRL},
> >>> +     {.reg = "xlnx,afi-fm1-rd-bus-width",    .id = AFIFM1_RDCTRL},
> >>> +     {.reg = "xlnx,afi-fm2-rd-bus-width",    .id = AFIFM2_RDCTRL},
> >>> +     {.reg = "xlnx,afi-fm3-rd-bus-width",    .id = AFIFM3_RDCTRL},
> >>> +     {.reg = "xlnx,afi-fm4-rd-bus-width",    .id = AFIFM4_RDCTRL},
> >>> +     {.reg = "xlnx,afi-fm5-rd-bus-width",    .id = AFIFM5_RDCTRL},
> >>> +     {.reg = "xlnx,afi-fm6-rd-bus-width",    .id = AFIFM6_RDCTRL},
> >>> +     {.reg = "xlnx,afi-fm0-wr-bus-width",    .id = AFIFM0_WRCTRL},
> >>> +     {.reg = "xlnx,afi-fm1-wr-bus-width",    .id = AFIFM1_WRCTRL},
> >>> +     {.reg = "xlnx,afi-fm2-wr-bus-width",    .id = AFIFM2_WRCTRL},
> >>> +     {.reg = "xlnx,afi-fm3-wr-bus-width",    .id = AFIFM3_WRCTRL},
> >>> +     {.reg = "xlnx,afi-fm4-wr-bus-width",    .id = AFIFM4_WRCTRL},
> >>> +     {.reg = "xlnx,afi-fm5-wr-bus-width",    .id = AFIFM5_WRCTRL},
> >>> +     {.reg = "xlnx,afi-fm6-wr-bus-width",    .id = AFIFM6_WRCTRL},
> >>> +     {.reg = "xlnx,afi-fs-ss0-bus-width",    .id = AFIFS},
> >>> +     {.reg = "xlnx,afi-fs-ss2-bus-width",    .id = AFIFS_SS2},
> >>> +     {}
> >>> +};
> >>> +
> >>> +static int zynqmp_afi_config(struct zynqmp_afi *afi_data) {
> >>> +     struct zynqmp_afi_configreg *cfgptr = afi_cfgreg;
> >>> +     struct device_node *np = afi_data->of_node;
> >>> +     u32 afi_ss0_val, afi_ss1_val, bus_width;
> >>> +     int ret;
> >>> +
> >>> +     while (cfgptr->reg) {
> >>> +             ret = of_property_read_u32(np, cfgptr->reg, &bus_width);
> >>> +             if (!ret) {
> >>> +                     if (cfgptr->id == AFIFS_SS2) {
> >>> +                             if (bus_width == 32)
> >>> +                                     ret = zynqmp_pm_afi(AFIFS_SS2,
> >>> +                                                         AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL);
> >>> +                             else if (bus_width == 64)
> >>> +                                     ret = zynqmp_pm_afi(AFIFS_SS2,
> >>> +
> >> AFIFS_SS0_SS2_BUS_WIDTH_64_CONFIG_VAL);
> >>> +                             else if (bus_width == 128)
> >>> +                                     ret = zynqmp_pm_afi(AFIFS_SS2,
> >>> +
> >> AFIFS_SS0_SS2_BUS_WIDTH_128_CONFIG_VAL);
> >>> +                             else
> >>> +                                     return -EINVAL;
> >>> +                     } else if (cfgptr->id == AFIFS) {
> >>> +                             if (bus_width == 32)
> >>> +                                     afi_ss0_val = AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL;
> >>> +                             else if (bus_width == 64)
> >>> +                                     afi_ss0_val =
> >> AFIFS_SS0_SS2_BUS_WIDTH_64_CONFIG_VAL;
> >>> +                             else if (bus_width == 128)
> >>> +                                     afi_ss0_val =
> >> AFIFS_SS0_SS2_BUS_WIDTH_128_CONFIG_VAL;
> >>> +                             else
> >>> +                                     return -EINVAL;
> >>> +
> >>> +                             ret = of_property_read_u32(np, "xlnx,afi-fs-ss1-bus-
> >> width",
> >>> +                                                        &bus_width);
> >>> +                             if (!ret) {
> >>> +                                     if (bus_width == 32)
> >>> +                                             afi_ss1_val =
> >> AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL;
> >>> +                                     else if (bus_width == 64)
> >>> +                                             afi_ss1_val =
> >> AFIFS_SS1_BUS_WIDTH_64_CONFIG_VAL;
> >>> +                                     else if (bus_width == 128)
> >>> +                                             afi_ss1_val =
> >> AFIFS_SS1_BUS_WIDTH_128_CONFIG_VAL;
> >>> +                                     else
> >>> +                                             return -EINVAL;
> >>> +
> >>> +                                     ret = zynqmp_pm_afi(AFIFS, afi_ss1_val |
> >> afi_ss0_val);
> >>> +                             }
> >>> +                     } else {
> >>> +                             if (bus_width == 32)
> >>> +                                     ret = zynqmp_pm_afi(cfgptr->id,
> >>> +                                                         AFIFM_BUS_WIDTH_32_CONFIG_VAL);
> >>> +                             else if (bus_width == 64)
> >>> +                                     ret = zynqmp_pm_afi(cfgptr->id,
> >>> +                                                         AFIFM_BUS_WIDTH_64_CONFIG_VAL);
> >>> +                             else if (bus_width == 128)
> >>> +                                     ret = zynqmp_pm_afi(cfgptr->id,
> >>> +                                                         AFIFM_BUS_WIDTH_128_CONFIG_VAL);
> >>> +                             else
> >>> +                                     return -EINVAL;
> >>> +                     }
> >>> +             }
> >>> +             cfgptr++;
> >>> +     }
> >>> +
> >>> +     return 0;
> >>> +}
> >>> +
> >>> +static int zynqmp_afi_enable_set(struct fpga_bridge *bridge, bool
> >>> +enable) {
> >>> +     struct device_node *overlay = bridge->info->overlay;
> >>> +     struct zynqmp_afi *priv = bridge->priv;
> >>> +     int ret = 0;
> >>> +
> >>> +     if (enable) {
> >>> +             reset_control_reset(priv->resets);
> >>> +             return 0;
> >>> +     }
> >>> +
> >>> +     of_node_get(overlay);
> >>> +     priv->of_node =
> >>> +     of_find_node_with_property(overlay,
> >>> +                                "xlnx,afi-fm0-rd-bus-width");
> >>
> >> I'm a little confused here. The fpga_image_info.overlay is for fpga-region, but
> >> from your binding doc this property is for this afi device. You want to add
> >> another overlay targeting afi dev node during reprograming?
> >>
> > 
> > Yes, it uses Overlay's(overlay targeting afi dev node). As I said above for design-to-design AFI configs
> > relevant to the full region may change and these configs must be set prior to program the full region
> > once this overlay integrated to the live tree the existing afi config values will be replace with the new one's
> > 
> >>> +     if (priv->of_node)
> >>> +             ret = zynqmp_afi_config(priv);
> >>> +     of_node_put(priv->of_node);
> >>> +
> >>> +     return ret;
> >>> +}
> >>> +
> >>> +static const struct fpga_bridge_ops zynqmp_afi_br_ops = {
> >>> +     .enable_set = zynqmp_afi_enable_set, };
> >>> +
> >>> +static const struct of_device_id zynqmp_afi_of_match[] = {
> >>> +     { .compatible =  "xlnx,zynqmp-afi-fpga" },
> >>> +     { },
> >>> +};
> >>> +MODULE_DEVICE_TABLE(of, zynqmp_afi_of_match);
> >>> +
> >>> +static int zynqmp_afi_probe(struct platform_device *pdev) {
> >>> +     struct device *dev = &pdev->dev;
> >>> +     struct zynqmp_afi *priv;
> >>> +     struct fpga_bridge *br;
> >>> +
> >>> +     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> >>> +     if (!priv)
> >>> +             return -ENOMEM;
> >>> +
> >>> +     priv->dev = dev;
> >>> +
> >>> +     priv->resets =
> >> devm_reset_control_array_get_optional_exclusive(&pdev->dev);
> >>> +     if (IS_ERR(priv->resets))
> >>> +             return PTR_ERR(priv->resets);
> >>> +
> >>> +     br = fpga_bridge_register(dev, "Xilinx ZynqMP AFI",
> >>> +                               &zynqmp_afi_br_ops, priv);
> >>> +     if (IS_ERR(br)) {
> >>> +             dev_err(dev, "unable to register Xilinx ZynqMP AFI");
> >>
> >> Need a "\n" at the end?
> >>
> > 
> > Will fix.
> > 
> > Regards,
> > Navakishore.
> > 
> 
> Thanks,
> Marco
> 

Re: [PATCH 4/4] fpga: zynqmp: Add afi config driver

[Marco Pagani]

On 2022-09-03 19:44, Xu Yilun wrote:
> On 2022-09-01 at 11:53:29 +0200, Marco Pagani wrote:
>> Hi Nava,
>>
>> On 2022-08-30 11:19, Manne, Nava kishore wrote:
>>> Hi Yilun,
>>>
>>> 	Please find my response inline.
>>>
>>>> -----Original Message-----
>>>> From: Xu Yilun <yilun.xu@intel.com>
>>>> Sent: Saturday, August 27, 2022 5:56 PM
>>>> To: Manne, Nava kishore <nava.kishore.manne@amd.com>
>>>> Cc: git (AMD-Xilinx) <git@amd.com>; robh+dt@kernel.org;
>>>> krzysztof.kozlowski+dt@linaro.org; michal.simek@xilinx.com;
>>>> mdf@kernel.org; hao.wu@intel.com; trix@redhat.com;
>>>> p.zabel@pengutronix.de; gregkh@linuxfoundation.org;
>>>> ronak.jain@xilinx.com; rajan.vaja@xilinx.com;
>>>> abhyuday.godhasara@xilinx.com; piyush.mehta@xilinx.com;
>>>> lakshmi.sai.krishna.potthuri@xilinx.com; harsha.harsha@xilinx.com;
>>>> linus.walleij@linaro.org; nava.manne@xilinx.com;
>>>> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
>>>> kernel@vger.kernel.org; linux-fpga@vger.kernel.org
>>>> Subject: Re: [PATCH 4/4] fpga: zynqmp: Add afi config driver
>>>>
>>>> CAUTION: This message has originated from an External Source. Please use
>>>> proper judgment and caution when opening attachments, clicking links, or
>>>> responding to this email.
>>>>
>>>>
>>>> On 2022-08-24 at 09:25:42 +0530, Nava kishore Manne wrote:
>>>>> Add zynqmp AXI FIFO interface(AFI) config driver. This is useful for
>>>>> the configuration of the PS-PL interface on Zynq US+ MPSoC platform.
>>>>
>>>> Please help illustrate how to use the device for FPGA reprogramming, why it
>>>> should be implemented as an FPGA bridge.
>>>>
>>>> From the code I actually didn't see any operation that gates the fpga-region
>>>> from other part of the machine.
>>>>
>>>
>>> The Zynq UltraScale MPSoC family consists of a system-on-chip (SoC) style integrated processing system (PS)
>>> and a Programmable Logic (PL) unit, providing an extensible and flexible SoC solution on a single die. 
>>> Xilinx Zynq US+ MPSoC connect the PS to the programmable logic (PL) through the AXI port. 
>>> This AXI port helps to establish the data path between the PS and PL (Here AXI Interface act as a Gating between PS and PL)
>>> and this AXI port configuration vary from design to design.  In-order to establish the proper communication path between
>>> PS and PL (Full region),  the AXI port data path should be configured with proper values priories to load the full region.
>>>
>>> Will update the description in v2.
>>
>> Are you implementing your AFI driver as a Bridge because you want to
>> change the configuration of the AXI HP interfaces exported by the PS
>> every time you reconfigure the full fabric?
>>
>> I understand the need to change the configuration of the PS-PL
>> interface at each full reconfiguration to ensure that the parameters
>> of the AXI ports exported by the PS (like the widths of data read
>> and write channels) matches the configuration of the master AXI ports
>> exported by the PL design. However, it seems to me that performing this
>> configuration doesn't fit the role of the FPGA Bridge, whose sole
>> responsibility should be gating the Region's interface during
>> reconfiguration.
>>
>> I think this need could be addressed by adding a new component to the
>> FPGA subsystem called "FPGA Adapter". The Adapter will be an optional
>> component associated with a Region like a Bridge. It will be responsible
>> for changing the configuration of its Region's static interface
>> (or PS/HPS/DRAM interface for the full FPGA) to match the interface
>> exported by the specific reconfigurable module (or full static design).
> 
> I saw the Documentation/driver_api/interconnect.rst, but didn't look deep
> into it. For this AFI case, it sets the bus width, is it OK to use it?
> 
> Thanks,
> Yilun

Thanks for pointing me to the interconnect subsystem. I'm currently
investigating if it's possible to implement a driver for the AFI
(and possibly other PS interconnects with their QoS regulators)
using the subsystem.
Thanks,
Marco

> 
>> Moreover, besides bus-level properties like address/data width and
>> protocol conversion, the Adapter could also be used to configure
>> system-level properties. For instance, the designer may use it to change
>> the memory access policy for the specific reconfigurable module if it
>> uses bus mastering.
>>
>>>
>>>>>
>>>>> Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
>>>>> ---
>>>>>  MAINTAINERS               |   6 ++
>>>>>  drivers/fpga/Kconfig      |  13 +++
>>>>>  drivers/fpga/Makefile     |   1 +
>>>>>  drivers/fpga/zynqmp-afi.c | 211
>>>>> ++++++++++++++++++++++++++++++++++++++
>>>>>  4 files changed, 231 insertions(+)
>>>>>  create mode 100644 drivers/fpga/zynqmp-afi.c
>>>>>
>>>>> diff --git a/MAINTAINERS b/MAINTAINERS index
>>>>> 20ffac651214..957e753e6406 100644
>>>>> --- a/MAINTAINERS
>>>>> +++ b/MAINTAINERS
>>>>> @@ -8032,6 +8032,12 @@ F:     Documentation/fpga/
>>>>>  F:   drivers/fpga/
>>>>>  F:   include/linux/fpga/
>>>>>
>>>>> +FPGA ZYNQMP PS-PL BRIDGE DRIVER
>>>>> +M:   Nava kishore Manne <nava.kishore.manne@amd.com>
>>>>> +S:   Supported
>>>>> +F:   Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
>>>>> +F:   drivers/fpga/zynqmp-afi.c
>>>>> +
>>>>>  INTEL MAX10 BMC SECURE UPDATES
>>>>>  M:   Russ Weight <russell.h.weight@intel.com>
>>>>>  L:   linux-fpga@vger.kernel.org
>>>>> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index
>>>>> 6c416955da53..c08794d30fb5 100644
>>>>> --- a/drivers/fpga/Kconfig
>>>>> +++ b/drivers/fpga/Kconfig
>>>>> @@ -130,6 +130,19 @@ config XILINX_PR_DECOUPLER
>>>>>         reconfiguration, preventing the system deadlock that can
>>>>>         occur if AXI transactions are interrupted by DFX.
>>>>>
>>>>> +config ZYNQMP_AFI
>>>>> +     tristate "Xilinx ZYNQMP AFI support"
>>>>> +     depends on FPGA_BRIDGE
>>>>> +     help
>>>>> +       Say Y to enable drivers to handle the PS-PL clocks configurations
>>>>> +       and PS-PL Bus-width. Xilinx Zynq US+ MPSoC connect the PS to the
>>>>> +       programmable logic (PL) through the AXI port. This AXI port helps
>>>>> +       to establish the data path between the PS and PL.
>>>>> +       In-order to establish the proper communication path between PS and
>>>> PL,
>>>>> +       the AXI port data path should be configured with the proper Bus-
>>>> width
>>>>> +       values and it will also handles the PS-PL reset signals to reset the
>>>>> +       PL domain.
>>>>
>>>> Same concern, please describe its relationship to FPGA reprogramming.
>>>>
>>>
>>> Same as above.
>>> Will update the description in v2.
>>>
>>>>> +
>>>>>  config FPGA_REGION
>>>>>       tristate "FPGA Region"
>>>>>       depends on FPGA_BRIDGE
>>>>> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index
>>>>> 42ae8b58abce..94cfe60972db 100644
>>>>> --- a/drivers/fpga/Makefile
>>>>> +++ b/drivers/fpga/Makefile
>>>>> @@ -31,6 +31,7 @@ obj-$(CONFIG_FPGA_BRIDGE)           += fpga-bridge.o
>>>>>  obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE)    += altera-hps2fpga.o altera-
>>>> fpga2sdram.o
>>>>>  obj-$(CONFIG_ALTERA_FREEZE_BRIDGE)   += altera-freeze-bridge.o
>>>>>  obj-$(CONFIG_XILINX_PR_DECOUPLER)    += xilinx-pr-decoupler.o
>>>>> +obj-$(CONFIG_ZYNQMP_AFI)             += zynqmp-afi.o
>>>>>
>>>>>  # High Level Interfaces
>>>>>  obj-$(CONFIG_FPGA_REGION)            += fpga-region.o
>>>>> diff --git a/drivers/fpga/zynqmp-afi.c b/drivers/fpga/zynqmp-afi.c new
>>>>> file mode 100644 index 000000000000..bc975d304039
>>>>> --- /dev/null
>>>>> +++ b/drivers/fpga/zynqmp-afi.c
>>>>> @@ -0,0 +1,211 @@
>>>>> +// SPDX-License-Identifier: GPL-2.0
>>>>> +/*
>>>>> + * Copyright (C) 2022 Xilinx, Inc.
>>>>> + */
>>>>> +
>>>>> +#include <linux/err.h>
>>>>> +#include <linux/firmware/xlnx-zynqmp.h> #include
>>>>> +<linux/fpga/fpga-bridge.h> #include <linux/io.h> #include
>>>>> +<linux/module.h> #include <linux/of.h> #include
>>>>> +<linux/platform_device.h> #include <linux/reset.h> #include
>>>>> +<linux/slab.h>
>>>>> +
>>>>> +/* Registers and special values for doing register-based operations */
>>>>> +#define AFI_RDCHAN_CTRL_OFFSET       0x00
>>>>> +#define AFI_WRCHAN_CTRL_OFFSET       0x14
>>>>> +#define AFI_BUSWIDTH_MASK    BIT(0)
>>>>> +
>>>>> +/**
>>>>> + * struct zynqmp_afi - AFI register description.
>>>>> + * @dev: device that owns this.
>>>>> + * @of_node: Device Tree overlay.
>>>>> + * @resets: Pointer to the reset control for ps-pl resets.
>>>>> + */
>>>>> +struct zynqmp_afi {
>>>>> +     struct device *dev;
>>>>> +     struct device_node *of_node;
>>>>> +     struct reset_control *resets;
>>>>> +};
>>>>> +
>>>>> +/**
>>>>> + * struct zynqmp_afi_configreg - AFI configuration registers info.
>>>>> + * @reg:     Name of the AFI configuration register.
>>>>> + * @id:              Register index value.
>>>>> + */
>>>>> +struct zynqmp_afi_configreg {
>>>>> +     char *reg;
>>>>> +     u32 id;
>>>>> +};
>>>>> +
>>>>> +static struct zynqmp_afi_configreg afi_cfgreg[] = {
>>>>> +     {.reg = "xlnx,afi-fm0-rd-bus-width",    .id = AFIFM0_RDCTRL},
>>>>> +     {.reg = "xlnx,afi-fm1-rd-bus-width",    .id = AFIFM1_RDCTRL},
>>>>> +     {.reg = "xlnx,afi-fm2-rd-bus-width",    .id = AFIFM2_RDCTRL},
>>>>> +     {.reg = "xlnx,afi-fm3-rd-bus-width",    .id = AFIFM3_RDCTRL},
>>>>> +     {.reg = "xlnx,afi-fm4-rd-bus-width",    .id = AFIFM4_RDCTRL},
>>>>> +     {.reg = "xlnx,afi-fm5-rd-bus-width",    .id = AFIFM5_RDCTRL},
>>>>> +     {.reg = "xlnx,afi-fm6-rd-bus-width",    .id = AFIFM6_RDCTRL},
>>>>> +     {.reg = "xlnx,afi-fm0-wr-bus-width",    .id = AFIFM0_WRCTRL},
>>>>> +     {.reg = "xlnx,afi-fm1-wr-bus-width",    .id = AFIFM1_WRCTRL},
>>>>> +     {.reg = "xlnx,afi-fm2-wr-bus-width",    .id = AFIFM2_WRCTRL},
>>>>> +     {.reg = "xlnx,afi-fm3-wr-bus-width",    .id = AFIFM3_WRCTRL},
>>>>> +     {.reg = "xlnx,afi-fm4-wr-bus-width",    .id = AFIFM4_WRCTRL},
>>>>> +     {.reg = "xlnx,afi-fm5-wr-bus-width",    .id = AFIFM5_WRCTRL},
>>>>> +     {.reg = "xlnx,afi-fm6-wr-bus-width",    .id = AFIFM6_WRCTRL},
>>>>> +     {.reg = "xlnx,afi-fs-ss0-bus-width",    .id = AFIFS},
>>>>> +     {.reg = "xlnx,afi-fs-ss2-bus-width",    .id = AFIFS_SS2},
>>>>> +     {}
>>>>> +};
>>>>> +
>>>>> +static int zynqmp_afi_config(struct zynqmp_afi *afi_data) {
>>>>> +     struct zynqmp_afi_configreg *cfgptr = afi_cfgreg;
>>>>> +     struct device_node *np = afi_data->of_node;
>>>>> +     u32 afi_ss0_val, afi_ss1_val, bus_width;
>>>>> +     int ret;
>>>>> +
>>>>> +     while (cfgptr->reg) {
>>>>> +             ret = of_property_read_u32(np, cfgptr->reg, &bus_width);
>>>>> +             if (!ret) {
>>>>> +                     if (cfgptr->id == AFIFS_SS2) {
>>>>> +                             if (bus_width == 32)
>>>>> +                                     ret = zynqmp_pm_afi(AFIFS_SS2,
>>>>> +                                                         AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL);
>>>>> +                             else if (bus_width == 64)
>>>>> +                                     ret = zynqmp_pm_afi(AFIFS_SS2,
>>>>> +
>>>> AFIFS_SS0_SS2_BUS_WIDTH_64_CONFIG_VAL);
>>>>> +                             else if (bus_width == 128)
>>>>> +                                     ret = zynqmp_pm_afi(AFIFS_SS2,
>>>>> +
>>>> AFIFS_SS0_SS2_BUS_WIDTH_128_CONFIG_VAL);
>>>>> +                             else
>>>>> +                                     return -EINVAL;
>>>>> +                     } else if (cfgptr->id == AFIFS) {
>>>>> +                             if (bus_width == 32)
>>>>> +                                     afi_ss0_val = AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL;
>>>>> +                             else if (bus_width == 64)
>>>>> +                                     afi_ss0_val =
>>>> AFIFS_SS0_SS2_BUS_WIDTH_64_CONFIG_VAL;
>>>>> +                             else if (bus_width == 128)
>>>>> +                                     afi_ss0_val =
>>>> AFIFS_SS0_SS2_BUS_WIDTH_128_CONFIG_VAL;
>>>>> +                             else
>>>>> +                                     return -EINVAL;
>>>>> +
>>>>> +                             ret = of_property_read_u32(np, "xlnx,afi-fs-ss1-bus-
>>>> width",
>>>>> +                                                        &bus_width);
>>>>> +                             if (!ret) {
>>>>> +                                     if (bus_width == 32)
>>>>> +                                             afi_ss1_val =
>>>> AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL;
>>>>> +                                     else if (bus_width == 64)
>>>>> +                                             afi_ss1_val =
>>>> AFIFS_SS1_BUS_WIDTH_64_CONFIG_VAL;
>>>>> +                                     else if (bus_width == 128)
>>>>> +                                             afi_ss1_val =
>>>> AFIFS_SS1_BUS_WIDTH_128_CONFIG_VAL;
>>>>> +                                     else
>>>>> +                                             return -EINVAL;
>>>>> +
>>>>> +                                     ret = zynqmp_pm_afi(AFIFS, afi_ss1_val |
>>>> afi_ss0_val);
>>>>> +                             }
>>>>> +                     } else {
>>>>> +                             if (bus_width == 32)
>>>>> +                                     ret = zynqmp_pm_afi(cfgptr->id,
>>>>> +                                                         AFIFM_BUS_WIDTH_32_CONFIG_VAL);
>>>>> +                             else if (bus_width == 64)
>>>>> +                                     ret = zynqmp_pm_afi(cfgptr->id,
>>>>> +                                                         AFIFM_BUS_WIDTH_64_CONFIG_VAL);
>>>>> +                             else if (bus_width == 128)
>>>>> +                                     ret = zynqmp_pm_afi(cfgptr->id,
>>>>> +                                                         AFIFM_BUS_WIDTH_128_CONFIG_VAL);
>>>>> +                             else
>>>>> +                                     return -EINVAL;
>>>>> +                     }
>>>>> +             }
>>>>> +             cfgptr++;
>>>>> +     }
>>>>> +
>>>>> +     return 0;
>>>>> +}
>>>>> +
>>>>> +static int zynqmp_afi_enable_set(struct fpga_bridge *bridge, bool
>>>>> +enable) {
>>>>> +     struct device_node *overlay = bridge->info->overlay;
>>>>> +     struct zynqmp_afi *priv = bridge->priv;
>>>>> +     int ret = 0;
>>>>> +
>>>>> +     if (enable) {
>>>>> +             reset_control_reset(priv->resets);
>>>>> +             return 0;
>>>>> +     }
>>>>> +
>>>>> +     of_node_get(overlay);
>>>>> +     priv->of_node =
>>>>> +     of_find_node_with_property(overlay,
>>>>> +                                "xlnx,afi-fm0-rd-bus-width");
>>>>
>>>> I'm a little confused here. The fpga_image_info.overlay is for fpga-region, but
>>>> from your binding doc this property is for this afi device. You want to add
>>>> another overlay targeting afi dev node during reprograming?
>>>>
>>>
>>> Yes, it uses Overlay's(overlay targeting afi dev node). As I said above for design-to-design AFI configs
>>> relevant to the full region may change and these configs must be set prior to program the full region
>>> once this overlay integrated to the live tree the existing afi config values will be replace with the new one's
>>>
>>>>> +     if (priv->of_node)
>>>>> +             ret = zynqmp_afi_config(priv);
>>>>> +     of_node_put(priv->of_node);
>>>>> +
>>>>> +     return ret;
>>>>> +}
>>>>> +
>>>>> +static const struct fpga_bridge_ops zynqmp_afi_br_ops = {
>>>>> +     .enable_set = zynqmp_afi_enable_set, };
>>>>> +
>>>>> +static const struct of_device_id zynqmp_afi_of_match[] = {
>>>>> +     { .compatible =  "xlnx,zynqmp-afi-fpga" },
>>>>> +     { },
>>>>> +};
>>>>> +MODULE_DEVICE_TABLE(of, zynqmp_afi_of_match);
>>>>> +
>>>>> +static int zynqmp_afi_probe(struct platform_device *pdev) {
>>>>> +     struct device *dev = &pdev->dev;
>>>>> +     struct zynqmp_afi *priv;
>>>>> +     struct fpga_bridge *br;
>>>>> +
>>>>> +     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
>>>>> +     if (!priv)
>>>>> +             return -ENOMEM;
>>>>> +
>>>>> +     priv->dev = dev;
>>>>> +
>>>>> +     priv->resets =
>>>> devm_reset_control_array_get_optional_exclusive(&pdev->dev);
>>>>> +     if (IS_ERR(priv->resets))
>>>>> +             return PTR_ERR(priv->resets);
>>>>> +
>>>>> +     br = fpga_bridge_register(dev, "Xilinx ZynqMP AFI",
>>>>> +                               &zynqmp_afi_br_ops, priv);
>>>>> +     if (IS_ERR(br)) {
>>>>> +             dev_err(dev, "unable to register Xilinx ZynqMP AFI");
>>>>
>>>> Need a "\n" at the end?
>>>>
>>>
>>> Will fix.
>>>
>>> Regards,
>>> Navakishore.
>>>
>>
>> Thanks,
>> Marco
>>
> 

Re: [PATCH 4/4] fpga: zynqmp: Add afi config driver

[Xu Yilun]

On 2022-08-30 at 09:19:52 +0000, Manne, Nava kishore wrote:
> Hi Yilun,
> 
> 	Please find my response inline.
> 
> > -----Original Message-----
> > From: Xu Yilun <yilun.xu@intel.com>
> > Sent: Saturday, August 27, 2022 5:56 PM
> > To: Manne, Nava kishore <nava.kishore.manne@amd.com>
> > Cc: git (AMD-Xilinx) <git@amd.com>; robh+dt@kernel.org;
> > krzysztof.kozlowski+dt@linaro.org; michal.simek@xilinx.com;
> > mdf@kernel.org; hao.wu@intel.com; trix@redhat.com;
> > p.zabel@pengutronix.de; gregkh@linuxfoundation.org;
> > ronak.jain@xilinx.com; rajan.vaja@xilinx.com;
> > abhyuday.godhasara@xilinx.com; piyush.mehta@xilinx.com;
> > lakshmi.sai.krishna.potthuri@xilinx.com; harsha.harsha@xilinx.com;
> > linus.walleij@linaro.org; nava.manne@xilinx.com;
> > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> > kernel@vger.kernel.org; linux-fpga@vger.kernel.org
> > Subject: Re: [PATCH 4/4] fpga: zynqmp: Add afi config driver
> > 
> > CAUTION: This message has originated from an External Source. Please use
> > proper judgment and caution when opening attachments, clicking links, or
> > responding to this email.
> > 
> > 
> > On 2022-08-24 at 09:25:42 +0530, Nava kishore Manne wrote:
> > > Add zynqmp AXI FIFO interface(AFI) config driver. This is useful for
> > > the configuration of the PS-PL interface on Zynq US+ MPSoC platform.
> > 
> > Please help illustrate how to use the device for FPGA reprogramming, why it
> > should be implemented as an FPGA bridge.
> > 
> > From the code I actually didn't see any operation that gates the fpga-region
> > from other part of the machine.
> > 
> 
> The Zynq UltraScale MPSoC family consists of a system-on-chip (SoC) style integrated processing system (PS)
> and a Programmable Logic (PL) unit, providing an extensible and flexible SoC solution on a single die. 
> Xilinx Zynq US+ MPSoC connect the PS to the programmable logic (PL) through the AXI port. 
> This AXI port helps to establish the data path between the PS and PL (Here AXI Interface act as a Gating between PS and PL)
> and this AXI port configuration vary from design to design.  In-order to establish the proper communication path between
> PS and PL (Full region),  the AXI port data path should be configured with proper values priories to load the full region.
> 
> Will update the description in v2.
> 
> > >
> > > Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
> > > ---
> > >  MAINTAINERS               |   6 ++
> > >  drivers/fpga/Kconfig      |  13 +++
> > >  drivers/fpga/Makefile     |   1 +
> > >  drivers/fpga/zynqmp-afi.c | 211
> > > ++++++++++++++++++++++++++++++++++++++
> > >  4 files changed, 231 insertions(+)
> > >  create mode 100644 drivers/fpga/zynqmp-afi.c
> > >
> > > diff --git a/MAINTAINERS b/MAINTAINERS index
> > > 20ffac651214..957e753e6406 100644
> > > --- a/MAINTAINERS
> > > +++ b/MAINTAINERS
> > > @@ -8032,6 +8032,12 @@ F:     Documentation/fpga/
> > >  F:   drivers/fpga/
> > >  F:   include/linux/fpga/
> > >
> > > +FPGA ZYNQMP PS-PL BRIDGE DRIVER
> > > +M:   Nava kishore Manne <nava.kishore.manne@amd.com>
> > > +S:   Supported
> > > +F:   Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
> > > +F:   drivers/fpga/zynqmp-afi.c
> > > +
> > >  INTEL MAX10 BMC SECURE UPDATES
> > >  M:   Russ Weight <russell.h.weight@intel.com>
> > >  L:   linux-fpga@vger.kernel.org
> > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index
> > > 6c416955da53..c08794d30fb5 100644
> > > --- a/drivers/fpga/Kconfig
> > > +++ b/drivers/fpga/Kconfig
> > > @@ -130,6 +130,19 @@ config XILINX_PR_DECOUPLER
> > >         reconfiguration, preventing the system deadlock that can
> > >         occur if AXI transactions are interrupted by DFX.
> > >
> > > +config ZYNQMP_AFI
> > > +     tristate "Xilinx ZYNQMP AFI support"
> > > +     depends on FPGA_BRIDGE
> > > +     help
> > > +       Say Y to enable drivers to handle the PS-PL clocks configurations
> > > +       and PS-PL Bus-width. Xilinx Zynq US+ MPSoC connect the PS to the
> > > +       programmable logic (PL) through the AXI port. This AXI port helps
> > > +       to establish the data path between the PS and PL.
> > > +       In-order to establish the proper communication path between PS and
> > PL,
> > > +       the AXI port data path should be configured with the proper Bus-
> > width
> > > +       values and it will also handles the PS-PL reset signals to reset the
> > > +       PL domain.
> > 
> > Same concern, please describe its relationship to FPGA reprogramming.
> > 
> 
> Same as above.
> Will update the description in v2.
> 
> > > +
> > >  config FPGA_REGION
> > >       tristate "FPGA Region"
> > >       depends on FPGA_BRIDGE
> > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index
> > > 42ae8b58abce..94cfe60972db 100644
> > > --- a/drivers/fpga/Makefile
> > > +++ b/drivers/fpga/Makefile
> > > @@ -31,6 +31,7 @@ obj-$(CONFIG_FPGA_BRIDGE)           += fpga-bridge.o
> > >  obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE)    += altera-hps2fpga.o altera-
> > fpga2sdram.o
> > >  obj-$(CONFIG_ALTERA_FREEZE_BRIDGE)   += altera-freeze-bridge.o
> > >  obj-$(CONFIG_XILINX_PR_DECOUPLER)    += xilinx-pr-decoupler.o
> > > +obj-$(CONFIG_ZYNQMP_AFI)             += zynqmp-afi.o
> > >
> > >  # High Level Interfaces
> > >  obj-$(CONFIG_FPGA_REGION)            += fpga-region.o
> > > diff --git a/drivers/fpga/zynqmp-afi.c b/drivers/fpga/zynqmp-afi.c new
> > > file mode 100644 index 000000000000..bc975d304039
> > > --- /dev/null
> > > +++ b/drivers/fpga/zynqmp-afi.c
> > > @@ -0,0 +1,211 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + * Copyright (C) 2022 Xilinx, Inc.
> > > + */
> > > +
> > > +#include <linux/err.h>
> > > +#include <linux/firmware/xlnx-zynqmp.h> #include
> > > +<linux/fpga/fpga-bridge.h> #include <linux/io.h> #include
> > > +<linux/module.h> #include <linux/of.h> #include
> > > +<linux/platform_device.h> #include <linux/reset.h> #include
> > > +<linux/slab.h>
> > > +
> > > +/* Registers and special values for doing register-based operations */
> > > +#define AFI_RDCHAN_CTRL_OFFSET       0x00
> > > +#define AFI_WRCHAN_CTRL_OFFSET       0x14
> > > +#define AFI_BUSWIDTH_MASK    BIT(0)
> > > +
> > > +/**
> > > + * struct zynqmp_afi - AFI register description.
> > > + * @dev: device that owns this.
> > > + * @of_node: Device Tree overlay.
> > > + * @resets: Pointer to the reset control for ps-pl resets.
> > > + */
> > > +struct zynqmp_afi {
> > > +     struct device *dev;
> > > +     struct device_node *of_node;
> > > +     struct reset_control *resets;
> > > +};
> > > +
> > > +/**
> > > + * struct zynqmp_afi_configreg - AFI configuration registers info.
> > > + * @reg:     Name of the AFI configuration register.
> > > + * @id:              Register index value.
> > > + */
> > > +struct zynqmp_afi_configreg {
> > > +     char *reg;
> > > +     u32 id;
> > > +};
> > > +
> > > +static struct zynqmp_afi_configreg afi_cfgreg[] = {
> > > +     {.reg = "xlnx,afi-fm0-rd-bus-width",    .id = AFIFM0_RDCTRL},
> > > +     {.reg = "xlnx,afi-fm1-rd-bus-width",    .id = AFIFM1_RDCTRL},
> > > +     {.reg = "xlnx,afi-fm2-rd-bus-width",    .id = AFIFM2_RDCTRL},
> > > +     {.reg = "xlnx,afi-fm3-rd-bus-width",    .id = AFIFM3_RDCTRL},
> > > +     {.reg = "xlnx,afi-fm4-rd-bus-width",    .id = AFIFM4_RDCTRL},
> > > +     {.reg = "xlnx,afi-fm5-rd-bus-width",    .id = AFIFM5_RDCTRL},
> > > +     {.reg = "xlnx,afi-fm6-rd-bus-width",    .id = AFIFM6_RDCTRL},
> > > +     {.reg = "xlnx,afi-fm0-wr-bus-width",    .id = AFIFM0_WRCTRL},
> > > +     {.reg = "xlnx,afi-fm1-wr-bus-width",    .id = AFIFM1_WRCTRL},
> > > +     {.reg = "xlnx,afi-fm2-wr-bus-width",    .id = AFIFM2_WRCTRL},
> > > +     {.reg = "xlnx,afi-fm3-wr-bus-width",    .id = AFIFM3_WRCTRL},
> > > +     {.reg = "xlnx,afi-fm4-wr-bus-width",    .id = AFIFM4_WRCTRL},
> > > +     {.reg = "xlnx,afi-fm5-wr-bus-width",    .id = AFIFM5_WRCTRL},
> > > +     {.reg = "xlnx,afi-fm6-wr-bus-width",    .id = AFIFM6_WRCTRL},
> > > +     {.reg = "xlnx,afi-fs-ss0-bus-width",    .id = AFIFS},
> > > +     {.reg = "xlnx,afi-fs-ss2-bus-width",    .id = AFIFS_SS2},
> > > +     {}
> > > +};
> > > +
> > > +static int zynqmp_afi_config(struct zynqmp_afi *afi_data) {
> > > +     struct zynqmp_afi_configreg *cfgptr = afi_cfgreg;
> > > +     struct device_node *np = afi_data->of_node;
> > > +     u32 afi_ss0_val, afi_ss1_val, bus_width;
> > > +     int ret;
> > > +
> > > +     while (cfgptr->reg) {
> > > +             ret = of_property_read_u32(np, cfgptr->reg, &bus_width);
> > > +             if (!ret) {
> > > +                     if (cfgptr->id == AFIFS_SS2) {
> > > +                             if (bus_width == 32)
> > > +                                     ret = zynqmp_pm_afi(AFIFS_SS2,
> > > +                                                         AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL);
> > > +                             else if (bus_width == 64)
> > > +                                     ret = zynqmp_pm_afi(AFIFS_SS2,
> > > +
> > AFIFS_SS0_SS2_BUS_WIDTH_64_CONFIG_VAL);
> > > +                             else if (bus_width == 128)
> > > +                                     ret = zynqmp_pm_afi(AFIFS_SS2,
> > > +
> > AFIFS_SS0_SS2_BUS_WIDTH_128_CONFIG_VAL);
> > > +                             else
> > > +                                     return -EINVAL;
> > > +                     } else if (cfgptr->id == AFIFS) {
> > > +                             if (bus_width == 32)
> > > +                                     afi_ss0_val = AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL;
> > > +                             else if (bus_width == 64)
> > > +                                     afi_ss0_val =
> > AFIFS_SS0_SS2_BUS_WIDTH_64_CONFIG_VAL;
> > > +                             else if (bus_width == 128)
> > > +                                     afi_ss0_val =
> > AFIFS_SS0_SS2_BUS_WIDTH_128_CONFIG_VAL;
> > > +                             else
> > > +                                     return -EINVAL;
> > > +
> > > +                             ret = of_property_read_u32(np, "xlnx,afi-fs-ss1-bus-
> > width",
> > > +                                                        &bus_width);
> > > +                             if (!ret) {
> > > +                                     if (bus_width == 32)
> > > +                                             afi_ss1_val =
> > AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL;
> > > +                                     else if (bus_width == 64)
> > > +                                             afi_ss1_val =
> > AFIFS_SS1_BUS_WIDTH_64_CONFIG_VAL;
> > > +                                     else if (bus_width == 128)
> > > +                                             afi_ss1_val =
> > AFIFS_SS1_BUS_WIDTH_128_CONFIG_VAL;
> > > +                                     else
> > > +                                             return -EINVAL;
> > > +
> > > +                                     ret = zynqmp_pm_afi(AFIFS, afi_ss1_val |
> > afi_ss0_val);
> > > +                             }
> > > +                     } else {
> > > +                             if (bus_width == 32)
> > > +                                     ret = zynqmp_pm_afi(cfgptr->id,
> > > +                                                         AFIFM_BUS_WIDTH_32_CONFIG_VAL);
> > > +                             else if (bus_width == 64)
> > > +                                     ret = zynqmp_pm_afi(cfgptr->id,
> > > +                                                         AFIFM_BUS_WIDTH_64_CONFIG_VAL);
> > > +                             else if (bus_width == 128)
> > > +                                     ret = zynqmp_pm_afi(cfgptr->id,
> > > +                                                         AFIFM_BUS_WIDTH_128_CONFIG_VAL);
> > > +                             else
> > > +                                     return -EINVAL;
> > > +                     }
> > > +             }
> > > +             cfgptr++;
> > > +     }
> > > +
> > > +     return 0;
> > > +}
> > > +
> > > +static int zynqmp_afi_enable_set(struct fpga_bridge *bridge, bool
> > > +enable) {
> > > +     struct device_node *overlay = bridge->info->overlay;
> > > +     struct zynqmp_afi *priv = bridge->priv;
> > > +     int ret = 0;
> > > +
> > > +     if (enable) {
> > > +             reset_control_reset(priv->resets);
> > > +             return 0;
> > > +     }
> > > +
> > > +     of_node_get(overlay);
> > > +     priv->of_node =
> > > +     of_find_node_with_property(overlay,
> > > +                                "xlnx,afi-fm0-rd-bus-width");
> > 
> > I'm a little confused here. The fpga_image_info.overlay is for fpga-region, but
> > from your binding doc this property is for this afi device. You want to add
> > another overlay targeting afi dev node during reprograming?
> > 
> 
> Yes, it uses Overlay's(overlay targeting afi dev node). As I said above for design-to-design AFI configs

I have concern on it. We should limit the overlay usage only on
fpga_region, this is because we are changing the hardware in this
region during reprograming. Adding overlays for other nodes could be
easily abused, any changes could be made even not related to the fpga
region. So if any cross device configurations should be made during
reprograming, it should be initiated by fpga region driver through
normal kernel APIs.

Thanks,
Yilun

> relevant to the full region may change and these configs must be set prior to program the full region
> once this overlay integrated to the live tree the existing afi config values will be replace with the new one's
> 
> > > +     if (priv->of_node)
> > > +             ret = zynqmp_afi_config(priv);
> > > +     of_node_put(priv->of_node);
> > > +
> > > +     return ret;
> > > +}
> > > +
> > > +static const struct fpga_bridge_ops zynqmp_afi_br_ops = {
> > > +     .enable_set = zynqmp_afi_enable_set, };
> > > +
> > > +static const struct of_device_id zynqmp_afi_of_match[] = {
> > > +     { .compatible =  "xlnx,zynqmp-afi-fpga" },
> > > +     { },
> > > +};
> > > +MODULE_DEVICE_TABLE(of, zynqmp_afi_of_match);
> > > +
> > > +static int zynqmp_afi_probe(struct platform_device *pdev) {
> > > +     struct device *dev = &pdev->dev;
> > > +     struct zynqmp_afi *priv;
> > > +     struct fpga_bridge *br;
> > > +
> > > +     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> > > +     if (!priv)
> > > +             return -ENOMEM;
> > > +
> > > +     priv->dev = dev;
> > > +
> > > +     priv->resets =
> > devm_reset_control_array_get_optional_exclusive(&pdev->dev);
> > > +     if (IS_ERR(priv->resets))
> > > +             return PTR_ERR(priv->resets);
> > > +
> > > +     br = fpga_bridge_register(dev, "Xilinx ZynqMP AFI",
> > > +                               &zynqmp_afi_br_ops, priv);
> > > +     if (IS_ERR(br)) {
> > > +             dev_err(dev, "unable to register Xilinx ZynqMP AFI");
> > 
> > Need a "\n" at the end?
> > 
> 
> Will fix.
> 
> Regards,
> Navakishore.
> 

Re: [PATCH 0/4]Add afi config drivers support

[Xu Yilun]

On 2022-08-24 at 09:25:38 +0530, Nava kishore Manne wrote:
> Xilinx SoC platforms (Zynq and ZynqMP) connect the PS to the programmable

Could you help explain what is PS?

Thanks,
Yiljn

> logic (PL) through the AXI port.This AXI port helps to establish the data
> path between the PS and PL. In-order to establish the proper communication
> data path between PS and PL the AXI port data path should be configured
> with the proper Bus-width values and it will also handle the PS-PL reset
> signals to reset the PL domain.
> 
> This patch series adds afi config drivers support to handle the PS-PL
> resets and AXI port bus-width configurations.
> 
> Nava kishore Manne (4):
>   firmware: xilinx: Add afi ioctl support
>   bindings: fpga: Add binding doc for the zynqmp afi config driver
>   bindings: firmware: Update binding doc for the zynqmp afi config node
>   fpga: zynqmp: Add afi config driver
> 
>  .../firmware/xilinx/xlnx,zynqmp-firmware.yaml |   7 +
>  .../bindings/fpga/xlnx,zynqmp-afi-fpga.yaml   | 100 +++++++++
>  MAINTAINERS                                   |   6 +
>  drivers/firmware/xilinx/zynqmp.c              |  14 ++
>  drivers/fpga/Kconfig                          |  13 ++
>  drivers/fpga/Makefile                         |   1 +
>  drivers/fpga/zynqmp-afi.c                     | 211 ++++++++++++++++++
>  include/linux/firmware/xlnx-zynqmp.h          |  36 +++
>  8 files changed, 388 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
>  create mode 100644 drivers/fpga/zynqmp-afi.c
> 
> -- 
> 2.25.1
> 

RE: [PATCH 0/4]Add afi config drivers support

[Manne, Nava kishore]

Hi Yilun,

	Please find my response inline.

> -----Original Message-----
> From: Xu Yilun <yilun.xu@intel.com>
> Sent: Saturday, August 27, 2022 11:33 AM
> To: Manne, Nava kishore <nava.kishore.manne@amd.com>
> Cc: git (AMD-Xilinx) <git@amd.com>; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; michal.simek@xilinx.com;
> mdf@kernel.org; hao.wu@intel.com; trix@redhat.com;
> p.zabel@pengutronix.de; gregkh@linuxfoundation.org;
> ronak.jain@xilinx.com; rajan.vaja@xilinx.com;
> abhyuday.godhasara@xilinx.com; piyush.mehta@xilinx.com;
> lakshmi.sai.krishna.potthuri@xilinx.com; harsha.harsha@xilinx.com;
> linus.walleij@linaro.org; nava.manne@xilinx.com;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; linux-fpga@vger.kernel.org
> Subject: Re: [PATCH 0/4]Add afi config drivers support
> 
> CAUTION: This message has originated from an External Source. Please use
> proper judgment and caution when opening attachments, clicking links, or
> responding to this email.
> 
> 
> On 2022-08-24 at 09:25:38 +0530, Nava kishore Manne wrote:
> > Xilinx SoC platforms (Zynq and ZynqMP) connect the PS to the
> > programmable
> 
> Could you help explain what is PS?
> 

The Zynq UltraScale MPSoC family consists of a system-on-chip (SoC) style integrated processing system (PS)
and a Programmable Logic (PL) unit, providing an extensible and flexible SoC solution on a single die.

Will add PS description in next version.

Regards,
Navakishore.